KR100623791B1 - Liquid crystal display device and method for lcd driving - Google Patents

Abstract

The present invention discloses a liquid crystal display device and a driving method thereof capable of preventing a delay of a data signal applied to the liquid crystal display device and preventing a signal distortion from an electromagnetic interference (EMI). The disclosed invention includes a timing controller for generating a data signal; Signal wires for separately dividing and transmitting data signals generated from the timing controller; A plurality of source drive ICs for processing data signals transmitted from the signal wires; And a liquid crystal panel configured to sequentially sample data signals processed by the source drive ICs to display an image.

Here, the signal lines are divided into four independent signal lines to correspond to the four divisions of the liquid crystal panel, and source drive ICs are electrically connected to correspond to the divided regions of the signal lines, respectively. Are divided into an odd number and an even number to transmit positive and negative data signals generated from the timing controller.

LCD, Drive, Delay, Signal, Source Drive IC

Description

Liquid crystal display and its driving method {LIQUID CRYSTAL DISPLAY DEVICE AND METHOD FOR LCD DRIVING}

1 is a view showing a liquid crystal display drive system according to the prior art.

2 is a view showing a source drive driving system of a liquid crystal display according to the prior art.

3 is a diagram showing the structure of signal wiring for transmitting a data signal from a timing controller to a source drive IC according to the prior art;

4 is a view showing a source drive driving system of a liquid crystal display according to the present invention;

5 is a diagram showing the structure of signal wiring for transmitting a data signal from a timing controller to a source drive IC according to the present invention;

6 is a view showing a source drive driving system that can prevent the EMI phenomenon in another embodiment according to the present invention.

7 is a view for explaining another embodiment of the present invention.

* Description of the symbols for the main parts of the drawings *

200: LCD panel 210: timing controller

201: source drive IC 201a: first latch portion

201b: second latch portion 201c: level shifter

201d: Digital-to-Analog Converter 201e: Buffer Section

The present invention relates to a liquid crystal display device, and more particularly, to a liquid crystal display device and a driving method thereof, which can prevent a delay of a data signal applied to the liquid crystal display device and prevent signal distortion caused by electromagnetic interference (EMI). It is about.

Liquid crystal display device, a kind of flat panel display device, uses the electrical characteristics of liquid crystal whose light transmittance varies according to the voltage applied to each pixel. Therefore, it is widely used not only as a portable computer but also as a monitor of a desktop computer.

A liquid crystal display device having such a characteristic includes an LCD panel that displays an image by image signals and light, a printed circuit board (PCB) that transmits image signals necessary for displaying images to the LCD panel, and a light toward the LCD panel. Guiding backlight assembly and other fixtures for securing these members.

Among these members, the LCD panel and the printed circuit board are electrically connected to a plurality of source and gate drive ICs, and various components such as a controller are mounted on the printed circuit board.

Here, when the data signal generated by the source drive IC and the drive signal generated by the gate drive IC are applied to each pixel of the LCD panel, the drive signal is a thin film transistor through a gate line formed on the LCD panel. Is applied to the gate electrode of " TFT ", thereby turning the TFT on or off.

On the other hand, the data signal flowing along the data lines formed in the LCD panel is applied to the pixel electrode only when the TFT is turned on by the drive signal, thereby changing the arrangement state of the liquid crystal existing between the pixel electrode and the counter electrode, Adjust the amount of light transmitted.

1 is a view showing a liquid crystal display driving system according to the prior art.

As illustrated in FIG. 1, in the driving system of the liquid crystal display 100, predetermined color data and control signals are input to the controller 110, and DC power is provided to the power supply unit 120.

When DC power is applied to the power supply unit 120, the power supply unit 120 supplies a constant voltage necessary for the operation of the controller 110, the gray scale generator 130, and the gate voltage generator 140.

Here, the controller 110 outputs various control signals and data for determining the gray level for each pixel to the source drive part 200 electrically connected to the LCD panel 160, and also the gate drive part 150. Configured to output control signals.

In addition, the gray generator 130 is configured to supply a gray voltage to the source drive part 200, and the gate voltage generator 140 is turned on / turned off to the gate drive part 150. Turn Off) Supply voltage for voltage generation.

In addition, the gate and source drive parts 150 and 200 electrically connected to the LCD panel 160 generate a gate signal and a data signal, respectively, and apply the gate signal and the data signal to the LCD panel 160.

In addition, the LCD panel 160 is formed by crossing the gate wiring 162 and the data wirings 164 with each other, and TFTs 166 are formed at these intersections, respectively. It is applied to the gate electrode of the TFT 166 and the data signal is applied to the source electrode through the data lines 164, the liquid crystal capacitor (Clc) and the storage capacitor (Cs) is formed on the drain electrode side.

On the other hand, the gate drive part 150 is electrically connected to a plurality of gate drive ICs for generating a drive signal. Each gate drive IC includes a shift register and a level shift and amplification unit, although not shown in the drawing.

Although not shown in the drawing, a plurality of source drive ICs are electrically connected to the source drive part 200, and each source drive IC includes a latch unit, a level shifter, a digital / analog converter, and a buffer unit.

2 is a view showing a source drive driving system of a liquid crystal display according to the prior art.

As shown in FIG. 2, when a data signal is applied to the source drive IC 170 by a timing controller (T-CON) 180 embedded in the controller of the liquid crystal display, the source drive IC 170 may be applied. In the present invention, an image is displayed by sequentially sampling data signals on the LCD panel 160.

The timing controller 180 arranges the data signals in a form suitable for driving in accordance with a dot inversion scheme, and then outputs the data signals to the respective source drive ICs 170.

The data signals R, G, and B aligned by the timing controller 180 are transmitted to the source drive IC 170 along a plurality of signal wires formed to be divided based on the center of the LCD panel 160. .

As described above, data signals are transmitted to a region divided by the center of the LCD panel 160 through a plurality of signal wires, and the plurality of source drive ICs 170 connected to the divided signal wires apply a data signal. The data signal is sequentially output on the LCD panel 160.

The data signal transmitted from the timing controller 180 is adjusted together with the gamma voltage applied to the source drive IC 170, and then the data signal is sequentially output by sampling the data signal to the LCD panel 160. To the latch portion 170a, the second latching portion 170b, the level shifter 170c, the digital / analog converter 170d and the output buffer 170e. It is.

The first latch unit 170a receives a data signal transmitted through a signal wire, and then outputs the data signal to the second latch unit 170b. The second latch unit 170b holds the data signal.

The reason for holding the data signal in the second latch unit 170b is to sequentially fill the data signals in all the source drive ICs 170 and then simultaneously output them to the level shifter 170c. to be.

The data signal output from the second latch unit 170b is amplified by the level shifter 170c and then output to the digital / analog converter 170d.

The digital-to-analog converter 170d converts R, G, and B data signals, which are digital signals, into analog signals. At this time, the gray voltage output from the gray voltage generator is reflected.

The gradation voltage reflected by the digital / analog converter 170d is output to the buffer unit 170e, and the buffer unit 170e outputs the gray level voltage to the LCD panel 160 in order to sequentially form a pixel area of a matrix. Is approved.

In FIG. 2, the data signal is transmitted to both edge regions of the LCD panel 160. Since a signal delay occurs, the LCD panel 160 is divided into two regions to transmit the data signal.

3 is a diagram illustrating a structure of a signal line for transmitting a data signal from a timing controller to a source drive IC according to the related art.

As shown in FIG. 3, the LCD panel is divided into two parts, and a data signal transmitted from a timing controller is transmitted from a source drive IC disposed in the divided area.

That is, when a data signal is transmitted from the timing controller to the signal line along the data line buffers 190, the source drive IC applies the data signal using signal lines electrically connected to the signal lines. Receive.

The applied data signal is processed according to the signal processing procedure of the source drive IC described in FIG. 2, and then sequentially outputs the data signal to the LCD panel.

In this case, since a plurality of source drive ICs are sequentially connected to the signal wires drawn from the timing controller, the source drive ICs receive data signals from the signal wires in sequence.

In the figure, 185, which is illustrated but not described, is a shift register, and 172 is a latch portion of the source drive IC.

However, in the conventional technology as described above, source drive ICs are sequentially connected to a plurality of signal wires drawn from the timing controller, and a large load is applied from the signal wire position.

Thus, a problem arises in that a large load applied to the signal wiring increases the signal delay and lowers the driving reliability.

Such a large load has a problem of increasing the delay of the data signal in the source drive IC disposed at the edge farthest from the source drive IC disposed close to the timing controller.

In addition, since a data signal is transmitted to each of the signal wires, and each data signal is transmitted to the entire signal wire of the same length, there is a disadvantage in that the parasitic resistance and the parasitic capacitor greatly affect the signal.

As a liquid crystal display device becomes larger and higher in recent years, such a load between signal wires increases power consumption and greatly affects image quality.

The present invention prevents signal delay by doubling the number of signal wires that transmit data signals from the timing controller to the source drive IC, and again sampling the data signals by dividing each of the signals into two divided regions based on the LCD panel. And a liquid crystal display and a driving method thereof capable of improving image quality due to load reduction.

In order to achieve the above object, the liquid crystal display device according to the present invention,

A timing controller for generating a data signal;

Signal wires for separately dividing and transmitting data signals generated from the timing controller;

A plurality of source drive ICs for processing data signals transmitted from the signal wires;

And a liquid crystal panel configured to sequentially sample data signals processed by the source drive ICs to display an image.

Here, the signal lines are divided into four independent signal lines to correspond to the four divisions of the liquid crystal panel, and source drive ICs are electrically connected to correspond to the divided regions of the signal lines, respectively. Are divided into an odd number and an even number to transmit positive and negative data signals generated from the timing controller.

The signal wires are loaded between the signal wires by transmitting positive and negative data signals along odd or even wires to prevent electromagnetic interference (EMI) and transmitting data signals to the divided signal wires. (load) It is characterized in that the load can be reduced.

In the liquid crystal display device according to the present invention,

A timing controller for generating data signals in red, green, and blue;

Signal wires for dividing and transmitting different data signals generated from the timing controller into odd or even wires, respectively;

A plurality of source drive ICs for sampling the data signal transmitted from the signal lines into a pixel signal;

And a liquid crystal panel displaying an image by pixel signals sampled from the source drive ICs.

Here, the signal lines are divided into four independent lines so as to correspond to four division regions of the liquid crystal panel. The data signals generated by the timing controller are positive and negative data signals, and the source drive ICs include signal lines. It is characterized in that it is connected to the odd or even signal wiring of each.

The source drive ICs selectively process a positive or negative data signal transmitted from the odd or even signal wires, and the signal wires are divided into odd or even wires in an area divided into four independent wires. It is characterized by.

In addition, the liquid crystal display device driving method according to another embodiment of the present invention,

Generating a data signal from a timing controller of the liquid crystal display device;

Transmitting the data signal generated from the timing controller to signal wires divided into a plurality of areas;

Receiving a data signal from the divided signal wires and performing signal processing on source drive ICs;

And outputting a data signal processed by each of the source drive ICs to a liquid crystal panel to display an image.

Here, the timing controller selectively generates positive and negative data signals, and the source drive ICs selectively process positive and negative data signals, respectively, to prevent signal distortion due to electromagnetic interference (EMI). The display area of the liquid crystal panel is divided and displayed to correspond to signals transmitted along the divided signal lines.

The liquid crystal panel displays an image by a positive or negative data signal, and prevents a delay of a data signal applied to the liquid crystal panel by dividing the signal wires.

According to the present invention, the signal delay is doubled by doubling the number of signal wires for transmitting the data signal from the timing controller to the source drive IC, and again sampling the data signal by dividing the data signal into two divided regions based on the LCD panel. Image quality can be improved due to prevention and reduced load.

Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings.

4 is a view illustrating a source drive driving system of a liquid crystal display according to the present invention.

As shown in FIG. 4, the signal wires drawn from the timing controller 210 are divided into two sides based on the center of the LCD panel 200, and the signal wires are divided into two parts in the divided region. It is divided.

Therefore, the LCD panel 200 is divided into four regions and a data sampling signal is applied.

In the prior art, the signal wires were divided into two sides of the timing controller 210, but in the present invention, the number of signal wires is doubled, and in the area divided into two around the LCD panel 200, the signal wires are divided into four parts. The divided data signal can be applied to the LCD panel 200.

Therefore, the data signal applied from the timing controller 210 is transmitted to each of four regions by four divided signal wires. Therefore, since the number of the source drive ICs 201 electrically connected to the four signal wires divided by four is twice as much as before, the load cap generated in the signal wires is reduced.

  When a data signal is transmitted from the timing controller 210 along the signal wires, a reduction in the load cap occurring between the signal wires is the size of the buffer buffering the data signal to apply to the source drive ICs 201. There is an advantage to reduce.

In addition, reducing the load cap between the signal lines reduces the frequency of the data signal applied to the source drive ICs, respectively, so that a fast data signal can be transmitted without signal delay.

In addition, the reduction of the load cap applied to each of the signal wires may reduce signal attenuation, thereby reducing power consumption of the system as a whole.

Referring to the drawing shown in FIG. 4, the number of source drive ICs 201 disposed in the LCD panel 200 is the same, but sources connected to each of the four divided signal wires drawn from the timing controller 210. It can be seen that the number of drive ICs 201 has decreased.

Since the source drive ICs 201 respectively connected to the divided signal wires latch the data signal corresponding to the quarter area of the LCD panel 200 and sequentially sample the data signal to the LCD panel 200. It is advantageous in that signal processing is fast and a large load is not applied between the signal wires.

The process of transmitting signals from the timing controller 210 to the LCD panel 200 according to the 4-split signal wiring structure proposed by the present invention is as follows.

First, the structure of signal wires drawn out from the timing controller 210 is divided into two sides on both sides of the center of the LCD panel 200. It is further divided into two divided regions and divided into four divided regions as a whole.

Data signals are independently transmitted to the four divided regions of the signal wires, and source drive ICs 201 are divided into four groups and connected to each of the divided signal wires.

Each of the four divided signal wires transmits a data signal transmitted from the timing controller 210 to the first latch 201a of the source drive ICs 201 connected to the signal wires. The data signal transmitted to the first latch unit 201a is transferred to a second latching latch 201b to hold the data signal.

When the data signal held by the second latch unit 201b is output, the signal is amplified by the level shifter 201c and then output to the digital / analog converter 201d.

The digital-to-analog converter 201d converts the data signals R, G, and B, which are digital signals, into analog signals. In this case, the gray voltage output from the gray voltage generator is reflected.

The gradation voltage reflected by the digital / analog converter 201d is output to the output buffer 201e, and the buffer unit 201e applies a signal to the LCD panel 200 to apply an image. .

In this case, since data signals are sampled independently of each other so as to correspond to the divided regions on the basis of the LCD panel 200, the buffer units 201e of the source drive ICs 201 divided into four regions are adjacent to other source drives. The timing signal is applied to the buffer units 201e of the ICs 201 to apply the data signal to the quadrant region of the LED panel 200.

5 is a diagram illustrating the structure of signal wires for transmitting data signals from a timing controller to a source drive IC according to the present invention.

As shown in FIG. 5, the area in which the data signal is sampled on the LCD panel is divided into two centers of the panel, and the divided area is divided into two and divided into four divided areas as a whole.

Correspondingly, signal wires drawn from the timing controller are also divided into four divided regions.

Therefore, when the divided signal lines corresponding to the divided region around the LCD panel are enlarged, the signal lines are formed twice as many as before, and each of them is divided into the A region and the B region. have.

In the region A, the source drive ICs are independently connected, and in the region B, the source drive ICs are independently connected, so that the data signals are sequentially sampled for the 1/4 region of the LCD panel.

The number of signal wires drawn out from the timing controller is twice, but each wire is divided into two parts, and since only one quarter of the source drive ICs are connected to the divided wires, the load applied to the signal wires is known in the prior art. It is cut in half compared to

This doubling of the load on the signal wires has the advantage of reducing the size of the buffer connected between the timing controller and the signal wires.

That is, the data signal transmitted from the timing controller transfers the data signal to the signal wires divided through the data line buffer 209 disposed at the input terminal of the signal wire. When the number of source drive ICs connected to the IC is smaller than that of the related art, a smaller buffer size can be used for driving.

In addition, the shift registers 205 disposed along the signal lines also have an advantage of reducing signal delay and signal distortion because the data signals are shifted only in regions corresponding to the divided source drive ICs.

Although not shown in the drawing, reference numeral 202 denotes a latch portion of the source drive IC.

FIG. 6 is a diagram illustrating a source drive driving system capable of preventing an EMI phenomenon according to another embodiment of the present invention.

As shown in FIG. 6, a signal line for applying a data signal from a timing controller 210 to the source drive ICs 301 is divided into two centers around the LCD panel 200, and at this time, a divided signal. The wirings are arranged separately from odd wiring odd and even wiring.

Therefore, the source drive ICs 301 disposed in the divided region are alternately applied with the data signals from the even and odd signal lines to sample the data signals.

 For example, a positive data signal is sampled in the odd-numbered signal line odd, and a negative data signal sampled in the even-numbered signal line even.

That is, when the change amount of the data signal is determined from the timing controller 210 and selectively outputs the negative data signal or the positive data signal, the source drive ICs 301 respectively disposed in the divided region are selectively negative. The data signal or the positive data signal is sampled.

The source drive ICs 301 disposed in the divided area with respect to the LCD panel 200 receive a signal from an odd signal line or even signal line selectively according to the amount of data change. As a result, the throughput in each source drive IC 301 is reduced.

When the source drive ICs 301 sample the data signals in this manner, a signal defect due to EMI can be prevented because the amount of change among the data signals transmitted to the signal wire is smaller than in the related art.

Although not shown in the figure, 301a, 301b, 301c, 301d, and 301e, which are not described, represent the first latch portion, the second latch portion, the level shifter, the digital / analog converter, and the buffer portion of the source drive IC described in FIG.

7 is a view for explaining another embodiment of the present invention.

As illustrated in FIG. 7, signal wires drawn from the timing controller 210 are divided into odd or even positions, respectively, and are disposed at both sides with respect to the center of the LCD panel 200.

The signal lines divided into even and odd numbers on both sides of the LCD panel 200 are composed of signal lines divided into even and odd numbers.

That is, the LCD panel 200 is divided into four areas to sample the data signal. When sampling the data signal to each of the four divided areas, the LCD panel 200 includes the positive and the even signal lines from the odd or even signal lines. The negative data signals were selectively sampled.

Therefore, by dividing into areas corresponding to the four divisions of the LCD panel 200, the load cap is reduced between the signal wires, and the positive and negative data signals are selectively sampled to prevent signal distortion caused by EMI. There is an advantage to that.

In FIG. 7, as shown in FIG. 4, the same division into four division areas is performed based on the LCD panel 200. However, each signal wire is divided into odd and even wires, thereby providing a data signal. There is a difference in sampling.

Therefore, a data signal is transmitted to the signal wires divided into four, and sampling is performed only for the divided areas, so that a load cap is reduced between the signal wires, and when sampling the data signal, EMI can be prevented by selectively processing signals of different polarity in odd and even lines.

When a data signal is transmitted from the timing controller 210 along the signal wires, a reduction in the load cap occurring between the signal wires is the size of the buffer buffering the data signal to apply to the source drive ICs 401. There is an advantage to reduce.

In addition, the reduction of the load cap between the signal wires may reduce the frequency of the data signal applied to the source drive ICs, thereby enabling fast data signal transmission without signal delay.

In addition, the reduction of the load cap applied to each of the signal wires may reduce signal attenuation, thereby reducing power consumption of the system as a whole.

7 shows that the number of source drive ICs 401 disposed in the LCD panel doubles, unlike in FIG. 4, because it selectively samples the positive data signal and the negative data signal, respectively.

However, although the number of source drive ICs 401 connected to each of the four divided signal wires drawn out from the timing controller 210 appears to have increased, the signal throughput can be selectively adjusted since each sample is selectively sampled. Decrease compared to

In the signal processing procedure of the source driving system having such a structure, the positive and negative data signals are transmitted from the timing controller to the odd and even signal lines, respectively.

The source drive IC sampling the data signal is driven by two drive ICs to correspond to odd and even numbers. At this time, the selection of odd and even numbers is selected in a direction in which the reduction rate is small according to the change amount of the adjacent data signal.

Therefore, since the amount of change in the data signal is small, it is possible to prevent the signal distortion characteristic due to EMI.

When data signals are transmitted from the odd or even signal wires, respectively, the signal processing scheme passes through the first latch portion 401a and the second latch portion 401b, as described in FIG. 4, and then the level shifter 401c. Will output

The data signal leveled up by the level shifter 401d is applied to the LCD panel 200 through the digital / analog converter 401d and the buffer unit 401e.

Accordingly, there is an advantage in that signal delay, load reduction, and image quality improvement can be prevented while preventing EMI from data signals.

As described in detail above, the present invention doubles the number of signal wires for transmitting the data signal from the timing controller to the source drive IC, and divides the data signal by dividing the data signal into two divided regions based on the LCD panel. By sampling, there is an effect of improving image quality due to signal delay prevention and load reduction.

In addition, by applying a positive data signal or a negative data signal to the odd-numbered and even-numbered signal wires from the timing controller, signal failure due to EMI can be prevented.

The present invention is not limited to the above-described embodiments, and various changes can be made by those skilled in the art without departing from the gist of the present invention as claimed in the following claims.

Claims (18)

A timing controller for generating a data signal; Signal wires for selectively dividing and transmitting a positive or negative data signal generated from the timing controller, respectively; A plurality of source drive ICs for processing data signals transmitted from the signal wires; And a liquid crystal panel for sequentially sampling the data signals processed by the source drive ICs to display an image. The method of claim 1, And the signal wires are divided into four independent signal wires so as to correspond to four divisions of the liquid crystal panel. The method according to claim 1 or 2, And the source drive ICs are electrically connected to correspond to the divided regions of the signal lines. The method of claim 1, And the signal lines are divided into odd and even numbers to transmit positive and negative data signals generated from the timing controller. The method of claim 4, wherein The signal lines are characterized in that the positive and negative data signals are transmitted along odd or even lines to prevent electromagnetic interference (EMI). The method of claim 1, And a load load between the signal wires can be reduced by transmitting data signals to the divided signal wires, respectively. A timing controller for generating data signals in red, green, and blue; Signal wires for dividing and transmitting different data signals generated from the timing controller into odd or even wires, respectively; A plurality of source drive ICs for sampling the data signal transmitted from the signal lines into a pixel signal; And a liquid crystal panel for displaying an image by pixel signals sampled from the source drive ICs. The method of claim 7, wherein And the signal lines are divided into four independent lines so as to correspond to a four-divided area of the liquid crystal panel. The method of claim 7, wherein And a data signal generated by the timing controller is a positive and a negative data signal. The method of claim 7, wherein And the source drive ICs are connected to odd or even signal lines of the signal lines, respectively. The method according to claim 7 or 9, And the source drive ICs selectively process positive or negative data signals transmitted from the odd or even signal lines. The method of claim 8, And the signal lines are divided into odd or even lines in a region divided into four independent lines. Generating a data signal from a timing controller of the liquid crystal display device; Selectively transmitting a positive or negative data signal generated from the timing controller to signal wires divided into a plurality of areas; Receiving a data signal from the divided signal wires and performing signal processing on source drive ICs; Displaying an image by outputting data signals processed by the source drive ICs to a liquid crystal panel; Liquid crystal display device driving method comprising a. delete The method of claim 13, And the source drive ICs selectively process positive and negative data signals, respectively, to prevent signal distortion caused by electromagnetic interference (EMI). The method of claim 13, And a display area of the liquid crystal panel is divided so as to correspond to signals transmitted along the divided signal lines. The method of claim 13, And the liquid crystal panel displays an image by a positive or negative data signal. The method of claim 13, And delaying a data signal applied to the liquid crystal panel by dividing the signal lines.

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