KR100850211B1 - Liquid crystal display device having timing controller and source driver - Google Patents

Abstract

An LCD device having a timing controller and a source driver is provided to reuse IP(Intellectual Property) blocks in the LCD(Liquid Crystal Display) device by utilizing packet typed data. An LCD(Liquid Crystal Display) device includes a timing controller(310) and plural source drivers(361-366). The timing controller receives first data from outside and outputs clock signals and second data used for displaying the first data. The source drivers receive the second data, convert the second data into analog data, and output the converted data to a display panel. The clock signals and the second data are respectively transmitted through first and second signal lines which connect the timing controller with the source drivers using a point-to-point scheme.

Description

Liquid Crystal Display device having Timing Controller and Source Driver

BRIEF DESCRIPTION OF THE DRAWINGS In order to better understand the drawings cited in the detailed description of the invention, a brief description of each drawing is provided.

1 is a view showing a conventional LCD device.

FIG. 2 is a diagram illustrating signals or data input and output to the LCD device of FIG. 1.

3A is a diagram illustrating an LCD device according to an embodiment of the present invention.

3B is a diagram illustrating a modification of FIG. 3A.

FIG. 3C is a diagram illustrating the clock and delay lines of FIG. 3B in detail.

4A is a diagram illustrating signals or data input and output to and from the LCD device of FIG. 3A.

4B is a diagram illustrating one form of second data input and output to FIG. 3A.

FIG. 5 is a diagram illustrating another form of a signal or data input and output to and from the LCD device of FIG. 3A.

FIG. 6A illustrates a display panel connected to the source driver of FIG. 3A.

FIG. 6B is a diagram illustrating a liquid crystal in the panel of FIG. 6A.

FIG. 6C is a diagram illustrating a differential voltage supplied into the liquid crystal of FIG. 6B.

FIG. 7 is a diagram illustrating another modified example of FIG. 3A.

8 is a diagram illustrating another modified example of FIG. 3A.

** Description of the symbols for the main parts of the drawings **

300: liquid crystal display device

310: timing controller (TCON)

311: Controller & Buffer Memory Unit

315: clock signal generator

317: Clock

319: Phase Locked Loop (PLL)

310: packet data generator

323: power

330: data transmitter

340: switching unit

350: first signal line

355: second signal line

361 to 366: source driver (SD)

373: Delay Line

600: display panel

610: liquid crystal cell

The present invention relates to an LCD device including a source driver and a timing controller, and more particularly to an LCD device capable of reusing IP blocks in an LCD device.

1 is a view showing a conventional LCD device.

Referring to FIG. 1, a conventional LCD device 100 includes a timing controller 110, a plurality of source drivers 125, and a display panel 140.

The timing controller 110 receives image data from the host system 105. Here, the received image data is referred to as first data D1. The timing controller 110 temporarily stores the first data D1 in the controller & buffer 112, determines the time point and the position at which the first data D1 is output, and determines the second data D2_i. ) In addition, the clock output unit 114 outputs the required clock signal CLK through which the second data D2_i is transmitted.

The source drivers 125 receive the second data, convert the second data into analog signals, and output the second data to the display panel 140.

The display panel 140 displays an image screen according to the source driver output signals.

In the conventional LCD device 100, the clock output unit 114 and the plurality of source drivers 125 included in the timing controller 110 are connected in a multi-drop manner. When the signal is transmitted in the multi-drop method, the signal input to the source driver SDn located far from the clock output unit 114 becomes a signal in which distortion occurs in the clock signal CLK.

In addition, when the clock signal CLK is transmitted in a multi-drop method, and the second data signal D2_i is simultaneously transmitted in synchronization with the clock signal CLK, electromagnetic interference (EMI) from the second data signals is transmitted. This will occur.

FIG. 2 is a diagram illustrating signals or data input and output to the LCD device of FIG. 1.

Referring to FIG. 2, when a horizontal synchronization signal (HSYNC) 201 is applied to logic high, synchronization of liquid crystal cells provided in the horizontal direction of the display panel is started.

Within the logic high section of the horizontal synchronization signal HSYNC, a logic high section of the data enable signal DE occurs. The data enable signal DE is a signal that enables data transmission to be activated, and data transmission is activated during a logic high period. That is, during the logic high period of the data enable signal DE, data transmission is performed.

Referring to the signal 210, the first data D1 is transmitted during the logic high period of the data enable signal DE. Here, the amount of data capable of displaying one horizontal line of the display panel is transmitted during one logical high period. No data is transmitted from the host system 105 to the timing controller 110 during the period c to d, which is the logical low period of the data enable signal DE.

The clock signal CLK 215 has a constant frequency and is continuously output. The first data D1 transmitted to the timing controller 110 is transmitted in synchronization with a rising edge or a falling edge of the clock signal CLK.

Referring to the illustrated 220, 225, and 230 signal lines, the second data D2_i transmitted from the timing controller 110 to the source drivers 125 are commonly transmitted through signal lines connected by multi-drops. do. Therefore, since the second data D2_i is transmitted in synchronization with one clock signal CLK, the second data is transmitted at the same timing.

As described above, since the second data D2_i are transmitted to the respective source drivers 125 at the same time, the differential current required for data transmission is also applied at the same time. Therefore, since a single current is suddenly required, there is a problem that the stability of the system is lowered. In addition, since data is simultaneously applied to the above-described adjacent source drivers, an electromagnetic interference (EMI) phenomenon occurs largely.

In addition, the timing controller 110 of the conventional LCD device receives the first data D1 and outputs the second data D2, so that each data load time or charge sharing time ( The operating conditions such as charge share time must be set separately. That is, a separate circuit for performing the data load time, the charge share time, and the like must be provided internally.

In addition, the conventional LCD device has a disadvantage in that the existing IP block (Intellectual Property Block) cannot be reused when the resolution, color depth, channel number of the source driver, etc. of the LCD device are changed. Here, the IP block means a functional block (semiconductor design module) designed to be reused with independent functions when designing an integrated circuit (IC). In other words, it refers to a block in which functions necessary for configuring a logic circuit of a semiconductor are arranged in a hardware or software state. Examples of the IP block include the source drivers 125 and respective components (eg, the controller and the buffer unit 115) in the timing controller 110. Such a conventional LCD device is shown in detail in US Patent No. 6,954,201.

As described above, the conventional LCD device 100 transmits a clock signal through a signal line connected in a multi-drop method, so that an electromagnetic interference (EMI) phenomenon occurs largely, and to all source drivers at a certain point in time. Since data is transmitted, there is a problem of instability of the system. In addition, there is a problem in that the existing IP blocks cannot be reused and changed whenever the LCD device and the source driver are changed.

An object of the present invention is to provide an LCD device capable of reducing the occurrence of electromagnetic interference by transmitting a clock signal through a signal line connected in a point-to-point manner.

Another object of the present invention is to provide an LCD device capable of reusing an IP block even when an operating condition is changed by making data transmitted to a source driver in the form of packet data.

An LCD device according to an embodiment of the present invention for achieving the above technical problem is provided with a timing controller and a plurality of source drivers.

The timing controller receives first data applied from the outside and outputs clock signals and second data to display the first data.

The source driver receives the second data, converts the second data into analog data, and outputs the analog data to the display panel.

The clock signals are transmitted through a first signal line connecting the timing controller and the source drivers in a point-to-point manner, and the second data is transmitted through a second signal line connecting the timing controller and the source drivers in a point-to-point manner.

The second data is packet data.

Preferably, the timing controller includes a packet data generation unit for converting and outputting the first data into a packet data form.

Preferably, the packet data includes information at the time point at which the second data is loaded from the source driver to the display panel.

Preferably, the timing controller includes a phase locked loop that receives an internally generated clock signal, and delays it to output n clock signals having different phases.

An LCD device according to another embodiment of the present invention includes a timing controller and a plurality of source drivers.

The timing controller receives first data applied from the outside and outputs clock signals and second data to display the first data.

The source drivers receive an output signal of the timing controller, convert the analog signal into analog data, and output the analog signal to the display panel.

The clock signals and the second data are transmitted through the first signal line unit connecting the timing controller and the source driver in a point-to-point manner.

The second data is transmitted in the form of packet data.

The clock signal may be embedded in the second data and output.

DETAILED DESCRIPTION In order to fully understand the present invention, the operational advantages of the present invention, and the objects achieved by the practice of the present invention, reference should be made to the accompanying drawings which illustrate preferred embodiments of the present invention and the contents described in the drawings.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings. Like reference numerals in the drawings denote like elements.

3A is a diagram illustrating an LCD device according to an embodiment of the present invention.

In FIG. 3A, a case in which six source drivers are provided is illustrated as an example, and it will be apparent that a plurality of other source drivers may be provided.

Referring to FIG. 3A, a liquid crystal display (LCD) device 300 according to an embodiment of the present invention may include a timing controller (TCON) 310 and a plurality of source drivers (SDs) 361. To 366).

The timing controller 310 receives the first data D1 from an external host system 315, adjusts a position and a time point at which the first data D1 is to be displayed, and adjusts the second data D2. Output to source drivers 361 to 366. Here, the external host system 315 may be a personal computer (PC), a graphics card, a graphic processing apparatus of a TV, or the like.

The timing controller 310 may internally include a clock (CLOCK) 317, a phase locked loop (PLL) 319, a controller and a buffer memory unit 311, and a packet data generator ( A packet data generator 320 and a data transmitter 330.

The clock 317 generates a clock signal CLK having a predetermined frequency. Here, the generation time of the predetermined frequency and the clock signal is determined according to the control of the controller and the buffer memory unit 311.

The phase locked loop 319 receives a clock signal generated from the clock 317 and outputs a plurality of clock signals 350 having a phase difference to the plurality of source drivers, respectively. Accordingly, the plurality of clock signals output from the phase locked loop 319 have different phases. Here, the phase locked loop 319 may be provided inside the clock 317 or may be provided outside. 3A illustrates a case where the phase locked loop 319 is provided outside the clock 317 as an example.

The control unit and the buffer memory unit 311 receive the first data D1 and various control signals from the host system 315. Then, the first data D1 is temporarily stored, and a time point, a position (address), etc. of the first data D1 are determined according to the control signal. Here, the various control signals are the horizontal synchronizing signal HSYNC, the vertical synchronizing signal VSYNC, and the like.

The packet data generator 320 uses headers and payloads using first data D1, which is image data for display on a pixel, and various control signals output from the controller and the buffer memory unit 311. Generates packet data including a portion.

Here, the header determines the meaning of data in the payload unit. For example, depending on the value of the header, payload data is determined by the time at which the source driver SD is loaded into the display panel, the address where the payload data is located, and the voltage polarity across the pixels. It may be a part having information on charge sharing time, etc., which is a time required for changing, or may be a part having image information actually displayed.

The data sending unit 330 outputs data output from the packet data generating unit 320 to each source driver.

The timing controller 310 of the LCD device 300 according to the present invention may further include a switching unit 340. The switching unit 340 cuts off power supply in a section in which data is not sent from the data sending unit. Here, the on or off of the switching unit 340 tracks the signal level output from the data sending unit, and detects an inactive section in which transmission is not performed. In the transmission deactivation period, the switch is turned off to cut off the power supply. Here, the power source may be a source of differential current.

In FIG. 3A, the switching unit 340 is illustrated by using a simple switch as an example, but it will be apparent that other conventional power control devices may be used. That is, the switching unit 340 becomes a power supply control device that tracks the signal level output from the data sending unit and controls the power supply in response thereto.

The plurality of source drivers 361 to 366 respectively receive the second data D2 output from the timing controller 310 and apply them to both ends of the liquid crystal of the display panel according to the second data D2. Output the voltage value. The source driver (SD) is a type of digital to analog converter (DAC). Therefore, the second data D2, which is a digital signal, is converted into an analog voltage and output. According to the analog voltage value output from the source driver, the gray voltage driving the liquid crystal is changed, so that the brightness of the light output from the liquid crystal is changed.

Here, in outputting the clock signal CLK, the timing controller 310 and the plurality of source drivers are connected in a point to point manner. The clock signals are individually transmitted through the first signal line 350 connected in a point-to-point manner. Here, the clock signals transmitted separately may be clock signals having different phases output from the phase locked loop 319. In addition, the phase lock loop 319 may be clock signals having different phases without causing a phase delay.

In addition, in outputting the second data D2, the timing controller 310 and the plurality of source drivers are connected in a point-to-point manner. Through the second signal line 355 connected in a point-to-point manner, the second data D2 of the packet data type is individually transmitted to the respective source drivers.

Here, the data transmitted to the 366 source driver SD # 6 is shown as 'DATA +/-' because the transmitted data is in the form of differential signals of inverted and non-inverted. The clock signal is also shown as 'CLK +/-' and is transmitted in the form of a differential signal of inverted and non-inverted.

3B is a diagram illustrating a modification of FIG. 3A.

Referring to FIG. 3B, FIG. 3B includes a delay line 373 instead of the phase locked loop 319 of FIG. 3A. Since the rest of the configuration is the same as in FIG. 3A, detailed descriptions thereof will be omitted.

The delay line 373 receives a clock signal CLK output from the clock 370 and delays it using delay cells. Accordingly, a plurality of clock signals CLK having different phases are output from the delay line 373.

The delay line 373 may be provided inside the clock 371 or may be provided outside the clock 371. 3B illustrates a case where the delay line 373 is provided outside the clock 371 as an example.

Delay cells provided in the delay line are described in detail with reference to FIG. 3C below.

FIG. 3C is a diagram illustrating the clock and delay lines of FIG. 3B in detail.

Referring to FIG. 3C, the delay line 373 of FIG. 3B includes a plurality of delay cells 380. Delay cell 380 may be implemented using an inverter 381. When the delay cell is implemented using an inverter, the delay amount may be determined by adjusting the value of the resistance R and the capacitance C. Here, the original clock signal CLK is set to CLK0, and the signal delayed in phase by passing through the first inverter 381 is passed through the first clock signal CLK1 and the two inverters 381 and 382 to receive the phase delayed signal. This is called the second clock signal CLK2.

Therefore, when passing through the delay line 373, clock signals having different phases or more than the number of source drivers provided are output. Each second data synchronized with the respective clock signals is output to the source drivers.

4A is a diagram illustrating signals or data input and output to and from the LCD device of FIG. 3A.

Referring to FIG. 4A, during the logic high period of the data enable signal DE, the first data D1 output from the host system 315 is transmitted to the timing controller 310.

The second data transmitted from the timing controller 310 to the first source driver SD1 361 is output at a3 time point. The second data transmitted to the second source driver (SD2) 362 is output at the time b1. The second data transmitted to the third source driver SD3 363 is output at the time c1. As described above, while passing through the phase-locked loop 319 or the delay line 373, respectively, is synchronized to the clock signal having a different phase, the output time point is different.

In addition, a data load time is individually set in the packet data.

Preferably, the loading time in each of the source drivers is set differently. That is, the second data transmitted to the first source driver 361 is loaded at a4 time point, and the second data transmitted to the second source driver 362 is loaded at b2 time point. In this way, by varying the load time points, the simultaneous switching noise is reduced, and the data load time between the source drivers caused by the delay of the panel gate line is reduced. It can make up for the difference.

Here, the form of the second data transmitted to the source drivers will be described later with reference to FIG. 4B.

4B is a diagram illustrating one form of second data input and output to FIG. 3A.

Referring to FIG. 4B, the second data D2 has a form of packet data. The packet data 430 includes a header 431 and a payload unit 435.

Here, the header 431 is a part having information regarding what data the data of the payload unit 435 is. The payload unit 435 becomes a part having substantial information about image data, loading time, charge sharing time, or the like. The packet data generator 320 generates the second data D2.

The payload data may be data load time information that is a time point at which the second data D2 is loaded from the source driver to the panel display according to the value of the header 431. In addition, the charge sharing time (charge sharing time), the exact address where the data is located, or the size information of the data may be further included.

For example, the payload data 435 followed by the header 431 indicates the loading time, and the payload data 435 includes a data load time. Then, the payload data 435 included in the packet data 430 received from the source driver is recognized as the loading time, and the data is loaded at the loading time. The source driver SD loads the second data into the display panel at a corresponding time by decoding load time information present in the second data.

The payload data 435 followed by the header 431 indicates that the image data is to be image data, and the payload data 435 includes the image day. Then, the source driver recognizes the received packet data 430 as image data.

Therefore, the LCD device according to the embodiment of the present invention has a disadvantage in that the existing IP blocks cannot be reused when the resolution, color depth, etc. of the LCD device, or the number of channels of the source driver change in the conventional LCD device. It can be overcome. In addition, even if the charge sharing time required for display, the exact address where the data is located, or the size information of the data are changed, the packet data may be generated according to the changed information. That is, by generating the second data in the form of packet data, existing IP blocks can be reused.

FIG. 5 is a diagram illustrating another form of a signal or data input and output to and from the LCD device of FIG. 3A.

Referring to FIG. 5, a case in which two packet data are transmitted in one data transmission section is illustrated.

Data to be output on one horizontal line of the display panel is transmitted in one data transmission section. Here, data of one line may be divided into two packet data or more packet data and transmitted.

Preferably, the loading time of the first transmitted packet data is set to be different. Then, the loading time of the second transmitted packet data is set to be different. That is, 510 packet data is loaded at time a5 and 520 packet data is loaded at time b5. In addition, the loading timing of the 515 packet data and the 525 packet data may also be set differently.

This method can reduce the malfunction of the source driver due to power noise caused by the consumption of a large amount of current when analog data is loaded on the LCD panel, where the malfunction of the source driver is unstable. It is a problem that data cannot be normally input at a high speed transmitted from the timing controller TCON.

FIG. 6A illustrates a display panel connected to the source driver of FIG. 3A.

6A shows that the display panel 600 includes a myriad of liquid crystal cells 610. If the polarities of the voltages applied to the liquid crystal cells are all the same, an instantaneous color change occurs, thus altering the polarities of the liquid crystal cells at the intersection. As shown, adjacent liquid crystal cells have different polarities.

In addition, the voltage polarity of each liquid crystal cell continues to change.

FIG. 6B is a diagram illustrating a liquid crystal in the panel of FIG. 6A.

Referring to FIG. 6B, the brightness of the liquid crystal cell 610 is determined according to the magnitude of the voltage applied across the liquid crystal cell 610. The voltage polarity of the liquid crystal cells continues to change. As shown in Fig. 6B, a 1v voltage difference is generated by applying positive and negative voltages to the A and B terminals, respectively, and then to the A and B terminals, respectively, (-) and (+). Apply a voltage to cause a 1v voltage difference.

FIG. 6C is a diagram illustrating a differential voltage supplied into the liquid crystal of FIG. 6B.

Referring to FIG. 6C, the voltage of the terminal A is changed as shown in the 630 graph, and the voltage of the terminal B is changed into the 650 graph.

In changing the voltage, the reference voltage is 0V and the sum of the two voltages is 0V. Here, the time from the highest or minimum voltage point to the voltage value of 0 V at both the A and B terminals is referred to as a charge sharing time. It is the time from t1 to t3 shown.

In the present invention, the charge sharing time can be changed by including the charge sharing time and the start time in the packet data.

FIG. 7 is a diagram illustrating another modified example of FIG. 3A.

Referring to FIG. 7, one clock signal line is connected to every two source driver bundles. Since the remaining components are the same as in FIG. 3A, detailed descriptions will be omitted. In addition, it will be apparent that one clock signal line may be connected to every two or more source driver bundles.

8 is a diagram illustrating another modified example of FIG. 3A.

Referring to FIG. 8, each clock signal may be embedded in each corresponding data signal and transmitted. That is, as shown in FIG. 3A, the clock signal is merged and transmitted to the corresponding second data D2 by using an embedding technique without having to provide a separate first signal line unit for the clock signals. The above-described embedding technique will be apparent to those of ordinary skill in the art.

As described above, optimal embodiments have been disclosed in the drawings and the specification. Although specific terms have been used herein, they are used only for the purpose of describing the present invention and are not intended to limit the scope of the present invention as defined in the claims or the claims. Therefore, those skilled in the art will understand that various modifications and equivalent other embodiments are possible therefrom. Therefore, the true technical protection scope of the present invention will be defined by the technical spirit of the appended claims.

As described above, the LCD device according to the present invention connects the clock signal line between the timing controller and the source driver in a point-to-point manner, and in the form of a timing controller timing controller timing controller, enabling more data transmission and electromagnetic interference characteristics. There is an advantage to improve. By using the data in the form of packets, there is an advantage that can be reused without having to individually design the IP blocks in the LCD device. And, through the switching unit, by cutting off the supply of the differential current in the period when the data is not transmitted to the source drivers, there is an effect that can reduce the power consumption.

Claims (20)

A timing controller which receives first data applied from the outside and outputs clock signals and second data to display the first data; And Receiving n second data and converting the second data into analog data and outputting the second data to a display panel; The clock signals are transmitted through a first signal line unit connecting the timing controller and the source drivers in a point-to-point manner, and the second data line is a second signal line connecting the timing controller and the source drivers in a point-to-point manner. Transmitted through wealth, And the second data is packet data. The method of claim 1, The timing controller is A packet data generator which receives the first data and converts the first data into the packet data and outputs the second data; The packet data is A header having information about what information the data of the payload portion has; And And a payload portion including data loading time, charge sharing time, image data to be displayed, and the like. The method of claim 2, wherein the timing controller And n clock signals having different phases from the n source drivers, respectively. The method of claim 1, wherein the packet data is And an image of a time point at which image data is loaded into the display panel from the source driver. The method of claim 3, wherein the timing controller And a phase locked loop which receives an internally generated clock signal and outputs the n clock signals having different phases. The method of claim 3, wherein the timing controller Having a delay line comprising a plurality of delay cells, And the n clock signals having different phases are output by using the delay line. The method of claim 5, wherein the timing controller A controller and a buffer memory unit configured to receive and store the first data and output a control signal for display; A packet data generation unit generating second data which is packet data using the first data; And And a data output unit configured to output the second data to the source driver. The method of claim 6, wherein the timing controller A controller and a buffer memory unit configured to receive and store the first data and output a control signal for display; A packet data generation unit generating second data which is packet data using the first data; And And a data output unit configured to output the second data to the source driver. The method of claim 4, wherein The second data is A header indicating that data in the payload portion is loading time; And It includes a payload unit including information such as the loading time, the time or location of loading,  The LCD device, And a user adjusts a loading time of the second data by adjusting a value of the payload unit of the packet data. The method of claim 9, wherein the packet data is And the loading time points of the second data are different from each other. The method of claim 4, wherein the packet data is And an information of a charge sharing time, which is a time required to change the voltage polarity across the pixel, or an image information to be actually displayed. The method of claim 11, wherein the source driver is And a decoder which receives the packet data and decodes the packet data to obtain information on a loading time or charge sharing time. The method of claim 1, wherein the size of the packet data is And differently set according to the number of image signals included in the one packet data. The method of claim 1, The first signal line portion includes a plurality of first signal lines, The second signal line part includes a plurality of second signal lines. And the first signal lines and the second signal lines are different signals. The method of claim 1, wherein the LCD device And an image data to be displayed on one horizontal line of the display panel during one activation period of the data enable signal. The method of claim 15, wherein the LCD device In transmitting the second data, Transmit image data to be displayed on one horizontal line of the display panel to the source driver as one packet data, or Display panel LCD device, characterized in that for transmitting the image data to be displayed on one horizontal line divided into two or more packet data. The method of claim 1, wherein the timing controller And a switching unit which supplies or cuts off the differential current required for the second data transmission. The method of claim 17, wherein the timing controller is And detecting a time period during which the second data is not transmitted, and controlling the switching unit to be turned off in a time period during which the second data is not transmitted. A timing controller which receives first data applied from the outside and outputs clock signals and second data to display the first data; And A plurality of source drivers configured to receive an output signal of the timing controller, convert it into analog data, and output the analog signal to a display panel; The clock signals and the second data are transmitted through a first signal line unit connecting the timing controller and the source drivers in a point-to-point manner. The second data becomes packet data, And the clock signal is embedded in the second data and output. The method of claim 19, The second data is A header having information about what information the data in the payload section has; And It includes a payload unit including information such as the loading time, the time or location of loading,  The LCD device And a user adjusts a loading time of the second data by adjusting a value of the payload unit of the packet data.

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