KR101001989B1 - Apparatus and method driving liquid crystal display device - Google Patents

Abstract

The present invention relates to a driving device and a method of a liquid crystal display device to prevent flicker according to the driving frequency.

A driving device of a liquid crystal display device according to an embodiment of the present invention includes a liquid crystal panel in which a liquid crystal cell is formed at each intersection of gate lines and data lines; A system for generating data and control signals having a first drive frequency; A data driver for driving data lines of the liquid crystal panel; A gate driver for driving gate lines of the liquid crystal panel; A timing controller for comparing the first driving frequency with a preset second driving frequency and converting the first driving frequency into the second driving frequency and supplying the second driving frequency to the liquid crystal panel according to a comparison result; The timing controller may include a signal generator generating a dot clock using the control signals based on the vertical synchronization signal of the first driving frequency, and a vertical synchronization signal of the first driving frequency output from the signal generator. A comparator for comparing with the vertical synchronization signal of the second drive frequency, and a signal selector for selectively outputting control signals of the first drive frequency and control signals of the second drive frequency according to a comparison result of the comparator; And a frequency converter for converting the control signals of the first drive frequency output from the signal selector into control signals of the second drive frequency, and the converted second drive frequency supplied from the frequency converter. Any one of control signals of and the control signals of the second driving frequency output from the signal selector And a control signal generator for generating a gate control signal and a data control signal for driving the gate driver and the data driver, respectively.

The present invention converts data and control signals supplied from the system by a driving frequency of less than 60 Hz to 60 Hz or more to drive a liquid crystal display device, thereby preventing flicker occurring in data displayed on the liquid crystal panel. Can be.

Description

Driving apparatus and method of liquid crystal display device {APPARATUS AND METHOD DRIVING LIQUID CRYSTAL DISPLAY DEVICE}             

1 is a block diagram schematically illustrating a driving device of a general liquid crystal display device.

2 is a block diagram schematically illustrating a driving device of a liquid crystal display according to an exemplary embodiment of the present invention.

3 is a block diagram illustrating a timing controller illustrated in FIG. 2.

<Description of Symbols for Main Parts of Drawings>

10, 110: system 12, 112: timing controller

18, 118: data driver 20, 120: gate driver

22, 122: liquid crystal panel 132: data generator

136: signal generator 138: comparison unit

140: signal selector 142: frequency converter

144: control signal generator 150: data selector

152: write frame memory 154: read frame memory

156: clock selection unit 160: data alignment unit

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a driving device and a method of a liquid crystal display device, and more particularly to a driving device and a method of a liquid crystal display device to prevent flicker according to a driving frequency.

A conventional liquid crystal display device displays an image by adjusting the light transmittance of a liquid crystal using an electric field.

To this end, the liquid crystal display includes a liquid crystal panel in which liquid crystal cells are arranged in a matrix and a driving circuit for driving the liquid crystal panel.

In the liquid crystal panel, the gate lines and the data lines are arranged to cross each other, and the liquid crystal cells are positioned in an area where the gate lines and the data lines cross each other. The liquid crystal panel is provided with pixel electrodes and a common electrode for applying an electric field to each of the liquid crystal cells. Each of the pixel electrodes is connected to any one of the data lines via source and drain terminals of a thin film transistor (hereinafter, referred to as a TFT) as a switching element. The gate terminal of the thin film transistor is connected to one of the gate lines for causing the data voltage signal to be applied to the pixel electrodes for one line. Accordingly, the liquid crystal display displays an image by adjusting light transmittance by an electric field applied between the pixel electrode and the common electrode according to the data voltage signal supplied for each liquid crystal cell.

Referring to FIG. 1, a driving apparatus of a general liquid crystal display device includes a system 10 such as a personal computer (not shown) and a liquid crystal panel in which liquid crystal cells are arranged in a matrix form at each intersection of data lines and gate lines. 22, the data driver 18 for driving the data lines, the gate driver 20 for driving the gate lines, and the gate driver 20 and the data driver according to a control signal input from the system 10. The timing controller 12 which controls the drive timing of 18) and supplies the data R, G, B input from the system 10 to the data driver 18 is provided.

The liquid crystal panel 22 includes TFTs and liquid crystal cells formed at regions defined by intersections of gate lines and data lines.

The TFT is turned on when the scan signal from the gate line, that is, the gate high voltage is supplied, and supplies the pixel signal from the data line to the liquid crystal cell. The TFT is turned off when the gate low voltage is supplied from the gate line to maintain the pixel signal charged in the liquid crystal cell.

A liquid crystal cell is equivalently represented by a capacitor, and is composed of a common electrode facing each other with a liquid crystal interposed therebetween and a pixel electrode connected to a TFT. The liquid crystal cell further includes a storage capacitor so that the charged pixel signal is stably maintained until the next pixel signal is charged. The liquid crystal cell realizes gray by adjusting the light transmittance by varying the arrangement state of the liquid crystal according to the pixel signal charged through the TFT.

The system 10 uses data chips (or video controllers, CPUs, etc.), not shown, for data R, G, B, and control signals (input clock clk, horizontal synchronization signal H, vertical synchronization signal). V)) are generated and supplied to the timing controller 12. At this time, a low voltage differential signal (LVDS) interface, a TTL interface, and the like are used to transmit data and control signals between the system 10 and the timing controller 12.

The timing controller 12 controls to drive the data driver 18 composed of a plurality of drive ICs and the gate driver 20 composed of a plurality of gate drive ICs using a control signal input from the system 10. Generate a signal. In addition, the timing controller 12 aligns the data Data input from the system 10 so as to correspond to the driving frequency of the vertical synchronization signal H from the system 10, and arranges the aligned data RGB as a data driver. Is sent to 18.

Specifically, the timing controller 12 drives a plurality of gate driver ICs by using control signals (input clock clk, horizontal synchronization signal H, and vertical synchronization signal V) input from the system 10. The gate control signals GCS are generated, and the data control signals DCS for driving the data driver ICs are generated. Accordingly, the gate control signals and the data control signals become equal to the driving frequency supplied from the system 10 to the timing controller 12.

The data driver 18 selects reference voltages according to the input data, converts the reference voltages into analog pixel signals, and supplies them to the liquid crystal panel 22 in response to the data control signals DCS input from the timing controller 12.

The gate driver 20 controls the gate terminals of the TFTs arranged on the liquid crystal panel 22 on / off line by line in response to gate control signals GCS input from the timing controller 12. The analog pixel signals supplied from the data driver 18 are applied to the respective liquid crystal cells connected to the respective TFTs.

Such liquid crystal display devices are often used not only for monitors but also for televisions. As a result, the liquid crystal display is driven by a low driving frequency in order to reduce power consumption. In particular, a liquid crystal display for displaying television signals of the PAL (color television system developed in West Germany) signal system among the television signal systems is driven at a driving frequency of 40 Hz. Accordingly, when the liquid crystal display is driven at a low driving frequency of 40 Hz, flicker occurs in the image displayed on the liquid crystal panel 22.

Accordingly, an object of the present invention is to provide a driving device and method for a liquid crystal display device capable of preventing flicker according to the driving frequency.

In order to achieve the above object, a driving apparatus of a liquid crystal display according to an embodiment of the present invention includes a liquid crystal panel in which a liquid crystal cell is formed at each intersection of gate lines and data lines; A system for generating data and control signals having a first drive frequency; A data driver for driving data lines of the liquid crystal panel; A gate driver for driving gate lines of the liquid crystal panel; A timing controller for comparing the first driving frequency with a preset second driving frequency and converting the first driving frequency into the second driving frequency and supplying the second driving frequency to the liquid crystal panel according to a comparison result; The timing controller may include a signal generator generating a dot clock using the control signals based on the vertical synchronization signal of the first driving frequency, and a vertical synchronization signal of the first driving frequency output from the signal generator. A comparator for comparing with the vertical synchronization signal of the second drive frequency, and a signal selector for selectively outputting control signals of the first drive frequency and control signals of the second drive frequency according to a comparison result of the comparator; And a frequency converter for converting the control signals of the first drive frequency output from the signal selector into control signals of the second drive frequency, and the converted second drive frequency supplied from the frequency converter. Any one of control signals of and the control signals of the second driving frequency output from the signal selector And a control signal generator for generating a gate control signal and a data control signal for driving the gate driver and the data driver, respectively.

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In the driving apparatus, the control signal may be a vertical synchronization signal, a horizontal synchronization signal, and a clock signal.

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In the driving device, the timing controller selects a clock to output any one of a dot clock of a control signal output from the signal selector and a dot clock of the converted control signal output from the frequency converter according to a comparison result of the comparison unit. And data for converting the data supplied from the system to have the second driving frequency according to the comparison result of the comparator, and for supplying the converted data to the data driver according to the dot clock supplied from the clock selector. It is characterized by further comprising a generator.

In the driving device, the data generation unit selectively outputs data supplied from the system according to a comparison result of the comparison unit, and a write memory that stores the data output by the selection of the data selection unit in units of frames. And storing at least two frame data of the frame unit stored in the write memory or storing data supplied from the data selector and outputting the stored data to the data driver according to a dot clock from the clock selector. And a data alignment unit.

The data generator may further include a read memory that reads data in units of frames stored in the write memory and supplies the read data to the data alignment unit.

In the driving device, the first driving frequency is less than 60 Hz, and the second driving frequency is 60 Hz or more.

In the driving device, the second driving frequency is 75 Hz.

According to an aspect of the present invention, there is provided a method of driving a liquid crystal display device, the method including: providing a liquid crystal panel in which liquid crystal cells are formed at intersections of gate lines and data lines; Generating data and control signals having a first driving frequency; Comparing the first driving frequency with a second driving frequency and converting the first driving frequency into the second driving frequency and supplying the second driving frequency to the liquid crystal panel according to the comparison result; The converting into the second driving frequency may include generating a dot clock using the control signals based on the vertical synchronization signal of the first driving frequency through a signal generator, and by using the comparison unit, the signal generator. Comparing the vertical synchronous signal of the first driving frequency with the vertical synchronous signal of the second driving frequency and outputting the control signals of the first driving frequency and the first signal according to the comparison result through a signal selection unit; Selectively outputting control signals of a second driving frequency; converting the control signals output from the signal selection unit to the second driving frequency according to a comparison result of the comparison unit through a frequency converter; Control signals of the converted second driving frequency supplied from a converter and an image output from the signal selector Generating a gate control signal and a data control signal for driving each of the gate driver and the data driver by using any one of the control signals of the second driving frequency.

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Other objects and features of the present invention in addition to the above object will be apparent from the description of the embodiments with reference to the accompanying drawings.

Hereinafter, exemplary embodiments of the present invention will be described with reference to FIGS. 2 and 3.

2 and 3, a driving device of a liquid crystal display according to an exemplary embodiment of the present invention includes a system 110 such as a personal computer (not shown), a liquid crystal cell at each intersection of data lines and gate lines. The liquid crystal panel 122 arranged in the matrix form, the data driver 118 for driving the data lines, the gate driver 120 for driving the gate lines, and the driving of less than 60 Hz supplied from the system 110. A timing controller 112 for driving the liquid crystal panel 122 by converting the frequency to 60 Hz or more is provided.

The liquid crystal panel 122 includes TFTs and liquid crystal cells formed at regions defined by intersections of gate lines and data lines.

The TFT is turned on when the scan signal from the gate line, that is, the gate high voltage is supplied, and supplies the pixel signal from the data line to the liquid crystal cell. The TFT is turned off when the gate low voltage is supplied from the gate line to maintain the pixel signal charged in the liquid crystal cell.

A liquid crystal cell is equivalently represented by a capacitor, and is composed of a common electrode facing each other with a liquid crystal interposed therebetween and a pixel electrode connected to a TFT. The liquid crystal cell further includes a storage capacitor so that the charged pixel signal is stably maintained until the next pixel signal is charged. The liquid crystal cell realizes gray by adjusting the light transmittance by varying the arrangement state of the liquid crystal according to the pixel signal charged through the TFT.

The system 110 uses a data chip (or a video controller, a CPU, etc.) not shown in the drawing to show data R, G, and B and control signals (input clock clk, horizontal synchronization signal H, and vertical synchronization signal). V)) are generated and supplied to the timing controller 112. At this time, a low voltage differential signal (LVDS) interface and a TTL interface are used to transmit data and control signals between the system 110 and the timing controller 112.

The timing controller 112 uses a control signal (input clock clk, horizontal sync signal H, vertical sync signal V) input from the system 110 to configure a data driver 118 composed of a plurality of drive ICs. And control signals DCS and GCS for driving the gate driver 120 including the plurality of gate drive ICs. In addition, the timing controller 112 is generated from an image displayed on the liquid crystal panel 122 when data RGB driven by a driving frequency of less than 60 Hz displayed on the liquid crystal panel 122 is displayed on the liquid crystal panel 122. In order to prevent the flicker phenomenon, a driving frequency of less than 60 Hz supplied from the system 110 is converted to 60 Hz or more (hereinafter, assuming 75 Hz), and based on the converted driving frequency of 75 Hz, the system ( The data Data input from the 110 is sorted, and the sorted data RGB is transmitted to the data driver 118.

To this end, the timing controller 112 uses the input clock clk and the horizontal synchronization signal H based on the vertical synchronization signal V among the control signals supplied from the system 110 as shown in FIG. 3. A signal generator 136 for generating a dot clock Dclk, a comparator 138 for comparing whether or not the vertical synchronization signal V output from the signal generator 136 is 75 Hz, and a comparator 138 Is selected by the signal selector 140 and the signal selector 140 for selectively outputting the output signals V, H, and Dclk from the signal generator 136 output according to the comparison result A frequency converter 142 for converting the output signals V, H, and Dclk to be synchronized to 75 Hz, and an output signal V, H, Dclk and a frequency converter selected and output by the signal selector 140 The data control signal DCS and the gay signal using any one of the output signals V'H'Dclk 'converted by 142 are used. The control signal generator 144 generating the control signal GCS and the output signals V and H supplied from the signal selector 140 to the control signal generator 144 according to the output signal of the comparator 138. , The clock selector 156 which selects and outputs the dot clock Dclk among the converted output signals V ', H', and Dclk 'outputted from the dot clock Dclk or the frequency converter 142 among the Dclk. And the data Data supplied from the system 110 according to the output signal of the comparator 138, and the aligned data RGB according to the output signal from the clock selector 156. ) Is provided with a data generator 132.

The signal generator 136 generates and outputs a dot clock Dclk using the horizontal synchronous signal H and the input clock clk based on the vertical synchronous signal V supplied from the system 110.

The comparison unit 138 compares the driving frequency of the vertical synchronization signal V supplied from the system 110 with the reference frequency of 75 Hz, and compares the driving frequency of the vertical synchronization signal V supplied from the system 110. The logic signal according to the comparison result is supplied to each of the data generator 132, the signal selector 140, and the clock selector 156. For example, the comparison unit 138 generates a logic signal of a high state when the driving frequency of the vertical synchronization signal V supplied from the system 110 is 75 Hz or more, and a low state (LOW) when the driving frequency of the vertical synchronization signal V is less than 75 Hz. Generate a logic signal and supply it to each of the data generator 132, the signal selector 140, and the clock selector 156.

The signal selector 140 outputs the output signals V, H, and Dclk output from the signal generator 136 according to the logic signal output from the comparator 138. 144). That is, the signal selector 140 generates a control signal from the output signals V, H, and Dclk supplied from the signal generator 136 in response to the logic signal of the HIGH state supplied from the comparator 138. Supply to section 144. In this case, the output signals V, H, and Dclk supplied from the signal selector 140 to the control signal generator 144 are defined as first output signals V, H, and Dclk. On the other hand, the signal selector 140 performs frequency conversion on the output signals V, H, and Dclk supplied from the signal generator 136 in response to a logic signal of a low state LOW supplied from the comparator 138. Supply to the unit 142. At this time, the output signals V, H, and Dclk supplied from the signal selector 140 to the frequency converter 142 are defined as second output signals V, H, and Dclk.

The frequency converter 142 converts the frequencies of the second output signals V, H, and Dclk supplied from the signal selector 140. That is, the driving frequency of the vertical synchronization signal V supplied from the frequency converter 142 to the control signal generator 144 is converted to 75 Hz. Thereafter, the frequency converter 142 converts the horizontal synchronization signal H and the dot clock Dclk to 75 Hz based on the converted vertical synchronization signal V '. The frequency converter 142 converts the frequencies of the second output signals V, H, and Dclk supplied from the signal selector 140 to 75 Hz, and converts the converted second output signals V ', H', Dclk ') is supplied to the control signal generator 144.

The control signal generator 144 may include the first output signals V, H, and Dclk supplied from the signal selector 140 and the converted second output signals V ′ and H ′ supplied from the frequency converter 142. , Dclk ') generates and supplies a data control signal DCS for controlling the driving timing of the data driver 118 to the data driver 118 and controls the driving timing of the gate driver 120. The gate control signal GCS is formed to be supplied to the gate driver 120.

Accordingly, each of the data control signal DCS and the gate control signal GCS generated by the control signal generator 144 has a driving frequency for driving the liquid crystal panel 122 at 75 Hz.

The clock selector 156 may include a dot clock Dclk and a frequency converter of the first output signals V, H, and Dclk output from the signal selector 140 according to a logic signal supplied from the comparator 138. One of the dot clocks Dclk 'of the converted second output signals V', H ', and Dclk' output from 142 is selected and supplied to the data generator 132. That is, the signal selector 140 may dot the first output signals V, H, and Dclk output from the signal selector 140 in response to a logic signal of the high state HIGH supplied from the comparator 138. The converted second output signal outputted from the frequency converter 142 in response to a logic signal of a low state LOW supplied to the data generator 132 and supplied from the comparator 138. The dot clocks Dclk 'of V', H ', and Dclk' are supplied to the data generator 132.

The data generator 132 may further include a data selector 150 for selectively outputting data Data supplied from the system 110 according to a logic signal supplied from the comparator 138 and a data selector 142. The write frame memory 152 for storing the data Data selected and output in units of frames and the frame data stored in the write frame memory 152 are supplied with at least two frame data. And a read frame memory 154 for reading and supplying data of frame units stored in the write frame memory 152 to the data aligning unit 160.

The data selector 150 switches so that the data Data supplied from the system 110 is supplied to the data alignment unit 160 in response to the logic signal of the HIGH state supplied from the comparator 138. On the other hand, the data selector 150 switches so that data supplied from the system 110 is supplied to the write frame memory 152 in response to a logic signal of a low state LOW supplied from the comparator 138. do.

The write frame memory 152 stores the data Data supplied by the switching of the data selector 150 in units of frames.

The read frame memory 154 reads data stored in the write frame memory 152 and supplies the data to the data alignment unit 160.

The data aligning unit 160 sequentially stores at least two frame data Data of the frame unit data supplied from the write frame memory 152 by the read frame memory 154. Accordingly, the data Data supplied from the system 110 passes through the data selector 150 and the write and read frame memories 152 and 154 by the selection of the comparator 138. Or the data sorting unit 160 via the data selector 150. That is, when the driving frequency of the data Data supplied from the system 110 is less than 75 Hz, the data Data is arranged through the data selector 150 and the write and read frame memories 152 and 154. ) Is supplied to the data aligning unit 160 via the data selector 150.

The at least two or more frame data Data stored in the data aligning unit 160 of the data generating unit 132 is a driving frequency of at least one of the dot clocks Dclk and Dclk 'supplied from the clock selector 156. Is output to the data driver 118 accordingly.

When the driving frequency of the data Data supplied from the system 110 is 75 Hz or more, the data generator 132 rearranges the data and supplies the data to the data driver 118. On the other hand, the data generator 132 uses the first and second frame memories 144 and 146 and the data aligner 148 when the driving frequency of the data supplied from the system 110 is less than 75 Hz. The data is converted to have a driving frequency of 75 Hz and supplied to the data driver 118. Accordingly, the data generator 132 converts the driving frequency of the data RGB supplied to the data driver 118 to be 75 Hz.

The data driver 118 supplies data RGB having a driving frequency of 75 Hz supplied from the data generator 132 of the timing controller 112 in response to the data control signals DCS supplied from the timing controller 112. Accordingly, reference voltages are selected, converted into analog pixel signals, and supplied to the liquid crystal panel 122.

The gate driver 120 controls the gate terminals of the TFTs arranged on the liquid crystal panel 122 one line on / off in response to the gate control signals GCS supplied from the timing controller 112. The analog pixel signals supplied from the data driver 118 are applied to the respective liquid crystal cells connected to the TFTs.

The driving apparatus and method of the liquid crystal display according to the exemplary embodiment of the present invention detect whether or not the vertical synchronization signal V supplied from the system 110 to the timing controller 112 is 75 Hz or more, and then timing the system 110. When the vertical synchronization signal V supplied to the controller 112 is less than 75 Hz, the driving frequency of the data RGB supplied from the system 110 is converted to 75 Hz and supplied to the data driver 118, and the vertical synchronization is less than 75 Hz. The data driver 118 and the gate driver 120 are converted into a 75Hz signal by using the converted 75Hz vertical sync signal V ', the horizontal sync signal H', and the dot clock DclK '. To generate data and gate control signals DCS and GCS. Accordingly, the driving apparatus and method of the liquid crystal display according to the exemplary embodiment of the present invention drive the driving frequency of the data RGB displayed on the liquid crystal panel 122 at a driving frequency of 75 Hz on the liquid crystal panel 122. This prevents a flicker phenomenon occurring in the displayed data RGB. Therefore, the driving device and method of the liquid crystal display according to the embodiment of the present invention is a low frequency drive frequency of 40 Hz, such as a television signal of the PAL (color television system developed in West Germany) of the television signal system to a drive frequency of 60 Hz or more By converting and displaying on the liquid crystal panel 122, the flicker phenomenon can be prevented.

In addition, the liquid crystal display according to the exemplary embodiment of the present invention can reduce power consumption by receiving data and control signals V, H, and Dclk from the system 110 at low driving frequencies.

As described above, the driving device and method of the liquid crystal display according to the exemplary embodiment of the present invention convert the data and control signals supplied from the system to 60 Hz or more by a driving frequency of less than 60 Hz to drive the liquid crystal display. A flicker phenomenon generated in the data displayed on the image can be prevented.

Those skilled in the art will appreciate that various changes and modifications can be made without departing from the technical spirit of the present invention. Therefore, the technical scope of the present invention should not be limited to the contents described in the detailed description of the specification but should be defined by the claims.

Claims (26)

delete delete delete delete delete delete delete A liquid crystal panel in which a liquid crystal cell is formed at each intersection of the gate lines and the data lines; A system for generating data and control signals having a first drive frequency; A data driver for driving data lines of the liquid crystal panel; A gate driver for driving gate lines of the liquid crystal panel; A timing controller for comparing the first driving frequency with a preset second driving frequency and converting the first driving frequency into the second driving frequency and supplying the second driving frequency to the liquid crystal panel according to a comparison result; The timing controller, A signal generator which generates a dot clock using the control signals based on the vertical synchronization signal of the first driving frequency; A comparison unit for comparing the vertical synchronization signal of the first driving frequency output from the signal generator with the vertical synchronization signal of the second driving frequency; A signal selector for selectively outputting control signals of the first driving frequency and control signals of the second driving frequency according to a comparison result of the comparing unit; A frequency converter for converting the control signals of the first driving frequency from the signal selector into the control signals of the second driving frequency; Each of the gate driver and the data driver is driven using any one of the converted control signals of the second driving frequency supplied from the frequency converter and the control signals of the second driving frequency output from the signal selector. And a control signal generator for generating a gate control signal and a data control signal. The method of claim 8, And the control signal is a vertical synchronization signal, a horizontal synchronization signal, and a clock signal. delete The method of claim 8, The timing controller, A clock selector configured to output one of a dot clock of a control signal output from the signal selector and a dot clock of a converted control signal output from the frequency converter according to a comparison result of the comparison unit; A data generator for converting data supplied from the system to have the second driving frequency according to a comparison result of the comparator, and supplying the converted data to the data driver according to a dot clock supplied from the clock selector; A drive device for a liquid crystal display device, characterized in that provided. The method of claim 11, The data generator, A data selection unit for selectively outputting data supplied from the system according to a comparison result of the comparison unit; A write memory for storing the data output by selection of the data selection unit in units of frames; Data alignment for storing at least two frame data of frame unit data stored in the write memory or storing data supplied from the data selector and outputting the stored data to the data driver according to a dot clock from the clock selector. And a driving unit of the liquid crystal display device. 13. The method of claim 12, And the data generator further includes a read memory which reads data in frame units stored in the write memory and supplies the data to the data alignment unit. The method of claim 8, The first driving frequency is less than 60Hz, the second driving frequency is 60Hz or more drive device of the liquid crystal display device. The method of claim 14, And the second driving frequency is 75 Hz. delete delete delete delete delete Providing a liquid crystal panel in which a liquid crystal cell is formed at each intersection of the gate lines and the data lines; Generating data and control signals having a first driving frequency; Comparing the first driving frequency with a second driving frequency and converting the first driving frequency into the second driving frequency and supplying the second driving frequency to the liquid crystal panel according to the comparison result; Converting to the second driving frequency, Generating a dot clock using the control signals based on the vertical synchronization signal of the first driving frequency through a signal generator; Comparing a vertical synchronous signal of the first driving frequency with the vertical synchronous signal of the second driving frequency through a comparison unit; Selectively outputting the control signals of the first driving frequency and the control signals of the second driving frequency according to the comparison result through a signal selecting unit; Converting the control signals output from the signal selector to the second driving frequency according to a comparison result of the comparator through a frequency converter; Driving each of the gate driver and the data driver using any one of the converted control signals of the second driving frequency supplied from the frequency converter and the control signals of the second driving frequency output from the signal selector. And generating a gate control signal and a data control signal for the liquid crystal display. The method of claim 21, And the control signal is a vertical synchronization signal, a horizontal synchronization signal, and a clock signal. The method of claim 21, Converting to the second driving frequency, Selecting and outputting any one of a dot clock of a control signal output from the signal selector and a dot clock of the converted control signal according to a comparison result of the comparator using a clock selector; And converting the data having the first driving frequency to have the second driving frequency according to the comparison result of the comparing unit. The method of claim 23, Converting the data, Selectively outputting data having the first driving frequency according to a comparison result of the comparing unit; Storing data having the first output frequency selectively output in units of frames using a memory; Storing and aligning at least two frame data of the frame unit stored in the memory; And outputting the aligned data according to a dot clock supplied from the clock selector to supply data having the second driving frequency to the data lines. The method of claim 21, Wherein the first driving frequency is less than 60 Hz, and the second driving frequency is 60 Hz or more. The method of claim 25, And the second driving frequency is 75 Hz.

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