KR20160048274A - Display Device - Google Patents

Abstract

According to the present invention, a display device comprises a display panel, a power module, a timing controller, and a gate driving unit. A gate line is arranged on the display panel. The power module varies a voltage level of at least one of a gate high voltage or a gate low voltage. The timing controller synchronizes the gate high voltage and the gate low voltage, that the power module outputs, with a gate control signal. The gate driving unit outputs a gate pulse based on the gate high voltage and the gate low voltage that the power module provides and outputs a gate pulse in which a voltage level of at least one of the gate high voltage or the gate low voltage is varied.

Description

[0001]

The present invention relates to a display device.

The flat panel display includes a liquid crystal display (LCD), a field emission display (FED), a plasma display panel (PDP), and an organic light emitting diode (OLED) ). In a flat panel display device, pixels are formed in an area where data lines and gate lines cross each other.

Video data voltages to be displayed are supplied to the data lines and gate pulses are sequentially supplied to the gate lines. The video data voltage is supplied to the pixels of the display line to which the scan pulse is supplied and the video data is displayed while all the display lines are sequentially scanned by the scan pulse.

In recent years, the panel of the display device is often made large, and the length of the gate line is increasing with the panel becoming a large screen. The self-resistance increases as the length of the gate line becomes long, and the delay of the gate pulse becomes a problem at a position distant from the input terminal of the gate pulse. When the delay phenomenon of the gate pulse becomes severe, not only the period in which the gate pulse is supplied is shortened but also the switch element, for example, the transistor can not be operated in severe cases.

The present invention is intended to provide a display device capable of scanning gate lines at a high speed by operating a switch element in a short time.

A display device of the present invention includes a display panel, a power module, a timing controller, and a gate driver. A gate line is disposed on the display panel. The timing controller generates a control signal synchronized with the gate control signal. The power module modulates at least one of a gate high voltage and a gate low voltage in response to a control signal supplied from the timing controller. The gate driver outputs a gate pulse based on the gate high voltage and the gate low voltage provided by the power module, and outputs a gate pulse in which at least one of the gate high voltage and the gate low voltage is varied.

The present invention can operate the switch element within a short time by increasing the voltage level of the initial section of the gate pulse.

In addition, when the gate pulse of the present invention is lowered, the voltage level of the gate low voltage can be lowered and the gate pulse can be initialized within a short time.

In particular, since the gate high voltage or the gate low voltage of the gate pulse can be modulated without requiring additional circuitry in the gate driver, high-speed driving of a display device having a large-area, high-resolution display panel can be performed with a simple configuration .

1 is a view showing a display device according to the present invention.
2 is a view showing a configuration of a gate drive IC according to the present invention;
3 is a view showing a power module and a gate driver according to a first embodiment;
4 is a diagram showing a drive waveform according to the first embodiment;
5 is a view showing a power module and a gate driver according to a second embodiment;
6 is a view showing a drive waveform according to the second embodiment;
7 is a view showing a power module and a gate driver according to a third embodiment;
8 is a view showing a drive waveform according to the third embodiment;

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Reference will now be made in detail to the preferred embodiments of the present invention, examples of which are illustrated in the accompanying drawings. Like reference numerals throughout the specification denote substantially identical components. In the following description, a detailed description of known functions and configurations incorporated herein will be omitted when it may make the subject matter of the present invention rather unclear.

1 is a view showing a display device according to the present invention.

Referring to FIG. 1, the display device according to the first embodiment includes a display panel 100, a timing controller 110, a data driver 130, and a gate driver 140.

The display panel 100 includes a plurality of pixels P and displays an image based on the gradation displayed by each of the pixels P. [ A plurality of pixels P are arranged in a matrix in each of the horizontal lines. Each of the pixels P is formed in a region where the data line DL and the gate line GL cross each other. Each pixel P includes a pixel circuit PC that operates in response to a supplied data signal DATA corresponding to a scan signal supplied through a switch element SW connected to a gate line GL and a data line DL, . The pixel circuit PC and the switch element SW may be implemented in different forms according to the type of the display panel, and for example, a transistor which is turned on in response to a gate pulse may be used.

The timing controller 110 receives the timing signals such as the vertical / horizontal synchronizing signals Vsync and Hsync, the data enable signal DE and the clock CLK and outputs the operation timing of the data driver 130 and the gate driver 140 Lt; / RTI > These control signals include a gate timing control signal and a data timing control signal. Also, the timing controller 110 supplies the digital video data RGB to the data driver 130.

The gate timing control signal generated by the timing controller 110 includes a gate start pulse GSP, a gate shift clock GSC, and a gate output enable signal GOE. The data timing control signal generated by the timing controller 110 includes a source start pulse SSP, a source sampling clock SSC and a source output enable signal SOE . The source start pulse (SSP) indicates the starting pixel on the line where data is to be displayed. The source sampling clock SSC indicates the latch operation of data in the data driver 130 based on the rising or falling edge.

The timing controller 110 also generates first and second control signals CON1 and CON2 for controlling the output timings of the gate high voltage VGH and the gate low voltage VGL of the power module 120. [ The timing controller 110 may generate the first and second control signals CON1 and CON2 based on the gate control signal GDC. For example, the timing controller 110 may generate the first and second control signals CON1 and CON2 based on the gate output enable signal GOE. The timing of the gate output enable signal GOE and the first and second control signals CON1 and CON2 will be described in the following embodiments.

The power module 120 generates the first and second gate high voltages VGH1 and VGH2 and the first and second gate low voltages VGL1 and VGL2 based on the input voltage. The first and second gate high voltages VGH1 and VGH2 are used as the high potential driving voltage of the output buffer connected to each gate line GL in the gate driver 140. [ The first and second gate low voltages VGL1 and VGL2 are used as the low potential voltage of the output buffer connected to each gate line GL in the gate driver.

 The power module 120 outputs the first and second gate high voltages VGH1 and VGH2 based on the first control signal CON1 supplied from the timing controller 110. [ The power module 120 also outputs the first and second gate low voltages VGL1 and VGL2 based on the second control signal CON2 supplied from the timing controller 110. [

The data driver 130 may comprise a plurality of source ICs, each of which includes a shift register, a latch, a digital-to-analog converter, an output buffer, and the like. The data driver 130 latches the digital video data RGB under the control of the timing controller 110.

The gate driver 140 generates a gate pulse using a gate control signal supplied from the timing controller 110. The gate control signal includes a gate start pulse (GSP), a gate shift clock (GSC), and a gate output enable (GOE).

The gate start pulse GSP is applied to the first gate drive IC (G-IC) to indicate the start line at which the scan is started so that the first gate drive IC (G-IC) generates the first gate pulse G1 . The gate shift clock GSC is a clock for shifting the gate start pulse GSP. The shift register of the gate ICs (G-ICs) shifts the gate start pulse GSP at the rising edge of the gate shift clock GSC. The gate output enable signal GOE is commonly input to the gate drive ICs (G-ICs). The gate drive ICs (G-ICs) output the first to m-th (m is the number of gate lines) gate pulses during the low logic period of the gate output enable signal GOE.

2 is a view showing a gate drive IC (G-IC) according to the present invention.

2, each gate drive IC (G-IC) has a logic portion (LOGIC) and a buffer portion 147. [ The logic unit LOGIC includes a shift register 141, a level shifter 145, and an AND gate 142 (hereinafter, referred to as an AND gate).

The shift register 141 sequentially shifts a gate start pulse (GSP) according to a gate shift clock (GSC) using a plurality of flip-flops connected in a dependent manner. Each of the AND gates 142 generates an output by logically multiplying the non-inverted output signal of the flip-flop of the shift register 141 and the inverted signal of the gate output enable (GOE). The enable signal GOE which is the gate output is inverted by the inverter 143 and input to one input terminal of the AND gate 142. [ The level shifter 145 shifts the output voltage swing width of the AND gate 142 to a swing width capable of operating the TFT of the liquid crystal display panel. For example, the level shifter 145 provides an output signal to the buffer unit 147 that swings between the first gate low voltage VGL1 and the first gate high voltage VGH. For example, the gate low voltage VGL may be set to a voltage of '-5V', and the first gate high voltage VGH1 may be set to a voltage of '20V'.

The buffer unit 147 modulates the voltage level of the output signal of the level shifter 145. For example, the buffer 147 may vary at least one of the first gate high voltage VGH1 or the first gate low voltage VGL1 of the level shifter 145. [

Embodiments in which the buffer unit 147 modulates the voltage level of the output signal of the level shifter 145 will be described as follows.

FIG. 3 is a diagram showing a buffer 147 according to the first embodiment, and FIG. 4 is a diagram showing timings of a gate control signal and a gate high voltage according to the first embodiment.

The timing controller 110 according to the first embodiment generates a first control signal CON1 for determining the output timing of the gate high voltage and provides the first control signal CON1 to the power module 120. [ The power module 120 generates the first and second gate high voltages VGH1 and VGH2 and swings between the first and second gate high voltages VGH1 and VGH2 based on the first control signal CON1 And outputs the gate high voltage to the gate drive IC (G-IC).

The output timings of the first and second gate high voltages VGH1 and VGH2 will be described below.

The timing controller 110 generates the first control signal CON1 based on the gate output enable signal GOE. The first control signal CON1 is supplied to the power module (not shown) so as to output the second gate high voltage VGH2 during the first interval t1 which is a predetermined interval from the moment when the gate output enable signal GOE starts to fall to the low level 120). In addition, the first control signal CON1 controls the gate high voltage output timing of the power module 120 so as to output the second gate high voltage VGH2 until the subsequent gate output enable signal GOE falls.

The power module 120 receives the first control signal CON1 and outputs the second gate high voltage VGH2 during the first and third periods t1 and t3, And outputs the first gate high voltage VGH1 during the second and fourth periods t2 and t4, which are periods other than the output of the two-gate high voltage VGH2.

The logic unit LOGIC of the gate driving unit 140 receives a gate start pulse GSP, a gate shift clock GSC and a gate output enable GOE from the timing controller 110 to generate a low level voltage and a high level voltage Lt; RTI ID = 0.0 > swing < / RTI > The output signal of the logic part LOGIC swings between the gate low voltage VGL and the first gate high voltage VGH1.

The buffer BUF of the i-th buffering unit 147 receives an output signal generated by the logic unit LOGIC to generate an i-th gate pulse Gi supplied to the ith gate line Output. The low potential input of the buffer BUF is provided with the gate low voltage VGL and the high potential input is provided with the first or second gate high voltage VGH2. Each buffer BUF uses a variable gate high voltage as a driving voltage to vary the high level voltage of the output signal generated by the logic unit LOGIC.

That is, during the first period t1, the first buffer of the buffer unit 147 outputs the first gate pulse G1 using the second gate high voltage VGH2 supplied to the high potential input terminal. During the second period t2, the first buffer of the buffer unit 147 outputs the first gate pulse G1 corresponding to the first gate high voltage VGH1 supplied to the high potential input terminal. The first buffer of the buffer unit 147 causes the high level voltage of the first gate pulse G1 to be synchronized with the gate high voltage VGH output from the power module 120. [

In the first embodiment described above, the timing controller 110 outputs the first control signal CON1 so that the first section t1 in which the second gate high voltage VGH2 is output is synchronized with the output timing of the gate pulse . As a modified embodiment, the timing controller 110 controls the power module 120 (FIG. 1) to output the second gate high voltage VGH2 at a point earlier than the point at which the gate pulse is output in order to rapidly increase the voltage level of the initial section of the gate pulse. The first control signal CON1 for controlling the first control signal CON2.

As described above, the gate driver 140 according to the first embodiment can modulate the gate high voltage VGH using the first and second gate high voltages VGH1 and VGH2 generated in the power module 120. [ That is, the gate driver 140 according to the first embodiment can vary the voltage level of the gate high voltage (VGH) without constructing an additional circuit.

In the gate pulse according to the first embodiment, the second gate high voltage VGH2, which is the voltage level in the initial period of the gate high voltage, is set to be higher than the voltage of the first gate high voltage VGH1, which is the voltage level of the general gate pulse Exhibits a pre-emphasis effect. Therefore, since the gate pulse according to the first embodiment can turn on the switch element SW in a short time, high-speed driving is possible, which is advantageous for application to a high-resolution large-area display panel.

FIG. 5 is a diagram showing a buffer 147 according to the second embodiment, and FIG. 6 is a diagram showing timings of a gate control signal and a gate high voltage according to the second embodiment.

The timing controller 110 according to the second embodiment generates a second control signal CON2 for determining the output timing of the gate low voltage and provides the second control signal CON2 to the power module 120. [ The power module 120 generates the first and second gate low voltages VGL1 and VGL2 and swings between the first and second gate low voltages VGL1 and VGL2 based on the second control signal CON2 And outputs the gate-low voltage to the gate drive IC (G-IC).

The output timings of the first and second gate low voltages VGL1 and VGL2 will be described below.

The timing controller 110 generates the second control signal CON2 based on the gate output enable signal GOE. The second control signal CON2 is supplied to the gate low voltage output terminal of the power module 120 so as to output the first gate low voltage VGL1 while the gate pulse is output, that is, during the low level of the gate output enable signal GOE Timing. The second control signal CON2 is set to output the second gate low voltage VGL2 during the second interval t22 which is a constant interval from the moment when the gate output enable signal GOE starts rising to the high level. Thereby controlling the gate-low voltage output timing of the transistor 120. [

The logic unit LOGIC of the gate driving unit 140 receives a gate start pulse GSP, a gate shift clock GSC and a gate output enable GOE from the timing controller 110 to generate a low level voltage and a high level voltage Lt; RTI ID = 0.0 > swing < / RTI > The output signal of the logic part LOGIC swings between the gate low voltage VGL and the first gate high voltage VGH1.

The buffer BUF of the i-th buffering unit 147 receives an output signal generated by the logic unit LOGIC to generate an i-th gate pulse Gi supplied to the ith gate line Output. The low potential input of the buffer BUF is provided with a first or second gate low voltage VGL2 and the high potential input is provided with a gate high voltage VGH. Each buffer BUF changes a low level voltage of an output signal generated by a logic unit (LOGIC) by using a variable gate low voltage as a low potential driving voltage.

That is, during the first period t21, the first buffer of the buffer unit 147 outputs the first gate pulse G1 using the first gate low voltage VGL1 supplied to the low potential input terminal. During the second period t22, the first buffer of the buffer unit 147 outputs the first gate pulse G1 corresponding to the second gate-low voltage VGL2 supplied to the low-potential input terminal. The first buffer of the buffer unit 147 causes the low level voltage of the first gate pulse G1 to be synchronized with the gate low voltage VGL output from the power module 120. [

In the second embodiment described above, the timing controller 110 generates the second control signal CON2 so that the second section t22 at which the second gate low voltage VGL2 is output is synchronized with the falling point of the gate pulse Based on the examples. As a modified embodiment, the timing controller 110 controls the power module 120 to output the second gate low voltage VGL2 at a point earlier than the point at which the gate pulse is lowered to increase the falling speed of the gate pulse Lt; RTI ID = 0.0 > CON2 < / RTI >

As described above, the gate driver 140 according to the second embodiment can modulate the gate low voltage VGL of the gate pulse using the first and second gate low voltages VGL1 and VGL2 generated in the power module 120 have. That is, the gate driver 140 according to the second embodiment can vary the voltage level of the gate low voltage (VGL) without forming additional circuits.

The gate driver 140 according to the second embodiment sets the voltage level at the time when the gate pulse falls at the second gate low voltage (VGL2) of the voltage level lower than the normal first gate low voltage (VGL1) It is possible to increase the polling timing. That is, in the gate driver 140 according to the second embodiment, the turn-off of the switch SW is performed to prevent the data voltage of the pixels P arranged on the horizontal line adjacent to the pixels P from being charged can do.

FIG. 7 is a diagram showing a buffer 147 according to the third embodiment, and FIG. 8 is a diagram showing timings of a gate control signal and a gate high voltage according to the third embodiment. In the third embodiment, substantially the same components as those in the above-described embodiment will not be described in detail.

The timing controller 110 according to the first embodiment generates a first control signal CON1 for determining the output timing of the gate high voltage and provides the first control signal CON1 to the power module 120. [ The power module 120 generates the first and second gate high voltages VGH1 and VGH2 and swings between the first and second gate high voltages VGH1 and VGH2 based on the first control signal CON1 And outputs the gate high voltage to the gate drive IC (G-IC).

The output timings of the first and second gate high voltages VGH1 and VGH2 will be described below.

The timing controller 110 generates the first and second control signals CON1 and CON2 based on the gate output enable signal GOE. The first control signal CON1 is supplied to the power module (not shown) so as to output the second gate high voltage VGH2 during the first interval t31, which is a constant interval from the moment when the gate output enable signal GOE starts to fall to the low level 120). In addition, the first control signal CON1 controls the gate high voltage output timing of the power module 120 so as to output the second gate high voltage VGH2 until the subsequent gate output enable signal GOE falls.

The second control signal CON2 is supplied to the gate low voltage output terminal of the power module 120 so as to output the first gate low voltage VGL1 while the gate pulse is output, that is, during the low level of the gate output enable signal GOE Timing. The second control signal CON2 is set to output the second gate low voltage VGL2 during the second interval t22 which is a constant interval from the moment when the gate output enable signal GOE starts rising to the high level. Thereby controlling the gate-low voltage output timing of the transistor 120. [

The power module 120 according to the third embodiment generates the first and second gate low voltages VGL1 and VGL2 and generates the first and second gate low voltages VGL1 and VGL2 based on the gate control signal And outputs the swinging gate low voltage to the gate drive IC (G-IC). The power module 120 generates first and second gate high voltages VGH1 and VGH2 and generates a gate high voltage VGH2 swinging between the first and second gate high voltages VGH1 and VGH2 based on the gate control signal To the gate drive IC (G-IC).

The power module 120 outputs the second gate high voltage VGH2 during the first interval t31 which is a constant interval from the moment when the gate output enable signal GOE starts to fall to the low level. The power module 120 outputs the second gate high voltage VGH2 until the subsequent gate output enable signal GOE falls.

The power module 120 outputs the first gate low voltage VGL1 during the period when the gate pulse is output, that is, while the gate output enable signal GOE is at the low level. The power module 120 outputs the second gate low voltage VGL2 during the third interval t33, which is a constant interval from the moment when the gate output enable signal GOE starts to rise to the high level.

The logic unit LOGIC of the gate driving unit 140 receives a gate start pulse GSP, a gate shift clock GSC and a gate output enable GOE from the timing controller 110 to generate a low level voltage and a high level voltage Lt; RTI ID = 0.0 > swing < / RTI > The output signal of the logic LOGIC swings between the gate-low voltage GOE and the first gate-high voltage VGH1.

The buffer BUF of the i-th buffering unit 147 receives an output signal generated by the logic unit LOGIC to generate an i-th gate pulse Gi supplied to the ith gate line Output. The low potential input of the buffer BUF is provided with a first or second gate low voltage VGL2 and the high potential input is provided with a first or second gate high voltage VGH2. Each buffer BUF changes a low level voltage of an output signal generated by a logic unit (LOGIC) by using a variable gate low voltage as a low potential driving voltage. Each buffer BUF uses a variable gate high voltage as a high potential driving voltage, and an output signal generated by the logic LOGIC varies a high level voltage.

As a result, the gate driver 140 according to the third embodiment outputs an initial emphasis waveform that increases the gate high voltage during the first period t31, and lowers the gate low voltage during the third period t33. That is, the gate driver 140 according to the third embodiment can quickly turn on the switch element SW of the pixel P, which is advantageous for application to a display panel having a short scan period. In addition, the gate driver 140 according to the third embodiment can quickly turn off the switch element SW of the pixel P, thereby preventing the data voltage from being wrongly supplied to the pixels between adjacent horizontal lines have.

It will be apparent to those skilled in the art that various modifications and variations can be made in the present invention without departing from the spirit or scope of the invention. Therefore, the technical scope of the present invention should not be limited to the contents described in the detailed description of the specification, but should be defined by the claims.

100: display panel 110: timing controller
120: Power module 130: Data driver
140: Gate driver

Claims (6)

A display panel on which gate lines are arranged;
A timing controller for generating a control signal synchronized with the gate control signal;
A power module for modulating at least one of a gate high voltage and a gate low voltage in response to the control signal received from the timing controller; And
And a gate driver for outputting a gate pulse based on the gate high voltage and the gate low voltage provided by the power module and outputting a gate pulse in which at least one of a gate high voltage and a gate low voltage is varied Display device.
The method according to claim 1,
Wherein the timing controller generates the control signal based on an output timing of the gate output enable signal.
The method according to claim 1,
The gate driver
A logic portion for generating an output signal that swings between a first gate low voltage and a first gate high voltage; And
And a buffer receiving the output signal of the logic unit and receiving the gate low voltage generated by the power module as a low potential input terminal and providing the gate high voltage generated by the power module to a high potential input terminal, .
The method of claim 3,
The timing controller controls the gate high voltage output timing of the power module so that the power module outputs a second gate high voltage having a voltage higher than the first gate high voltage for a predetermined period during an initial period in which the gate pulse is output The first control signal is generated,
And the gate driver outputs gate pulses synchronized with the first and second gate high voltages.
The method of claim 3,
The timing controller controls the gate low voltage output timing of the power module so that the power module outputs a second gate low voltage having a voltage lower than the first gate low voltage for a predetermined period of time at the end of the gate pulse Generates a second control signal,
And the gate driver outputs gate pulses synchronized with the first and second gate low voltages.
The method of claim 3,
Wherein the timing controller outputs a second gate high voltage having a voltage higher than the first gate high voltage for a predetermined period during an initial period in which the power module outputs the gate pulse, Generating a first control signal and a second control signal for respectively controlling a gate high voltage and a gate low voltage output timing of the power module to output a second gate low voltage having a voltage lower than the first gate low voltage,
And the gate driver outputs gate pulses synchronized with the first and second gate high voltages and the first and second gate low voltages.

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