KR102589904B1 - Display Device - Google Patents

Abstract

The display device according to the present invention includes a display panel on which a plurality of pixels are arranged, a system, a timing controller, a gate driver, and a data driver. The system outputs a variable vertical synchronization signal that is toggled at least twice within the video data and vertical blank. The timing controller receives a variable vertical synchronization signal from the system, sets the time when the variable vertical synchronization signal is last toggled as the reference toggle timing, and generates a gate control clock after a predetermined period of time has elapsed from the reference toggle timing. Generates gate signals that are synchronized with the timing of the gate control clock. Image data is converted into data voltage, and the data voltage is written to the pixel under the control of gate signals.

Description

Display Device

The present invention relates to a display device.

Flat panel displays (FPDs) are widely used not only in desktop computer monitors but also in portable computers such as laptop computers and tablets and mobile phone terminals due to their advantages of miniaturization and weight reduction. These flat panel displays include liquid crystal displays; LCD), Plasma Display Panel (PDP), Field Emission Display; FED) and Organic Light Emitting Diode Display (OLED).

A flat panel display device receives image data and timing signals from the system and generates various timing control signals based on this. In some cases, the frame time of the display device is not constant, which causes the timing control signal to be output at an undesirable timing.

Additionally, because the frame length is variable, a phenomenon in which luminance is lowered in a specific frame may occur.

The purpose of the present invention is to provide a display device that can improve malfunctions that occur due to misalignment of the output timing of a timing control signal.

Additionally, the object is to provide a display device that can improve a phenomenon in which luminance is lowered due to a change in the vertical blank period.

The display device according to the present invention includes a display panel on which a plurality of pixels are arranged, a system, a timing controller, a gate driver, and a data driver. The system outputs a variable vertical synchronization signal that is toggled at least twice within the video data and vertical blank. The timing controller receives a variable vertical synchronization signal from the system, sets the time when the variable vertical synchronization signal is last toggled as the reference toggle timing, and generates a gate control clock after a predetermined period of time has elapsed from the reference toggle timing. Generates gate signals that are synchronized with the timing of the gate control clock. Image data is converted into data voltage, and the data voltage is written to the pixel under the control of gate signals.

Since the present invention determines the timing of gate signals in response to changes in the period of vertical blanking, malfunctions due to timing errors in gate signals can be prevented.

The present invention can improve the phenomenon of lowering luminance due to an increase in the vertical blank period by adjusting the emission period of the pixel in response to the change in the vertical blank period.

1 is a diagram showing a display device according to a first embodiment.
Figure 2 is a diagram showing a communication protocol between a system and a timing controller according to the first embodiment.
Figure 3 is a diagram showing an example of a variable vertical synchronization signal.
Figure 4 is a diagram showing a communication protocol between a system and a timing controller according to a comparative example.
Figure 5 is a diagram showing a display device according to a second embodiment.
FIG. 6 is a diagram explaining driving of a display device according to the second embodiment.
Figure 7 is a diagram showing a communication protocol between a system and a timing controller according to a second embodiment.
Figure 8 is a diagram explaining a method of setting back porch information of the system according to the present invention.

Hereinafter, preferred embodiments according to the present invention will be described in detail with reference to the attached drawings. Like reference numerals refer to substantially the same elements throughout the specification. In the following description, if it is determined that a detailed description of a known function or configuration related to the present invention may unnecessarily obscure the gist of the present invention, the detailed description will be omitted.

1 is a diagram showing a display device according to a first embodiment.

Referring to FIG. 1, the display device according to the first embodiment includes a display panel 100, a data driver 300, a gate driver 400 and 500, and a timing controller 200.

A plurality of data lines (DL1 to DLm) and a plurality of gate lines (GL1 to GLn) are disposed in the display area (AA) of the display panel 100, and pixels (P) for image display are placed in the intersection area thereof. It is placed.

Each of the gate lines (GL1 to GLn) may include a scan line, an emission line, etc., and may vary depending on the embodiment of the pixel (P).

The timing controller 200 controls a data control signal and a gate control signal based on timing signals such as the vertical synchronization signal (Vsync), horizontal synchronization signal (Hsync), and data enable signal (DE) provided from the system 100. Create. The data control signal controls the operation timing of the data driver 300, and the gate control signal controls the operation timing of the gate drivers 400 and 500.

The data driver 300 generates a data voltage based on the data control signal and image data (DATA) provided from the timing controller 200 and supplies it to the data lines DL1 to DLm.

The gate drivers 400 and 500 include a level shifter 400 and a shift register 500. The level shifter 400 generates a gate clock (GCLK) based on the gate control signal provided from the timing controller 200. The shift register 500 generates a gate signal based on the gate clock (GCLK) output by the level shifter 400 and outputs it to the gate lines (GL). For this purpose, the shift register 500 includes shift registers that are dependently connected to each other. The shift register 500 may be formed directly on the non-display area (NAA) of the display panel (DIS) according to the gate-driver in panel (GIP) method.

FIG. 2 is a diagram illustrating a communication protocol between a system and a timing controller according to the first embodiment. Figure 3 is a diagram specifically explaining the timing of the period of the variable vertical synchronization signal.

Referring to FIG. 2, the system 100 transmits a variable vertical synchronization signal (Vsync_A) and a data enable signal (DE).

The timing controller 200 generates a gate control clock at a time delayed by a preset period from the reference timing within the vertical blank (VB). The nth vertical blank (VBn) starts from the timing when the data enable signal (DE) ends at the nth vertical active (VAn) to the data enable signal (DE) at the n+1th vertical active (VA(n+1)). It is defined as the timing when starts. The reference timing is a timing that precedes the end of the vertical blank (VB) by a preset period and is the same for each frame. The reference timing can be set to the second toggling time point (t2) of the variable vertical synchronization signal (Vsync_A).

The variable vertical synchronization signal (Vsync_A) toggles at least twice within the vertical blank (VB). The variable vertical synchronization signal (Vsync_A) is either a high voltage or a low voltage, and toggling can be defined as changing the voltage level. Hereinafter, this specification will focus on an embodiment in which the variable vertical synchronization signal (Vsync_A) toggles twice at the first timing (t1) and the second timing (t2) within the vertical blank (VB).

As shown in Figure 3, within each frame, the interval from the first timing (t1) to the second timing (t2) in the vertical blank (VB) is variable, and from the second timing (t2) to the third timing (t3) ) is fixed. That is, the interval from the start of the vertical blank (VB) to the first toggling timing of the variable vertical synchronization signal (Vsync_A) is variable, and the interval from the second toggling timing (t2) of the variable vertical synchronization signal (Vsync_A) to the vertical blanking time is variable. The interval until the end point (t3) of (VB) is fixed.

As shown in (a) of FIG. 3, the variable section in the variable vertical synchronization signal (Vsync_A) ranges from the start time (t1) of the vertical blank (VB) to the second toggling time (t2) of the variable vertical synchronization signal (Vsync_A). It can be set up to. Alternatively, the variable section in the variable vertical synchronization signal (Vsync_A) is from the start time (t1) of the vertical blank (VB) to the first toggle timing of the variable vertical synchronization signal (Vsync_A), as shown in (b) of FIG. can be set. In the embodiment shown in (b) of FIG. 3, the interval from the first toggling time of the variable vertical synchronization signal (Vsync_A) to the second toggling time (t2) may be fixed.

The gate control clock may include a start clock (VST) and a gate clock (GCLK). The start clock (VST) determines the output timing of the start signal output from the shift register 500, and the gate clock (GCLK) determines the output timing of the gate signal output from the shift register 500.

The timing controller 200 generates the start clock (VST) when the start setting period (d1) has elapsed from the second toggling of the variable vertical synchronization signal (Vsync_A). The start setting period (d1) may be set so that the generation timing of the start clock (vst) is before the start timing of the vertical active (VA).

The timing controller 200 generates the gate clock (GCLK) when the gate setting period (d2) has elapsed from the second toggling of the variable vertical synchronization signal (Vsync_A). The gate setting period (d3) can be set to be longer than the fixed period (df). If the display panel 100 includes dummy pixels in the non-display area (NAA), and the gate driver generates a gate signal to be applied to the dummy pixels, the gate setting period (d2) may be set to be less than the fixation period (df). It may be possible.

The fixation period (df) for each frame is the same. Likewise, for each frame, the start setting period (d1) is the same and the gate setting period (d2) is the same.

Since the reference timing (t2) and the start point of the vertical active (VA) period are the same for each frame, and the start setting period (d2) is the same for each frame, the start clock (VST) is generated from each vertical active (VA) period for each frame. The timing of this creation is the same. For example, the interval between the start clock (VST) generated within the nth vertical blank (VB) and the end of the nth vertical blank (VB), and the start clock (VST) generated within the n+1th vertical blank (VB) ) and the end point of the nth vertical blank (VB) are the same as 'd1'.

Likewise, the timing at which the gate clock (GCLK) starts to be generated from the start of the vertical active (VA) for each frame is the same. For example, if the gate setting period (d2) is set equal to the fixation period (df), the gate clock (GCLK) begins to be generated in synchronization with the start point of the vertical active (VA) in all frames.

As seen, the first embodiment can generate gate signals at a constant timing from the start of the vertical active (VA) period regardless of the change in the vertical blank (VB) period.

The period during which the vertical blank (VB) is maintained may vary due to a difference in the time required to render image data (DATA) within the system 100. If the system 100 does not render the image and still transmits predetermined image data (DATA) to the timing controller 200, all frames have the same period. However, when the system 100 performs image rendering, the time for rendering image data (DATA) for each frame may vary. In particular, video display devices such as AR or VR often render images in real time, so the frame period varies. If the frame period changes like this, the vertical blank (VB) period changes.

If the vertical blank (VB) period changes, a problem may occur in which the output timing of gate signals varies. Looking at this, it is as follows.

Figure 4 is a diagram explaining how a timing controller generates gate signals according to a comparative example.

Referring to FIG. 4, the timing controller according to the comparative example generates a gate control clock based on the point in time when the vertical active (VA) ends and the data enable signal (DE) begins to be maintained at a low level for a certain period of time. That is, in the comparative example, the output point of the gate control clock is determined based on the start point of the vertical blank (VB) period. Therefore, if the vertical blank (VB) period changes, the output timing of the gate control clock changes. For example, if the second vertical blank (VB) period is extended by '△t' compared to the first vertical blank (VB) period, the start clock (VST) and gate clock (GCLK) are set to '△' compared to the timing for normal driving. It is output as early as t'. As a result, the timing of writing video data (DATA) is misaligned and errors occur in video display.

The variable vertical synchronization signal (Vsync_A) of the present invention can generate gate control clocks (VST, GCLK) at a constant timing from the start of the vertical active (VA) period even if the vertical blank (VB) period is changed due to image rendering, etc. there is. As a result, the timing of gate signals generated by the shift register is kept constant for each frame, ensuring reliability of driving timing.

Figure 5 is a diagram showing a display device according to a second embodiment. Figure 6 is a diagram showing the light emission timing of the display device in the second embodiment. For configurations that are substantially the same as the above-described first embodiment, the representation in the drawings and detailed description will be omitted.

Referring to FIGS. 5 and 6 , the display device according to the second embodiment includes an input terminal of a high-potential driving voltage (VDD) and a shutter unit 600 that switches a current path between pixels (P).

The data driver 300 writes a data voltage (Vdata) to the pixels (P) through the data line (DL) during the vertical active (VA) of each frame.

The shutter unit 600 electrically connects the input terminal of the high-potential driving voltage (VDD) to the pixels (P) in response to the shutter control signal (GS) of the turn-on voltage. The shutter control signal GS maintains the turn-off voltage in the vertical active (VA) period and maintains the turn-on voltage for at least a certain period of time in the vertical blank (VB) period. The shutter unit 600 includes a switching transistor and may be implemented by converting the shutter control signal GS, which is a logic voltage, into an analog voltage to operate the switching transistor.

During the vertical active (VA) period within one frame, all pixels (P) receive data voltage (Vdata) in a line sequential manner. During the vertical active (VA) period, each pixel (P) and the input terminal of the high potential driving voltage (VDD) are electrically blocked, so each pixel (P) does not emit light.

In the vertical blank (VB) period, the shutter unit 600 is turned on so that each pixel (P) is simultaneously provided with a high potential driving voltage (VDD), and thus emits light simultaneously.

In this way, the display device of the second embodiment can improve the response speed (Motion Picture Response Time (MPRT)) by emitting all pixels P simultaneously after sequentially writing one frame of image data.

Figure 7 is a diagram showing signal transmission timing between a system and a timing controller according to a second embodiment. Detailed descriptions of configurations that are substantially the same as those of the embodiment described above in FIG. 7 will be omitted.

Referring to FIG. 7, the system 100 transmits a variable vertical synchronization signal (Vsync_A) and a data enable signal (DE).

The timing controller 200 generates the gate control clocks (VST, GCLK) and the shutter control signal (GS) at a time delayed by a preset period from the reference timing in the vertical blank (VB).

The timing controller 200 generates the start clock (VST) when the start setting period (d1) has elapsed from the second toggling time (t2) of the variable vertical synchronization signal (Vsync_A). And the timing controller 200 generates the gate clock (GCLK) when the gate setting period (d2) has elapsed from the second toggling time (t2) of the variable vertical synchronization signal (Vsync_A).

Additionally, the timing controller 200 inverts the shutter control signal GS to the turn-on voltage at the timing when the data enable signal DE is polled from the vertical blank VB to the low voltage. The timing controller can check the vertical active (VA) based on the vertical resolution information, and changes the polling time of the data enable signal (DE) from the timing when the vertical active (VA) ends to the starting timing of the vertical blank (VB). decide

And the timing controller 200 turns the shutter control signal (GS) of the turn-on voltage at the timing when the shutter control setting period (d3) has elapsed from the second toggling time (t2) of the variable vertical synchronization signal (Vsync_A). Invert to off voltage. The shutter control setting period d3 is set to be no longer than the fixation period df, so that the light-emitting period of the pixel P is limited within the vertical blank VB.

In the display device according to the second embodiment, the turn-on voltage of the shutter control signal (GS) becomes longer in proportion to the vertical blank (VB) period.

If the output timing of the shutter control signal (GS) is fixed for each frame, the luminance is lowered because the non-emission period becomes longer in frames where the vertical blank (VB) period becomes longer.

In contrast, the display device according to the second embodiment sets the light emission period to be long in proportion to the vertical blank (VB) period. Accordingly, the second embodiment can improve the phenomenon of lowering luminance due to the expansion of the vertical blank (VB) period.

Figure 8 is a diagram explaining a method of determining the timing of signals transmitted by the system.

2 and 7, the fixation period (df), start setting period (d1), gate setting period (d2), and shutter control setting period (d3) within the vertical blank (VB) are preset values. is fixed, and the system 100 and the timing controller 200 can implement the first and second embodiments described above based on prearranged procedures.

In contrast, in the present invention, the fixation period (df), start setting period (d1), gate setting period (d2), shutter control setting period (d3), etc. within the vertical blank (VB) are not set in advance, and the system ( It may also be determined by communication between 100) and the timing controller 200.

Referring to FIG. 8, image data (DATA) transmitted from the system 100 to the timing controller 200 includes back porch information (BP info).

Back porch information (BP info) may be transmitted between the falling edge and rising edge of the variable vertical synchronization signal (Vsync_A). In this case, the interval between the falling edge and the rising edge of the variable vertical synchronization signal (Vsync_A) is set to be longer than the transmission time of the back porch information (BP info).

The back porch information (BP info) is the interval of the classic period (df) corresponding to the interval from the second toggling timing (t2) of the variable vertical synchronization signal (Vsync_A) to the end of the vertical blank (VB), the vertical blank ( VB) may include information such as a fixation period (df), a start setting period (d1), a gate setting period (d2), and a shutter control setting period (d3).

The timing controller 200 may receive predefined back porch information (BP info) from the system 100 and generate driving signals based on this. Alternatively, the system 100 may provide predefined back porch information (BP info) to the timing controller 200, and the timing controller 200 may determine whether to utilize the back porch information (BP info). The timing controller 200 uses the back porch information (BP info) transmitted by the system 100 as is, or uses the back porch information (BP info) defined in the timing controller 200. You can request to retransmit back porch information (BP info). Alternatively, the system 100 accesses the Extended Display Identification Data (EDID) or checks the back porch information (BP info) through the timing controller 200, and drives and operates according to the display timing and system situation. Video signals can be transmitted along with back porch information (BP info).

The second toggling timing (t2) of the variable vertical synchronization signal (Vsync_A) is set in consideration of the variable period of the vertical blank (VB). That is, the system 100 can expand the vertical blank (VB) by delaying the second toggling timing (t2) of the variable vertical synchronization signal (Vsync_A) as much as the frame period is required to be expanded in the image rendering process.

Through the above-described content, those skilled in the art will be able to see that various changes and modifications can be made without departing from the technical idea of the present invention. Therefore, the technical scope of the present invention should not be limited to what is described in the detailed description of the specification, but should be defined by the scope of the patent claims.

100: display panel 200: timing controller
300: data driving circuit 400,500: gate driving circuit

Claims (11)

A display panel with a plurality of pixels arranged;
A system that outputs video data and a variable vertical synchronization signal that is toggled at least twice within the vertical blank; and
Timing to receive the variable vertical synchronization signal from the system, set the time when the variable vertical synchronization signal is last toggled as a reference toggle timing, and generate a gate control clock after a predetermined period of time from the reference toggle timing. controller;
a gate driver that generates gate signals synchronized to the timing of the gate control clock; and
A data driver converting the image data into a data voltage and writing the data voltage to the pixel under the control of the gate signals,
The gate control clock includes a start clock and a gate clock,
The interval between the reference toggling timing and the start clock generation timing and the interval between the reference toggling timing and the gate clock generation timing are set to be the same for each frame as a fixed period,
A display device in which the interval from the start of the vertical blank to the reference toggling timing varies for each frame. According to claim 1,
A display device wherein a fixation period from the reference toggling timing of the variable vertical synchronization signal to the end of the vertical blank is set to be the same for each frame. delete According to claim 2,
The timing controller generates the start clock after a start setting period has elapsed from the reference toggling timing, and generates the gate clock after a gate setting period has elapsed from the reference toggling timing. According to claim 4,
The start setting period is set shorter than the fixed period from the reference toggling timing of the variable vertical synchronization signal to the end of the vertical blanking. According to claim 1,
The variable vertical synchronization signal is toggled twice,
The system is a display device that transmits information about a predetermined period for generating the gate control clock between toggling timings of the variable vertical synchronization signal. According to claim 6,
The system is a display device that transmits information about the predetermined period through a channel that transmits the image data. According to claim 1,
The system outputs the image data during vertical activation between adjacent vertical blanks,
The pixel emits light by receiving a high-potential driving voltage from the input terminal of the high-potential driving voltage,
A display device further comprising a shutter control unit that electrically switches the pixel and the input terminal of the high potential driving voltage under the control of a shutter control signal. According to claim 8,
The timing controller is
At the start of the vertical blank period, outputting the shutter control signal as a turn-on voltage,
A display device that outputs the shutter control signal as a turn-off voltage after a shutter control setting period has elapsed from the reference toggling timing. According to clause 9,
The variable vertical synchronization signal is toggled twice,
The system transmits information about the shutter control setting period between toggling timing of the variable vertical synchronization signal. According to claim 10,
The system is a display device that transmits information about the shutter control setting period through a channel that transmits the image data.

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