KR20100096383A - Liquid crystal display - Google Patents

Abstract

PURPOSE: A liquid crystal display is provided to improve image quality by modulating a scan pulse applied to the liquid crystal display. CONSTITUTION: An LCD panel(10) comprises a plurality of gate lines and plurality of data lines. An LCD panel is divided into a first region and a second region. A gate driving circuit(13) generates a first scan pulse and a second scan pulse. The first scan pulse runs a first area. A second scan pulse drives the second region. A gate modulation circuit(14) generates a modulation gate high voltage. The gate modulation circuit makes the slope of RC discharge of the modulation gate high voltage different according to the size of parasitic capacitance.

Description

Liquid Crystal Display

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a liquid crystal display device, and more particularly, to a liquid crystal display device for modifying a waveform of a scan pulse to improve image quality.

A conventional liquid crystal display device displays an image by adjusting the light transmittance of a liquid crystal using an electric field. To this end, the liquid crystal display includes a liquid crystal panel in which liquid crystal cells are arranged in a matrix, and a driving circuit unit for driving the liquid crystal panel. In the liquid crystal panel, the gate lines and the data lines are arranged to cross each other, and the liquid crystal cells are positioned in an area where the gate lines and the data lines cross each other. The liquid crystal panel is provided with pixel electrodes and a common electrode for applying an electric field to each of the liquid crystal cells. Each of the pixel electrodes is connected to one of the data lines via source and drain terminals of a thin film transistor (hereinafter, referred to as a TFT) as a switching element. The gate terminal of the TFT is connected to any one of the gate lines supplied with the scan pulses. The driving circuit unit includes a gate driving circuit for driving the gate lines, a data driving circuit for driving the data lines, and a common voltage generating circuit for driving the common electrode. The gate driving circuit sequentially supplies scan pulses to the gate lines to sequentially drive the liquid crystal cells on the liquid crystal panel by one line. The data driving circuit supplies a data voltage to each of the data lines whenever a scan pulse is supplied to any one of the gate lines. The common voltage generation circuit supplies a common voltage to the common electrode. The liquid crystal display displays an image by adjusting the light transmittance by the potential difference between the pixel electrode and the common electrode.

On the other hand, in the liquid crystal panel of the liquid crystal display, a feed through voltage (ΔVp) corresponding to a difference voltage between the data voltage supplied to the data lines and the liquid crystal cell voltage charged in the liquid crystal cell is generated. The feed through voltage DELTA Vp is generated by the parasitic capacitance existing between the TFT's gate terminal and the liquid crystal cell electrode, and its size varies depending on the parasitic capacitance on the liquid crystal panel, causing flicker. This feed through voltage DELTA Vp is defined by the following equation.

Here, 'Cgs' is the capacitance of the parasitic capacitor formed between the gate terminal and the drain terminal of the TFT, 'Clc' is the capacitance of the liquid crystal capacitor connected between the drain terminal and the common electrode of the TFT, and 'Cst' is the capacitance of the TFT. The capacity of the storage capacitor connected to the drain terminal and the previous gate line. ΔVg is a difference voltage between the gate high voltage and the gate low voltage constituting the scan pulse. The gate high voltage has a level at which the TFT can be turned on, the gate low voltage has a level at which the TFT can be turned off, and a scan pulse is swinged between the gate high voltage and the gate low voltage.

The size of the flicker is proportional to the magnitude of the feed through voltage DELTA Vp, which is particularly caused when the scan pulse falls from the gate high voltage to the gate low voltage. Therefore, in order to reduce the occurrence of flicker, it is necessary to reduce the difference voltage between the gate high voltage VGH and the gate low voltage VGL at the falling edge of the scan pulse. However, in the conventional LCD, since the scan pulse falls directly from the gate high voltage VGH to the gate low voltage VGL at the falling edge of the scan pulse, a lot of flicker is caused and the image quality is deteriorated.

Recently, as shown in FIG. 1, the gate high voltage VGH is lowered from the first level VGH1 to the second level VGH2 near the falling edge of the scan pulse, thereby decreasing the gate high voltage VGH and the gate low voltage VGL. Gate modulation has been proposed to reduce the occurrence of flicker by reducing the difference voltage ΔVg between This gate modulation method modulates the gate high voltage (VGH) using the RC delay phenomenon.

However, the conventional gate modulation method modulates the gate high voltage VGH to a uniform size based on a fixed RC value in the process of adjusting the common voltage using the flicker pattern. As a result, the conventional gate modulation method is difficult to apply the image quality improvement when the degree of flicker is locally changed due to the positional difference of the parasitic capacitance in the panel.

Accordingly, an object of the present invention is to provide a liquid crystal display device which improves image quality by modulating a scan pulse to adaptively correspond to the parasitic capacitance characteristics in a panel.

In order to achieve the above object, a liquid crystal display according to an exemplary embodiment of the present invention includes a liquid crystal in which a plurality of gate lines and a plurality of data lines cross each other, and are divided and driven into first and second regions having different parasitic capacitances. Display panel; A second scan pulse for generating the first scan pulse for driving the first region and a second scan pulse different from the first scan pulse for driving the second region using an input gate low voltage and a modulation gate high voltage. A gate driving circuit generating a; And modulating an input gate high voltage through RC discharge to generate the modulated gate high voltage, and within a predetermined discharge period, based on setting information input from the outside, the modulation gate high voltage according to the magnitude of the parasitic capacitance. A gate modulation circuit for varying the RC discharge slope is provided.

The gate modulation circuit may include: an RC value setting unit for setting a resistance value and a capacitor value for adjusting the RC discharge slope of the modulation gate high voltage; And a modulation unit configured to vary the RC discharge slope of the modulation gate high voltage according to the size of the parasitic capacitance by using a modulation control signal for controlling the resistance value, the capacitor value, the gate high voltage, and the modulation timing. do.

The discharge period is determined in synchronization with the modulation control signal.

The RC discharge slope of the modulation gate high voltage tends to increase as the parasitic capacitance increases.

The modulation gate high voltage may include: a first modulation gate high voltage used to generate the first scan pulse; A second modulation gate high voltage used to generate the second scan pulse; The parasitic capacitance of the second region is greater than the parasitic capacitance of the first region.

The first scan pulse has a first modulated voltage level reduced along a first RC discharge slope from the gate high voltage near its falling edge; The second scan pulse has a second modulated voltage level reduced along the second RC discharge slope from the gate high voltage near its falling edge; The first RC discharge slope is less than the second RC discharge slope, and the first modulation voltage level is higher than the second modulation voltage level.

The RC value setting unit sets the resistance value and the capacitor value by using setting information and a setting clock input from a user interface through I ² C communication.

The liquid crystal display according to the present invention reduces the difference between the gate high voltage and the gate low voltage by lowering the gate high voltage to a level lower than the original level near the falling edge of the scan pulse, thereby preventing flicker from occurring. By varying the difference voltage for each panel region according to the size, the effect of image quality improvement can be greatly improved even if the generation of flicker locally due to the positional difference of the parasitic capacitance in the panel.

Hereinafter, exemplary embodiments of the present invention will be described with reference to FIGS. 2 to 6.

2 shows a liquid crystal display according to an embodiment of the present invention. 3 illustrates an example of an integrated circuit configuring the modulator of FIG. 2, and FIG. 4 illustrates timings of input / output signals of FIG. 3.

2, a liquid crystal display according to an exemplary embodiment of the present invention includes a liquid crystal display panel 10, a timing controller 11, a data driving circuit 12, a gate driving circuit 13, and a gate modulation circuit 14. ).

In the liquid crystal display panel 10, a liquid crystal layer is formed between two glass substrates. The liquid crystal display panel includes m × n liquid crystal cells Clc arranged in a matrix by a cross structure of m data lines DL and n gate lines GL.

Data lines DL, gate lines GL, TFTs, and a storage capacitor Cst are formed on the lower glass substrate of the liquid crystal display panel 10. The liquid crystal cells Clc are connected to the TFT and are driven by an electric field between the pixel electrodes 1 and the common electrode 2. The black matrix, the color filter, and the common electrode 2 are formed on the upper glass substrate of the liquid crystal display panel 10. The common electrode 2 is formed on the upper glass substrate in a vertical electric field driving method such as twisted nematic (TN) mode and vertical alignment (VA) mode, but the in-plane switching (IPS) mode and the fringe field switching (FFS) mode In the same horizontal electric field driving method, the pixel electrode 1 may be formed on the lower glass substrate. A polarizing plate is attached to each of the upper glass substrate and the lower glass substrate of the liquid crystal display panel 10, and an alignment layer for setting the pre-tilt angle of the liquid crystal is formed.

The timing controller 11 receives timing signals such as a data enable signal (DE), a dot clock (CLK), and the like, and receives the data driver circuit 12, the gate driver circuit 13, and the gate modulator circuit 14. Generate control signals for controlling the operation timing of the signal.

The gate control signal GDC for controlling the operation timing of the gate driving circuit 13 may include a gate start pulse (GSP) indicating a start horizontal line at which scanning starts in one vertical period in which one screen is displayed; A gate shift clock signal (Gate Shift) generated at a pulse width corresponding to an ON period of a TFT as a timing control signal input to a shift register in the gate driving circuit 13 to sequentially shift the gate start pulse GSP. Clock: GSC), and a gate output enable signal (GOE) indicating the output of the gate driving circuit 13, and the like.

The data control signal DDC for controlling the operation timing of the data driving circuit 12 is a source sampling instructing the latch operation of data in the data driving circuit 12 based on a rising or falling edge. A clock (Source Sampling Clock: SSC), a source output enable signal (SOE) indicating the output of the data driving circuit 12, and the liquid crystal cells Clc of the liquid crystal display panel 10. And a polarity control signal POL indicating the polarity of the data voltage.

The gate modulation control signal for controlling the operation timing of the gate modulation circuit 14 includes the first control signal DPM for controlling the timing of generation of the modulation gate high voltage MVGH, and the RC discharge of the gate high voltage VGH. And a second control signal FLK for controlling the viewpoint.

In addition, the timing controller 11 rearranges the digital video data RGB input from the external system board to the data driving circuit 12 according to the resolution of the liquid crystal display panel 10.

The data driving circuit 12 based on the gamma reference voltages GMA from the gamma reference voltage generator (not shown) in response to the data control signal DDC from the timing controller 11. The analog gamma compensation voltage is converted into an analog gamma compensation voltage, and the analog gamma compensation voltage is supplied to the data lines DL of the liquid crystal display panel 10 as a data voltage. To this end, the data driving circuit 12 stores a shift register for sampling the clock signal, a register for temporarily storing the digital video data RGB, and one line of data in response to a clock signal from the shift register. A latch for simultaneously outputting data for a line, a digital / analog converter for selecting a positive / negative gamma voltage under reference to a gamma reference voltage corresponding to a digital data value from the latch, and a positive / negative gamma A plurality of data drive integrated circuits include a multiplexer for selecting a data line DL to which analog data converted by voltage is supplied, and an output buffer connected between the multiplexer and the data line DL.

The gate driving circuit 13 synthesizes an input modulation gate high voltage VGHM and a gate low voltage VGL under the control of the gate control signal GDC from the timing controller 11 to supply the data voltage. After generating a scan pulse for selecting a horizontal line of the display panel 10, the scan pulse is sequentially supplied to the gate lines GL. To this end, the gate driving circuit 13 is connected between a shift register, a level shifter for converting the output signal of the shift register into a swing width suitable for TFT driving of the liquid crystal cell Clc, and between the level shifter and the gate line GL. And a plurality of gate drive integrated circuits each including an output buffer.

The gate modulation circuit 14 modulates the gate high voltage VGH such that the RC discharge slope varies according to the size of the parasitic capacitance in the liquid crystal display panel 10 to generate the modulation gate high voltage VGHM. To this end, the gate modulating circuit 14 includes an RC value setting section 14a and a modulating section 14b.

The RC value setting unit 14a uses the setting information SDATA and the setting clock SCLK input from the user interface through I ² C communication to adjust the resistance value RE and the capacitor value for adjusting the RC discharge slope for each position. (CE) occurs. The resistance value RE and the capacitor value CE may be independently generated in units of horizontal driving blocks of the liquid crystal display panel 10 under the direction of the user, in consideration of the fact that the parasitic capacitance of the liquid crystal display panel 10 varies according to positions. Can be. In the inspection process performed after the manufacture of the liquid crystal display device is completed, the user applies a test data pattern to the liquid crystal display device to visually or electrically inspect the degree of flicker generation for each position of the liquid crystal display panel 10. The resistance value RE and the capacitor value CE can be adjusted for each horizontal driving block based on the. The number of horizontal blocks that are divided and driven may be k (k is a natural number of 2 or more). However, for convenience of explanation, the liquid crystal display panel 10 is divided into three horizontal driving blocks, and the resistance value RE and the capacitor value CE are generated independently for each horizontal driving block as an example. Explain. The RC value setting section 14a supplies this resistance value RE and the capacitor value CE to the modulation section 14b.

The modulator 14b includes an integrated circuit having a plurality of input / output terminals P1 to P8 as shown in FIG. 3 to generate a modulation gate high voltage VGHM. In FIG. 3, 'P1' is a terminal to which the gate high voltage VGH is input from the power generation circuit (not shown), 'P2' is a terminal to which the modulation gate high voltage VGHM is output, and 'P3' is RC. The terminal to which the resistance value RE set by the value setting unit 14a is input, 'P4' is the terminal to which the capacitor value CE set by the RC value setting unit 14a is input. Is a terminal to which the high potential power voltage VDD is input from the power generating circuit, 'P6' is a terminal to which the first control signal DPM is input from the timing controller 11, and 'P7' is a ground voltage GND. P8 denotes a terminal to be input, and a terminal to which the second control signal FLK is input from the timing controller 11, respectively. Through such an integrated circuit, the modulator 14b adjusts the level of the modulation gate high voltage VGHM during the discharge period t determined in synchronization with the second control signal FLK as shown in FIG. 4 to the gate high voltage VGH. The voltage level (La, Lb, Lc) after the end of discharge according to the RC discharge slope (s1 to s3) determined by the resistance value (RE) and the capacitor value (CE), but lowered near the high potential power voltage (VDD) at Differently. The level La of the first modulation gate high voltage VGHM determined by the first RC discharge slope s1 having the smallest slope has the highest level so as to correspond to the region with the lowest parasitic capacitance, and the slope is medium. The level Lb of the second modulation gate high voltage VGHM determined by the second RC discharge slope s2 corresponds to a region where parasitic capacitance is intermediate, and thus the level La of the first modulation gate high voltage VGHM. The second modulation gate has a lower level and the level Lc of the third modulation gate high voltage VGHM, which is determined by the third RC discharge slope s3 having the largest slope, corresponds to the region with the largest parasitic capacitance. It has a level lower than the level Lb of the high voltage VGHM.

5 illustrates an example of a scan pulse generated through the gate driving circuit 13 of FIG. 2, and FIG. 6 illustrates driving the liquid crystal display panel 10 in units of horizontal blocks using the scan pulse of FIG. 5. Shows.

5 and 6, the gate driving circuit 13 may include three gate integrated circuits 13a, 13b, and 13c for independently driving the liquid crystal display panel 10 in units of horizontal blocks 10a, 10b, and 10c. ).

The first gate integrated circuit 13a generates the first scan pulse SPa using the modulation gate high voltage VGHM from the gate modulation circuit 14 and the gate low voltage VGL from the power generation circuit. The first scan pulse SPa is supplied to the gate lines GL to drive the first horizontal block 10a. The first scan pulse SPa has a first modulation gate high voltage level La reduced from the gate high voltage VGH along the first RC discharge slope s1 near its falling edge. The first scan pulse SPa is supplied to the first horizontal block 10a having the smallest parasitic capacitance Cgs1 value in the liquid crystal display panel 10.

The second gate integrated circuit 13b generates the second scan pulse SPb using the modulation gate high voltage VGHM from the gate modulation circuit 14 and the gate low voltage VGL from the power generation circuit. The second scan pulse SPb is supplied to the gate lines GL to drive the second horizontal block 10b. The second scan pulse SPb has a second modulated gate high voltage level Lb reduced along the second RC discharge slope s2 from the gate high voltage VGH near its falling edge. The second scan pulse SPb is supplied from the liquid crystal display panel 10 to the second horizontal block 10b having a parasitic capacitance Cgs2 having a medium value.

The third gate integrated circuit 13c generates the third scan pulse SPc using the modulation gate high voltage VGHM from the gate modulation circuit 14 and the gate low voltage VGL from the power generation circuit. The third scan pulse SPc is supplied to the gate lines GL to drive the third horizontal block 10c. The third scan pulse SPc has a third modulation gate high voltage level Lc reduced along the third RC discharge slope s3 from the gate high voltage VGH near its falling edge. The third scan pulse SPc is supplied to the third horizontal block 10c having the largest parasitic capacitance Cgs3 value in the liquid crystal display panel 10.

As described above, the liquid crystal display according to the present invention lowers the gate high voltage to a level lower than the original level near the falling edge of the scan pulse to reduce the difference voltage between the gate high voltage and the gate low voltage to prevent the occurrence of flicker. In addition, by varying the difference voltage for each panel region according to the size of the parasitic capacitance, the effect of image quality improvement can be greatly improved even if the degree of flicker is locally changed due to the positional difference of the parasitic capacitance in the panel.

Those skilled in the art will appreciate that various changes and modifications can be made without departing from the technical spirit of the present invention. Therefore, the technical scope of the present invention should not be limited to the contents described in the detailed description of the specification but should be defined by the claims.

1 is a waveform diagram of a scan pulse generated by a conventional gate modulation method.

2 is a block diagram illustrating a liquid crystal display according to an exemplary embodiment of the present invention.

3 is a diagram illustrating an example of an integrated circuit of the modulator of FIG. 2.

4 is a timing diagram illustrating operation of input / output signals of FIG. 3.

FIG. 5 is a waveform diagram illustrating an example of a scan pulse generated through the gate driving circuit of FIG. 2.

FIG. 6 is a diagram illustrating driving a liquid crystal display panel in units of horizontal blocks by using the scan pulse of FIG. 5. FIG.

Description of the Related Art

10 liquid crystal display panel 11 timing controller

12: data driving circuit 13: gate driving circuit

14: gate modulation circuit 14a: RC value setting section

14b: modulator

Claims (7)

A liquid crystal display panel in which a plurality of gate lines and a plurality of data lines cross each other, and are divided and driven into first and second regions having different parasitic capacitances; A second scan pulse for generating the first scan pulse for driving the first region and a second scan pulse different from the first scan pulse for driving the second region using an input gate low voltage and a modulation gate high voltage. A gate driving circuit generating a; And The modulation gate high voltage is generated by modulating an input gate high voltage through RC discharge, but within a predetermined discharge period, based on the setting information input from the outside, the RC of the modulation gate high voltage according to the magnitude of the parasitic capacitance. And a gate modulation circuit for varying the discharge slope. The method of claim 1, The gate modulation circuit, An RC value setting unit for setting a resistance value and a capacitor value for adjusting the RC discharge slope of the modulation gate high voltage; And And using a modulation control signal for controlling the resistance value, the capacitor value, the gate high voltage, and the modulation timing, to provide a modulation unit for varying the RC discharge slope of the modulation gate high voltage according to the magnitude of the parasitic capacitance. A liquid crystal display device. The method of claim 2, And the discharge period is determined in synchronization with the modulation control signal. The method of claim 1, The slope of the RC discharge of the modulation gate high voltage has a tendency to increase as the parasitic capacitance increases. The method of claim 1, The modulation gate high voltage, A first modulation gate high voltage used to generate the first scan pulse; A second modulation gate high voltage used to generate the second scan pulse; The parasitic capacitance of the second region is greater than the parasitic capacitance of the first region. The method of claim 5, The first scan pulse has a first modulated voltage level reduced along a first RC discharge slope from the gate high voltage near its falling edge; The second scan pulse has a second modulated voltage level reduced along the second RC discharge slope from the gate high voltage near its falling edge; And wherein the first RC discharge slope is smaller than the second RC discharge slope, and the first modulation voltage level is higher than the second modulation voltage level. The method of claim 2, The RC value setting unit sets the resistance value and the capacitor value using setting information and a setting clock input from a user interface through I ² C communication.

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