KR20120072724A

KR20120072724A - Liquid crystal display

Info

Publication number: KR20120072724A
Application number: KR1020100134603A
Authority: KR
Inventors: 김세영; 조규행
Original assignee: 엘지디스플레이 주식회사
Priority date: 2010-12-24
Filing date: 2010-12-24
Publication date: 2012-07-04

Abstract

PURPOSE: A liquid crystal display is provided to optimize a common voltage in the entire screen by inputting a gamma reference voltage with straight polarity symmetric to the optimized common voltage of display position and nonpolar gamma reference voltage according to a source drive IC. CONSTITUTION: A programmable gamma IC generates first, second and third local gamma reference voltages with straight polarity and first, second and third local nonpolar gamma reference voltages. A first source drive IC generates a data voltage with straight polarity by converting a first digital video data to the first local gamma reference voltage with straight polarity and a nonpolar data voltage by converting the first digital video data to the first local nonpolar gamma reference voltage. A second source drive IC generates a data voltage with straight polarity by converting a second digital video data to the second local gamma reference voltage with straight polarity and a nonpolar data voltage by converting the second digital video data to the second local nonpolar gamma reference voltage. A third source drive IC(SIC3) generates a data voltage with straight polarity by converting a third digital video data to the third local gamma reference voltage with straight polarity and a nonpolar data voltage by converting the third digital video data to the third local nonpolar gamma reference voltage.

Description

Liquid Crystal Display {LIQUID CRYSTAL DISPLAY}

The present invention relates to a liquid crystal display device for inputting a local gamma compensation voltage optimized for each position of a screen region of a liquid crystal display panel to source drive ICs (Integrated Circuit).

The liquid crystal display of the active matrix driving method displays a moving image using a thin film transistor (hereinafter referred to as TFT) as a switching element. The liquid crystal display device can be miniaturized compared to a cathode ray tube (CRT) and is widely used as a display device for portable information equipment, office equipment, computers, and televisions.

The liquid crystal of the liquid crystal display device displays an image by changing the transmittance in accordance with the potential difference between the data voltage supplied to the pixel electrode and the common voltage supplied to the common electrode. In general, the common electrode is formed of one electrode film or electrode line over pixels of the entire screen. Therefore, the common voltage is applied to the common electrode as one voltage. However, the common voltage may vary due to the voltage drop depending on the screen position of the liquid crystal display panel. This is because the resistance is increased as the distance from the common voltage application portion in the common electrode. Therefore, when the common voltage is different for each screen position, the image quality is uneven and afterimages appear on the entire screen.

The liquid crystal display is driven in an inversion manner in which the polarity of the data voltage applied to the liquid crystal cell is periodically inverted as shown in FIG. 1 in order to reduce deterioration and afterimage of the liquid crystal. For example, as shown in FIG. 1, a positive data voltage synchronized with the gate pulse GP is charged in the Nth (N is a natural number) frame period, and the liquid crystal cell is charged in the N + 1 frame period. The negative data voltage synchronized with the is charged in the liquid crystal cell. The positive data voltage charged in the liquid crystal cell is lowered by ΔVp by the parasitic capacitance of the TFT and maintained by the storage capacitor Cst for one frame period. The negative voltage charged in the liquid crystal cell is increased by ΔVp and maintained for one frame period by the storage capacitor Cst. In FIG. 1, 'Vdata_255' is a positive / negative data voltage having a gray value '255', and 'Vdata_0' is a positive / negative data voltage having a gray value '0'. 'Vcom' is a common voltage applied to the common electrode.

ΔVp is a feed-through voltage and is defined as in Equation 1.

Where Cgd is the gate-drain parasitic capacitance of the TFT, Cst is the capacitance of the storage capacitor, Clc is the capacitance of the liquid crystal cell, Vgh is the gate high voltage of the gate pulse, and Vgl is the gate low voltage of the gate pulse. .

As can be seen in FIG. 1, when the common voltage Vcom changes according to the screen position of the liquid crystal display panel, the positive data voltage and the negative data voltage become asymmetrical with respect to the common voltage Vcom in the same gray scale. The polarity of the data voltage prevails. When the positive data voltage and the negative data voltage are biased in one of the above manners, the liquid crystal cell is driven by direct current, and afterimages appear on the liquid crystal display panel.

The common voltage Vcom is generally set to one voltage optimized based on the center of the screen. In this case, since the common voltage Vcom depends on the resistance of the common electrode, it is not optimized in other parts than the center of the screen. In order to solve this problem, a method of generating a common voltage Vcom into a plurality of voltages optimized for each screen position and distributing the voltages to a plurality of common electrodes divided on the screen may be considered. Is further added and the electrode structure of the liquid crystal display panel becomes complicated.

The present invention provides a liquid crystal display device capable of optimizing a common voltage and improving image quality over the entire screen.

The liquid crystal display of the present invention includes a first local positive gamma reference voltage, a first local negative gamma reference voltage, a second local positive gamma reference voltage, a second local negative gamma reference voltage, and a third local positive gamma reference A programmable gamma IC generating a voltage and a third local negative gamma reference voltage; Converting first digital video data into the first local positive gamma reference voltage to generate a positive data voltage, supplying the positive data voltage to data lines of the first screen block, and supplying the first digital video data to the A first source drive IC converting the first local negative gamma reference voltage to generate a negative data voltage and supplying the negative data voltage to the data lines of the first screen block; Converting the second digital video data into the second local positive gamma reference voltage to generate a positive data voltage, supplying the positive data voltage to the data lines of the second screen block, and supplying the second digital video data to the A second source drive IC converting the second local negative gamma reference voltage to generate a negative data voltage and supplying the negative data voltage to the data lines of the second screen block; And converting third digital video data into the third local positive gamma reference voltage to generate a positive data voltage, supplying the positive data voltage to data lines of a third screen block, and supplying the third digital video data. And a third source driver IC converting the third local negative gamma reference voltage to generate a negative data voltage and supplying the negative data voltage to the data lines of the third screen block.

The first local positive gamma reference voltage is higher than the second local positive gamma reference voltage, and the second local positive gamma reference voltage is higher than the third local positive gamma reference voltage.

The programmable gamma IC includes a fourth local positive gamma reference voltage, a fourth local negative gamma reference voltage, a fifth local positive gamma reference voltage, a fifth local negative gamma reference voltage, a sixth local positive gamma reference voltage, And generate a sixth local negative polarity gamma reference voltage.

The liquid crystal display converts fourth digital video data into the fourth local positive gamma reference voltage to generate a positive data voltage, and supplies the positive data voltage to data lines of a fourth screen block. And a fourth source drive IC which converts digital video data into the fourth local negative gamma reference voltage to generate a negative data voltage and supplies the negative data voltage to the data lines of the fourth screen block. .

The fourth local positive gamma reference voltage is lower than the second local positive gamma reference voltage and higher than the third local positive gamma reference voltage.

The liquid crystal display converts fifth digital video data into the fifth local positive gamma reference voltage to generate a positive data voltage, and supplies the positive data voltage to data lines of the fifth screen block. And a fifth source drive IC converting digital video data into the fifth local negative gamma reference voltage to generate a negative data voltage and supplying the negative data voltage to the data lines of the fifth screen block. .

The fifth local positive gamma reference voltage is equal to the fifth local positive gamma reference voltage.

The liquid crystal display converts sixth digital video data into the sixth local positive gamma reference voltage to generate a positive data voltage, and supplies the positive data voltage to the data lines of the sixth screen block. And a sixth source drive IC converting digital video data into the sixth local negative gamma reference voltage to generate a negative data voltage and supplying the negative data voltage to data lines of the sixth screen block. .

The sixth local positive gamma reference voltage is equal to the second local positive gamma reference voltage.

The absolute value of the first local negative gamma reference voltage is higher than the absolute value of the second local negative gamma reference voltage, and the absolute value of the second local negative gamma reference voltage is greater than the absolute value of the third local negative gamma reference voltage. high.

The absolute value of the fourth local negative gamma reference voltage is lower than the absolute value of the second local negative gamma reference voltage and higher than the absolute value of the third local negative gamma reference voltage.

The fifth local negative gamma reference voltage is equal to the fifth local negative gamma reference voltage.

The sixth local negative polarity gamma reference voltage is the same as the second local negative polarity gamma reference voltage.

According to the present invention, the common gamma reference voltage and the negative gamma reference voltage, which are symmetrical with the optimum common voltage for each screen position, may be input for each source drive IC to optimize the common voltage and improve image quality of the entire screen.

1 is a waveform diagram illustrating a positive / negative data voltage, a gate pulse, and a common voltage applied to a liquid crystal cell.
FIG. 2 is a diagram illustrating common voltage measurement positions in a common voltage measurement experiment for each screen position of a liquid crystal display panel.
FIG. 3 is a graph showing experimental results showing an optimum common voltage at which afterimages do not appear at each of the measurement positions of FIG. 2.
4 is a diagram illustrating a liquid crystal display according to an exemplary embodiment of the present invention.
FIG. 5 is a diagram illustrating the programmable gamma IC shown in FIG. 4.
FIG. 6 is a plan view showing the appearance and output channel pins of the programmable gamma IC shown in FIG. 4.
FIG. 7 is a block diagram illustrating an internal circuit configuration of the source drive ICs shown in FIG. 4.
8 is a diagram illustrating first local positive gamma reference voltages and first local negative gamma reference voltages input to a first source drive IC.
9 is a diagram illustrating second and sixth local positive gamma reference voltages and second and sixth local negative gamma reference voltages input to the second and sixth source drive ICs.
FIG. 10 is a diagram illustrating fourth and fifth local positive gamma reference voltages and fourth and fifth local negative gamma reference voltages input to fourth and fifth source drive ICs.
FIG. 11 is a diagram illustrating third local positive gamma reference voltages and third local negative gamma reference voltages input to a third source drive IC.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Reference will now be made in detail to the preferred embodiments of the present invention, examples of which are illustrated in the accompanying drawings. Like reference numerals throughout the specification denote substantially identical components. In the following description, when it is determined that a detailed description of known functions or configurations related to the present invention may unnecessarily obscure the subject matter of the present invention, the detailed description thereof will be omitted.

2 and 3 illustrate an experimental result of measuring common voltages at eight positions on the top, center, and bottom of a screen of a 47 ″ IPS (In Plane Switching) mode. The liquid crystal display panel PNL has a length in the horizontal direction and a length in the vertical direction. As a result, the voltage drop of the common voltage Vcom is greater in the horizontal direction of the liquid crystal display panel PNL. As a result, as shown in FIGS. 2 and 3, the deviation of the common voltage Vcom is greater in the horizontal direction than in the vertical direction of the liquid crystal display panel PNL.

The same positive gamma reference voltages and the same negative gamma compensation voltages were input to the source drive ICs used in the experiments of FIGS. 2 and 3. As a result of tuning the common voltage Vcom at each of the measurement positions to optimize the common voltage Vcom where no afterimage appears, the optimum common voltage Vcom is different for each screen position as indicated by "X" in FIG. 3.

The present invention does not separately generate the common voltage for each screen position to implement the optimum common voltage Vcom for each screen position based on the experimental results of FIGS. Optimize the positive / negative gamma reference voltages input to each of the source drive ICs so that the negative data voltages can be implemented symmetrically. As a result, the present invention may obtain the effect of applying one common voltage Vcom to the common electrode of the liquid crystal display panel PNL and implementing the optimum common voltage for each screen position.

4 is a diagram illustrating a liquid crystal display according to an exemplary embodiment of the present invention.

Referring to FIG. 4, the liquid crystal display device of the present invention includes a liquid crystal display panel PNL, source drive ICs SIC1 to SIC6, a gate driving circuit GIP, a programmable gamma IC, and a timing controller. TCON) and the like.

The liquid crystal display panel PNL includes a liquid crystal layer formed between the TFT array substrate and the color filter array substrate. The liquid crystal display panel PNL includes pixels arranged in a matrix by a cross structure of data lines and gate lines. A TFT array is formed on the TFT array substrate of the liquid crystal display panel PNL. The TFT array includes data lines, gate lines, TFTs formed at intersections of data lines and gate lines, a pixel electrode connected to each TFT, a storage capacitor (Cst), and the like. The liquid crystal of the pixels is driven by an electric field between the pixel electrode and the common electrode. The color filter array is formed on the color filter array substrate of the liquid crystal display panel PNL. The color filter array includes a black matrix, a color filter, a common electrode, and the like. A polarizing film is attached to each of the TFT array substrate and the color filter array substrate, and an alignment film for setting the pre-tilt angle of the liquid crystal is formed.

The liquid crystal display panel (PNL) is implemented in a vertical electric field driving method such as twisted nematic (TN) mode and a vertical alignment (VA) mode, or a horizontal electric field driving method such as IPS (In Plane Switching) mode and FFS (Fringe Field Switching) mode. Can be. The liquid crystal display of the present invention may be implemented in any form, such as a transmissive liquid crystal display, a transflective liquid crystal display, a reflective liquid crystal display. In the transmissive liquid crystal display device and the transflective liquid crystal display device, a backlight unit and a backlight driving circuit are required. The backlight unit may be implemented as a direct type backlight unit or an edge type backlight unit.

Each of the source drive ICs SIC1 to SIC6 latches the digital video data RGB of the input image under the control of the timing controller TCON. Each of the source drive ICs SIC1 to SIC6 converts latched digital video data into a positive gamma compensation voltage to generate a positive data voltage, and converts digital video data to a negative gamma compensation voltage to generate a negative data voltage. The positive / negative data voltage is output to the data lines DL. Each of the source drive ICs SIC1 to SIC6 has symmetrical positive gamma compensation voltages and negative gamma compensation voltages based on the optimum common voltage Vcom measured based on the experimental results of FIGS. 2 and 3. Is entered. For this purpose, the positive and negative gamma compensation voltages are separately supplied to the source drive ICs SIC1 to SIC6.

When the screen of the liquid crystal display panel PNL is divided by the area in charge of the source drive ICs SIC1 to SIC6, the first source drive IC SIC1 is applied to the data lines existing in the first screen block D1. Supply polarity / negative data voltage. The second source drive IC SIC2 supplies the positive / negative data voltages to the data lines existing in the second screen block D2. The third source drive IC SIC3 supplies a positive / negative data voltage to data lines existing in the third screen block D3. The fourth source drive IC SIC4 supplies the positive / negative data voltage to the data lines existing in the fourth screen block D4. The fifth source drive IC SIC5 supplies the positive / negative data voltage to the data lines existing in the fifth screen block D5. The sixth source drive IC SIC6 supplies the positive / negative data voltages to the data lines existing in the sixth screen block D6. The source drive ICs SIC1 to SIC6 may be connected to the data lines DL of the liquid crystal display panel PNL by a chip on glass (COG) process or a tape automated bonding (TAB) process.

The gate driving circuit GIP sequentially supplies gate pulses to the gate lines synchronized with the positive / negative data voltage under the control of the timing controller TCON. The gate driving circuit includes a level shifter and a shift register. The gate driving circuit GIP may be connected to the gate lines of the liquid crystal display panel PNL by a TAB process. The shift register may be directly formed on the TFT array substrate of the liquid crystal display panel PNL by a gate in panel (GIP) process. In this case, the level shifter is formed on a control board or a source printed circuit board with a timing controller TCON to supply start pulses and clock signals to a shift register formed of a GIP circuit on a TFT array substrate. .

Programmable Gamma ICs (PGMAs) are symmetrical positive gamma reference voltages (hereinafter referred to as "local positive gamma reference voltages") and negative gamma reference voltages (hereinafter referred to as "local") based on a common voltage optimized for each screen position. Negative gamma reference voltages "). For example, the programmable gamma IC PGMA supplies the first local positive gamma reference voltages and the first local negative gamma reference voltages to the first source drive IC SIC1. The programmable gamma IC PGMA supplies the second local positive gamma reference voltages and the second local negative gamma reference voltages to the second source drive IC SIC2. The programmable gamma IC PGMA supplies the third local positive gamma reference voltages and the third local negative gamma reference voltages to the third source drive IC SIC3. The programmable gamma IC PGMA supplies the fourth local positive gamma reference voltages and the fourth local negative gamma reference voltages to the fourth source drive IC SIC4. The programmable gamma IC PGMA supplies the fifth local positive gamma reference voltages and the fifth local negative gamma reference voltages to the fifth source drive IC SIC5. The programmable gamma IC PGMA supplies the sixth local positive gamma reference voltages and the sixth local negative gamma reference voltages to the sixth source drive IC SIC6. The digital video data is converted into local positive gamma reference voltages and supplied to the data lines as positive data voltages, and converted into local negative gamma reference voltages and supplied to the data lines as negative data voltages. The local positive gamma reference voltages and the local negative gamma reference voltages are symmetrical based on the optimum common voltage for each screen position of the liquid crystal display panel (PNL), thereby optimizing the common voltage across the entire screen of the liquid crystal display panel (PNL). do.

As shown in FIG. 3, there are screen blocks such that the deviation of the optimum common voltages for each position on the screen of the liquid crystal display panel PNL is difficult to visually see a difference in image quality. For example, when the screen of the liquid crystal display panel PNL is divided by the area of responsibility of the source drive ICs SIC1 to SIC6, the second screen block D2 and the sixth screen that the second source drive IC SIC2 is in charge of. The optimum common voltage deviation of the sixth screen block D6 that is in charge of the source drive ICs SIC6 is as small as 0.1V to 0.3V. Since the optimum common voltages of the second and sixth screen blocks D2 and D6 are almost insignificant, the second and sixth locals for optimizing the common voltage Vcom of the second and sixth screen blocks D2 and D6 are small. The positive gamma reference voltages are almost insignificant, and the second and sixth local negative polarity gamma reference voltages are insignificant. Accordingly, the programmable gamma IC (PGMA) may generate second and sixth local positive gamma reference voltages with the same positive gamma reference voltages through the same output channel pins, and the second and sixth local negative gamma reference voltages. Can be generated with the same negative gamma reference voltages through the same output channel pins, thereby reducing the number of output channel pins.

Similarly, since the optimal common voltages of the fourth and fifth screen blocks D4 and D5 have almost no difference, the fourth and fifth portions for optimizing the common voltage Vcom of the fourth and fifth screen blocks D4 and D5 are optimized. 5 The local positive gamma reference voltages are almost no difference, and the fourth and fifth local negative gamma reference voltages are little difference. Thus, the programmable gamma IC (PGMA) may generate fourth and fifth local positive gamma reference voltages with the same positive gamma reference voltages through the same output channel pins, and the fifth and fifth local negative gamma reference voltages. Can be generated with the same negative gamma reference voltages through the same output channel pins, thereby reducing the number of output channel pins.

The timing controller TCON transmits the digital video data of the input image to the source drive ICs SIC1 to SIC6. The timing controller TCON receives timing signals such as a vertical synchronization signal Vsync, a horizontal synchronization signal Hsync, a data enable signal DE, and a main clock CLK input from an external host system. Control signals for controlling the operation timings of the gates SIC1 to SIC6 and the gate driving circuit GIP. The control signals include a gate timing control signal for controlling the operation timing of the gate driving circuit GIP, and a source timing control signal for controlling the operation timing of the source drive ICs SIC1 to SIC6 and the polarity of the data voltage. .

The gate timing control signal includes a gate start pulse (GSP), a gate shift clock (GSC), a gate output enable signal (Gate Output Enable, GOE), and the like. The gate start pulse GSP controls the start operation timing of the gate driving circuit GIP. The gate shift clock GSC is a clock signal for shifting the gate start pulse GSP. The gate output enable signal GOE controls the output timing of the gate driving circuit GIP.

The source timing control signal includes a source start pulse (SSP), a source sampling clock (SSC), a polarity control signal (POL), a source output enable signal (SOE), and the like. The source start pulse SSP controls the data sampling start timing of the data driving circuit. The source sampling clock SSC is a clock signal that controls the sampling timing of data in the source drive ICs SIC1 to SIC6. The polarity control signal POL controls the polarity of the data voltages output from the source drive ICs SIC1 to SIC6. The source output enable signal SOE controls the charge sharing timing and the data output timing. If the digital video data to be input to the source drive ICs SIC1 to SIC6 is transmitted using a mini low voltage differential signaling (LVDS) interface standard, the source start pulse SSP and the source sampling clock SSC may be omitted.

The host system may be an external video source such as a set-top box, a TV system, a phone system, a DVD player, a Blu-ray player, a personal computer (PC). And a video source, such as a home theater system. The host system, including a System on Chip (SoC) with a scaler, converts graphic data from an external video source into a resolution suitable for display on a liquid crystal panel (LVN), thereby providing low voltage differential The signal is transmitted to the timing controller (TCON) through an interface such as a signaling interface or a transition minimized differential signaling (TMDS) interface. In addition, the host system transmits timing signals Vsync, Hsync, DE, and CLK synchronized with the input image to the timing controller TCON through an interface such as an LVDS interface and a TMDS interface.

5 is a diagram illustrating a programmable gamma IC (PGMA). 6 is a plan view showing the appearance of the programmable gamma IC (PGAM) and the output channel pins.

5 and 6, the programmable gamma IC PGMA includes a control interface 50, a non-volatile memory 52, a register 54, and a digital-to-analog converter. Digita to Analog Converter, hereinafter referred to as "DAC" 56, buffers 58, and so forth.

A serial clock SCL and serial data SDA synchronized with the serial clock SCL are input to the programmable gamma IC PGMA. The operator of the LCD module maker inputs serial data (SDA) to the programmable gamma IC (PGMA) to update the gamma data stored in the nonvolatile memory to output voltages of the positive / negative gamma reference voltages output from the programmable gamma IC (PGMA). Can be adjusted. The programmable gamma IC (PGMA) is supplied with a high potential supply voltage (VDD) and a low potential supply voltage (VSS). The low potential power voltage VSS may be a base voltage GND 0V.

The control interface 50 supplies gamma data input to the serial data SDA to the nonvolatile memory 52. The control interface 50 writes gamma data to the nonvolatile memory 52 and reads / writes memory for supplying the gamma data stored in the nonvolatile memory 52 to the register 54. The clock is generated and input to the nonvolatile memory 52 and the register 54.

The nonvolatile memory 52 stores gamma data under the control of the control interface 50. The gamma data are digital data that determine voltages of the positive and negative gamma reference voltages output through the output channel pins of the programmable gamma IC (PGMA).

The register 54 temporarily stores gamma data input from the nonvolatile memory 52 under the control of the control interface 50 and supplies the gamma data to the DACs 56. Gamma data is independently applied to each of the DACs 56. The DACs 56 are then connected 1: 1 to the output channel pin of the programmable gamma IC (PGMA). The DACs 56 output a positive / negative gamma reference voltage V _{GREF that} varies according to gamma data as shown in Equation 2.

Here, VDD denotes a high potential power supply voltage, n denotes a maximum gray value of pixel data, and GMA denotes gamma data.

When the high potential power voltage VDD is 17V and the maximum gray value of the pixel data is 1023, the DAC 56 to which gamma data GMA of '925' is inputted has a local value of (17 × 925) / 1023 = 15.37V. Output as a positive gamma reference voltage.

The buffers 58 are connected between the output terminals of the DACs 56 and the output channel pins of the programmable gamma IC (PGMA) and are output through the output channel pins in consideration of the load variation of the programmable gamma IC (PGMA). Stabilize the polarity / negative gamma reference voltages.

The output channel pins of the programmable gamma IC (PGMA) may be 22 as shown in FIG. 5. According to the present invention, the local positive gamma reference voltages and the local negative gamma reference voltages inputted to six source drive ICs SIC1 to SIC6 using one programmable gamma IC (PGMA) having 22 output channel pins. Occurs.

The programmable gamma IC PGMA outputs first to fourth sets of gamma reference voltages through the first to fourth output channel groups PG1 to PG4. Each of the first to fourth output channel groups PG1 to PG4 includes four output channel pins. The first output channel group PG1 outputs four gamma reference voltages PGMA1_1 to PGAM1_18 to be supplied to the first source drive IC SIC1 through four output channel pins. Gamma reference voltages PGMA1_1 to PGAM1_18 output through the output channel pins of the first output channel group PG1 are illustrated in FIG. 8. The second output channel group PG2 outputs four gamma reference voltages PGMA2_1 to PGAM2_18 and PGMA6_1 to PGAM6_18 to be supplied to the second and sixth source drive ICs SIC2 and SIC6 through four output channel pins. do. The gamma reference voltages PGMA2_1 to PGAM2_18 and PGMA6_1 to PGAM6_18 output through the output channel pins of the second output channel group PG2 are illustrated in FIG. 9. The third output channel group PG3 outputs four gamma reference voltages PGMA4_1 to PGAM4_18 and PGMA5_1 to PGAM5_18 to be supplied to the fourth and fifth source drive ICs SIC4 and SIC5 through four output channel pins. do. The gamma reference voltages PGMA4_1 to PGAM4_18 and PGMA5_1 to PGAM5_18 output through the output channel pins of the third output channel group PG3 are illustrated in FIG. 10. The fourth output channel group PG4 outputs four gamma reference voltages PGMA3_1 to PGAM3_18 to be supplied to the third source drive IC SIC3 through four output channel pins. The gamma reference voltages PGMA3_1 to PGAM3_18 output through the output channel pins of the fourth output channel group PG4 are illustrated in FIG. 11.

7 is a block diagram illustrating an internal circuit configuration of the source drive ICs SIC1 to SIC6.

Referring to FIG. 7, the source drive ICs SIC1 to SIC6 may include a data register 72, a shift register 74, a two line latch 76, a DAC 78, and an output circuit 80. ), Gamma compensation voltage generating circuit 82 and the like.

The data register 72 converts digital video data received from the timing controller TCON into parallel data and supplies it to the two-line latch 76. The shift register 74 sequentially generates the sampling clock by shifting the source start pulse SSP in accordance with the source sampling clock SSC. In FIG. 7, "EIO1" means a carry signal received from a source start pulse SSP or a previous stage source drive IC. "EIO2" means a carry signal of the shift register 74 which is transferred to the source drive IC of the next stage.

The two-line latch 76 samples the digital video data input from the data register 72 based on the sampling clock sequentially input from the shift register 74 and responds to the low logic voltage of the source output enable signal SOE. This outputs latched data simultaneously with two line latches of other source drive ICs.

The DAC 78 converts each of the digital video data input from the two-line latch 78 into positive gamma compensation voltages and negative gamma compensation voltages, and outputs a positive data voltage and a negative data voltage. The DAC 78 includes a PDAC for converting digital video data into a positive data voltage, and an NDAC for converting digital video data into a negative data voltage. The DAC 78 inverts the polarity of the data voltage output through its output channel in response to the polarity control signal POL.

The output circuit 80 performs charge sharing in response to the high logic voltage of the source output enable signal SOE and positive / negative through the output buffer in response to the low logic voltage of the source output enable signal SOE. The polarity data voltage is supplied to the data lines 105. In addition, the output circuit 80 supplies the black gray voltage to the data lines DL in response to the high logic voltage of the source output enable signal SOE.

The gamma compensation voltage generation circuit 82 divides the local positive gamma reference voltages and the local negative gamma reference voltages using a voltage divider circuit input from a programmable gamma IC (PGMA) to correspond to each of the gray levels of the data. Compensation voltages and negative gamma compensation voltages are generated. For example, the gamma compensation voltage generating circuit 82 uses a voltage dividing circuit including resistors connected in series to the first positive gamma reference voltages PGMA1_1, PGMA2_1, PGMA3_1, PGMA4_1, PGMA5_1, and PGMA6_1, which are positive voltages of the highest gray level. ) And the second positive gamma reference voltages PGMA1_9, PGMA2_9, PGMA3_9, PGMA4_9, PGMA5_9, and PGMA6_9, which are the positive polarity voltages of the lowest gray scales, are generated and supplied to the DAC 78. .

The gamma compensation voltage generating circuit 82 uses the voltage divider circuit including the resistors connected in series in FIGS. , PGMA6_18) and the second negative gamma reference voltages PGMA1_10, PGMA2_10, PGMA3_10, PGMA4_10, PGMA5_10, and PGMA6_10, which are the positive voltages of the lowest gray scales, are divided to generate negative gamma compensation voltages therebetween to the DAC (78). Enter it.

FIG. 8 is a diagram illustrating first local positive gamma reference voltages PGMA1_1 and PGMA1_9 and first local negative gamma reference voltages PGMA1_10 and PGMA1_18 input to the first source drive IC SIC1. FIG. 9 illustrates second and sixth local positive gamma reference voltages PGMA2_1, PGMA6_1, PGMA2_9, and PGMA6_9 that are input to the second and sixth source drive ICs SIC2 and SIC6, and second and sixth local parts. The polarity gamma reference voltages PGMA2_10, PGMA6_10, PGMA2_18, and PGMA6_18 are illustrated. FIG. 10 illustrates fourth and fifth local positive gamma reference voltages PGMA4_1, PGMA5_1, PGMA4_9, and PGMA5_9 input to fourth and fifth source drive ICs SIC4 and SIC5, and fourth and fifth local negatives. The polarity gamma reference voltages PGMA4_10, PGMA5_10, PGMA4_18, and PGMA5_18 are shown. FIG. 11 is a diagram illustrating third local positive gamma reference voltages PGMA3_1 and PGMA3_9 and third local negative gamma reference voltages PGMA3_10 and PGMA3_18 input to the third source drive IC SIC3.

8 to 10, the first local positive gamma reference voltages PGMA1_1 and PGMA1_9 may be the first positive gamma reference voltage PGMA1_1, which is the positive voltage of the highest gray level, and the positive voltage of the lowest gray level. The second positive gamma reference voltage PGMA1_9 is included. The first local negative gamma reference voltages PGMA1_10 and PGMA1_18 may include the first negative gamma reference voltage PGMA1_18 which is the negative voltage of the highest gray level, and the second negative gamma reference voltage PGMA1_10 that is the positive voltage of the lowest grayscale. ).

The second and sixth local positive gamma reference voltages PGMA2_1, PGMA2_9, PGMA6_1, and PGMA6_9 are the first positive gamma reference voltages PGMA2_1 and PGMA6_1, which are the positive voltages of the highest gray level, and the positive voltages of the lowest gray level. The second positive gamma reference voltages PGMA2_9 and PGMA2_9 are included. The first positive gamma reference voltages PGMA2_1 and PGMA6_1 are generated with the same voltage, and the second positive gamma reference voltages PGMA2_9 and PGMA6_9 are generated with the same voltage. The second and sixth local negative polarity gamma reference voltages PGMA2_10, PGMA6_10, PGMA2_18, and PGMA6_18 are the first negative polarity gamma reference voltages PGMA2_18 and PGMA6_18 which are the negative voltages of the highest gray level, and the negative voltages of the lowest gray level. The second negative gamma reference voltages PGMA2_10 and PGMA6_10 are included. The first negative gamma reference voltages PGMA2_18 and PGMA6_18 are generated with the same single voltage, and the second negative gamma reference voltages PGMA2_10 and PGMA6_10 are generated with the same single voltage.

The fourth and fifth local positive gamma reference voltages PGMA4_1, PGMA4_9, PGMA5_1, and PGMA5_9 are the first positive gamma reference voltages PGMA4_1 and PGMA5_1, which are the positive voltages of the highest gray level, and the positive voltages of the lowest gray level. The second positive gamma reference voltages PGMA4_9 and PGMA5_9 are included. The first positive gamma reference voltages PGMA4_1 and PGMA5_1 are generated with the same voltage, and the second positive gamma reference voltages PGMA4_9 and PGMA5_9 are generated with the same voltage. The fourth and fifth local negative gamma reference voltages PGMA4_10, PGMA5_10, PGMA4_18, and PGMA5_18 are the first negative polarity gamma reference voltages PGMA4_18 and PGMA5_18, which are negative voltages of the highest gray level, and the negative voltages of the lowest gray level. The second negative gamma reference voltages PGMA4_10 and PGMA5_10 are included. The first negative gamma reference voltages PGMA4_18 and PGMA5_18 are generated with the same voltage, and the second negative gamma reference voltages PGMA4_10 and PGMA5_10 are generated with the same voltage.

The third local positive gamma reference voltages PGMA3_1 and PGMA3_9 may include the first positive gamma reference voltage PGMA3_1, which is the positive voltage of the highest gray level, and the second positive gamma reference voltage PGMA3_9, which is the positive voltage of the lowest gray level. ). The third local negative gamma reference voltages PGMA3_10 and PGMA3_18 may include the first negative gamma reference voltage PGMA3_18 which is the negative voltage of the highest gray level, and the second negative gamma reference voltage PGMA3_10 that is the positive voltage of the lowest grayscale. ).

The local positive gamma reference voltages and the local negative gamma reference voltages for implementing an optimum common voltage on the entire screen of the liquid crystal display panel PNL may be set as follows.

In each of the local positive gamma reference voltages, the first positive gamma reference voltages PGMA1_1 to PGMA6_1 may be set to a voltage between 14.5V and 17.5V. In each of the local positive gamma reference voltages, the second positive gamma reference voltages PGMA1_9 to PGMA6_9 may be set to a voltage between 6V and 9V. In each of the local positive gamma reference voltages, the first negative gamma reference voltages PGMA1_18 to PGMA6_18 may be set to a voltage between 0.2V and 3V. In each of the local positive gamma reference voltages, the second negative gamma reference voltages PGMA1_10 to PGMA6_10 may be set to a voltage between 5V and 8V.

In order to realize an optimum common voltage across the entire screen of the liquid crystal display panel PNL, the relationship between the first positive gamma reference voltages PGMA1_1 to PGMA6_1 of each of the local positive gamma reference voltages is PGMA1_1> PGMA2_1 (= PGMA6_1). > PGMA4_1 (= PGMA5_1)> PGMA3_1 is satisfied.

In order to realize an optimum common voltage across the entire screen of the liquid crystal display panel PNL, the relation between the second positive gamma reference voltages PGMA1_9 to PGMA6_9 of each of the local positive gamma reference voltages is PGMA1_9> PGMA2_9 (= PGMA6_9). > PGMA4_9 (= PGMA5_9)> PGMA3_9 is satisfied.

In order to realize the optimum common voltage across the entire screen of the liquid crystal display panel PNL, the relationship between the first negative polarity gamma reference voltages PGMA1_18 to PGMA6_18 of each of the local positive polarity gamma reference voltages is PGMA1_18> PGMA2_18 (= PGMA6_18). > PGMA4_18 (= PGMA5_18)> PGMA3_18 is satisfied.

In order to realize an optimum common voltage across the entire screen of the liquid crystal display panel PNL, the second negative gamma reference voltages PGMA1_10 to PGMA6_10 of each of the local negative gamma reference voltages are PGMA1_10> PGMA2_10 (= PGMA6_10)> PGMA4_10 (= PGMA5_10)> PGMA3_10 is satisfied.

In the relationship between the gamma reference voltages, the gamma reference voltage is an absolute voltage.

It will be apparent to those skilled in the art that various modifications and variations can be made in the present invention without departing from the spirit or scope of the invention. Therefore, the technical scope of the present invention should not be limited to the contents described in the detailed description of the specification, but should be defined by the claims.

PNL: LCD panel SIC1 ~ SIC6: Source drive IC
GIP: Gate Driver Circuit PGMA: Programmable Gamma IC

Claims

A first local positive gamma reference voltage, a first local negative gamma reference voltage, a second local positive gamma reference voltage, a second local negative gamma reference voltage, a third local positive gamma reference voltage, and a third local negative A programmable gamma IC generating a polar gamma reference voltage;
Converting first digital video data into the first local positive gamma reference voltage to generate a positive data voltage, supplying the positive data voltage to data lines of the first screen block, and supplying the first digital video data to the A first source drive IC converting the first local negative gamma reference voltage to generate a negative data voltage and supplying the negative data voltage to the data lines of the first screen block;
Converting the second digital video data into the second local positive gamma reference voltage to generate a positive data voltage, supplying the positive data voltage to the data lines of the second screen block, and supplying the second digital video data to the A second source drive IC converting the second local negative gamma reference voltage to generate a negative data voltage and supplying the negative data voltage to the data lines of the second screen block; And
Converting third digital video data into the third local positive gamma reference voltage to generate a positive data voltage, supplying the positive data voltage to data lines of a third screen block, and supplying the third digital video data to the A third source drive IC converting into a third local negative gamma reference voltage to generate a negative data voltage and supplying the negative data voltage to the data lines of the third screen block;
Wherein the first local positive gamma reference voltage is higher than the second local positive gamma reference voltage, and the second local positive gamma reference voltage is higher than the third local positive gamma reference voltage. .

The method of claim 1,
The programmable gamma IC is
A fourth local positive gamma reference voltage, a fourth local negative gamma reference voltage, a fifth local positive gamma reference voltage, a fifth local negative gamma reference voltage, a sixth local positive gamma reference voltage, and a sixth local negative And a polarity gamma reference voltage.

The method of claim 2,
Converting fourth digital video data into the fourth local positive gamma reference voltage to generate a positive data voltage, supplying the positive data voltage to data lines of a fourth screen block, and supplying the fourth digital video data to the A fourth source drive IC converting the fourth local negative gamma reference voltage to generate a negative data voltage and supplying the negative data voltage to the data lines of the fourth screen block;
And the fourth local positive gamma reference voltage is lower than the second local positive gamma reference voltage and higher than the third local positive gamma reference voltage.

The method of claim 3, wherein
Converting fifth digital video data into the fifth local positive gamma reference voltage to generate a positive data voltage, supplying the positive data voltage to data lines of the fifth screen block, and supplying the fifth digital video data to the A fifth source drive IC converting the fifth local negative gamma reference voltage to generate a negative data voltage and supplying the negative data voltage to the data lines of the fifth screen block;
And the fifth local positive gamma reference voltage is the same as the fourth local positive gamma reference voltage.

The method of claim 2,
Converting sixth digital video data into the sixth local positive gamma reference voltage to generate a positive data voltage, supplying the positive data voltage to the data lines of the sixth screen block, and supplying the sixth digital video data to the A sixth source drive IC converting the sixth local negative gamma reference voltage to generate a negative data voltage and supplying the negative data voltage to the data lines of the sixth screen block;
And the sixth local positive gamma reference voltage is the same as the second local positive gamma reference voltage.

The method of claim 2,
The absolute value of the first local negative gamma reference voltage is higher than the absolute value of the second local negative gamma reference voltage, and the absolute value of the second local negative gamma reference voltage is greater than the absolute value of the third local negative gamma reference voltage. A liquid crystal display device, characterized in that high.

The method of claim 3, wherein
The absolute value of the fourth local negative gamma reference voltage is lower than the absolute value of the second local negative gamma reference voltage and higher than the absolute value of the third local negative gamma reference voltage.

The method of claim 4, wherein
And the fifth local negative gamma reference voltage is the same as the fourth local negative gamma reference voltage.

The method of claim 5, wherein
And the sixth local negative polarity gamma reference voltage is the same as the second local negative polarity gamma reference voltage.