KR20140090715A

KR20140090715A - Liquid crystal display device and method for driving the same

Info

Publication number: KR20140090715A
Application number: KR1020120151233A
Authority: KR
Inventors: 박종신; 조재형
Original assignee: 엘지디스플레이 주식회사
Priority date: 2012-12-21
Filing date: 2012-12-21
Publication date: 2014-07-18
Also published as: KR102039410B1

Abstract

The present invention relates to a liquid crystal display device and a driving method thereof capable of preventing malfunction due to delay of a gate signal. According to the driving method of a liquid crystal display device according to an embodiment of the present invention, a gate signal, which includes a first gate high voltage for turning on thin film transistors (TFTs) formed in pixels of a liquid crystal panel; a second gate high voltage having a voltage value lower than the first gate high voltage; a first gate low voltage for maintaining a turned-off state of the TFTs; and a second gate low voltage for turning off the TFTs with a voltage value lower than the first gate low voltage, is generated and TFTs formed in the pixels of the liquid crystal panel are switched by using the gate signal.

Description

TECHNICAL FIELD [0001] The present invention relates to a liquid crystal display device and a method of driving the same,

The present invention relates to a display device, and more particularly, to a liquid crystal display device and a driving method thereof that can prevent a malfunction due to delay of a gate signal.

The gate driving circuit of the liquid crystal display device includes a shift register for sequentially supplying gate pulses to a plurality of gate lines. The shift register includes a plurality of stages including a plurality of transistors, and the stages are cascade-connected to sequentially output the gate pulses.

Recently, a GIP (gate in panel) type gate driving circuit in which a transistor constituting a shift register of the gate driving circuit is embedded in a substrate of a display panel in the form of a thin film transistor (TFT) is applied.

1 is a view for explaining a driving method of a conventional liquid crystal display device.

1, a gate signal generated in a gate driving circuit is sequentially output from a first gate signal (1 ^st gate signal) through a last gate signal (last gate signal) through a plurality of stages, Are sequentially supplied from the first gate line formed in the panel to the last gate line. When a gate signal is supplied to the pixel, the TFT of each pixel is turned on.

In recent years, a liquid crystal panel has been enlarged and a narrow bezel has been formed, thereby increasing resistance and parasitic capacitance of lines formed on the liquid crystal panel, resulting in a malfunction due to signal delay.

As the liquid crystal panel becomes larger, the length of the gate line becomes longer, and a delay occurs in the gate signal. As a result of this gate signal delay, the TFT of the pixel can not be driven at the correct timing, which causes a malfunction.

Particularly, the deviation (? Vp1) of the pixel voltage charged in the pixel to which the gate signal is initially applied and the deviation (? Vp2) of the pixel voltage charged in the pixel to which the gate signal is last applied are increased, I can not.

In addition, due to the narrow bezel, the width of the lines outside the active area is reduced, and the rising time and the falling time of the gate signal are increased due to integration of many lines and configurations in a narrow space. As a result, the charging ratio of the pixel voltage is reduced. If the charging ratio of the pixel voltage is decreased, an image according to the source data can not be displayed, and flicker is increased to deteriorate display quality.

SUMMARY OF THE INVENTION The present invention is directed to a liquid crystal display device and a method of driving the same that can prevent a pixel from malfunctioning due to delay of a gate signal.

SUMMARY OF THE INVENTION The present invention has been made to solve the above problems and it is an object of the present invention to provide a liquid crystal display device capable of reducing the rising time and falling time of the gate signal and increasing the charging ratio of the pixel voltage, The present invention also provides a method for providing the above-described method.

SUMMARY OF THE INVENTION The present invention has been made to solve the above-described problems, and it is an object of the present invention to provide a liquid crystal display device which is capable of reducing a deviation (DELTA Vp1) of a pixel voltage charged in a pixel to which a gate signal is initially applied, The present invention also provides a liquid crystal display device and a method of driving the same.

Other features and advantages of the invention will be set forth in the description which follows, or may be obvious to those skilled in the art from the description and the claims.

According to an aspect of the present invention, there is provided a method of driving a liquid crystal display device including a first gate high voltage for turning on a TFT formed on a plurality of pixels of a liquid crystal panel; A second gate high voltage having a voltage value lower than the first gate high voltage; A first gate-low voltage for maintaining the turn-off state of the TFT; And a second gate-low voltage for turning off the TFT with a voltage value lower than the first gate-low voltage, and generating a gate signal by using a gate of the TFT formed on the plurality of pixels of the liquid crystal panel And a second switch.

The liquid crystal display device and the driving method thereof according to the embodiment of the present invention can prevent the pixel from malfunction due to the delay of the gate signal.

The liquid crystal display device and the driving method thereof according to the embodiment of the present invention can reduce the rising time and the falling time of the gate signal and increase the charging ratio of the pixel voltage.

The liquid crystal display device and the driving method thereof according to the embodiment of the present invention may be configured such that the deviation (DELTA Vp1) of the pixel voltage charged in the pixel to which the gate signal is initially applied and the deviation (DELTA Vp2) can be reduced and the display quality can be improved.

In addition, other features and advantages of the present invention may be newly understood through embodiments of the present invention.

1 is a view for explaining a driving method of a liquid crystal display device according to the related art.
2 is a view schematically showing a liquid crystal display device according to an embodiment of the present invention.
3 is a diagram showing a pixel structure of a liquid crystal display device according to an embodiment of the present invention.
FIG. 4 is a view for explaining a driving method of a liquid crystal display device according to an embodiment of the present invention, showing a waveform of a data signal applied to a pixel and a gate signal applied to a gate line; FIG.
FIG. 5 is a diagram showing an effect in which a deviation of a pixel voltage is improved. FIG.
6 is a schematic view of a liquid crystal display device according to another embodiment of the present invention.
7 is a view showing a drive IC of a liquid crystal display device according to another embodiment of the present invention.
8 is a view showing a pixel structure of a liquid crystal display device according to another embodiment of the present invention.

In the drawings, the same reference numerals have been used for the same components, even if they are shown in different drawings.

Meanwhile, the meaning of the terms described in the present specification should be understood as follows. The word " first, "" second," and the like, used to distinguish one element from another, are to be understood to include plural representations unless the context clearly dictates otherwise. The scope of the rights is not limited by these terms.

It should be understood that the terms "comprises" or "having" does not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, or combinations thereof.

It should be understood that the term "at least one" includes all possible combinations from one or more related items. For example, the meaning of "at least one of the first item, the second item and the third item" means not only the first item, the second item or the third item, but also the first item, the second item and the third item Means a combination of all items that can be presented from two or more.

In describing an embodiment of the present invention, when it is described that some structure (electrode, line, wiring, layer, contact) is formed over or on another structure, and below or below, It should be interpreted as including the case where the third structure is interposed between these structures as well as when they are in contact with each other.

The liquid crystal display device has been developed in various ways such as TN (Twisted Nematic) mode, VA (Vertical Alignment) mode, IPS (In Plane Switching) mode and FFS (Fringe Field Switching) mode according to a method of adjusting the arrangement of liquid crystal layers.

Among them, the IPS mode and the FFS mode are a horizontal electric field system in which a pixel electrode (Pixel ITO) and a common electrode (Vcom) are arranged on a lower substrate and the arrangement of liquid crystal layers is adjusted by an electric field between the pixel electrode and the common electrode . The liquid crystal display device according to the embodiment of the present invention can be applied regardless of the mode.

Hereinafter, a liquid crystal display device and a driving method thereof according to an embodiment of the present invention will be described with reference to the accompanying drawings.

The main object of the present invention is to improve the waveform of the gay signal of the liquid crystal display device to prevent malfunction due to signal delay. Therefore, detailed descriptions and drawings of the backlight unit for supplying light to the liquid crystal panel and the mechanisms not related to the main contents of the present invention can be omitted.

FIG. 2 is a view schematically showing a liquid crystal display device according to an embodiment of the present invention, and FIG. 3 is a diagram showing a pixel structure of a liquid crystal display device according to an embodiment of the present invention.

2, a liquid crystal display device according to an embodiment of the present invention includes a liquid crystal panel 100 in which a plurality of pixels are arranged in a matrix form, a driving circuit for driving the liquid crystal panel 100, A backlight unit (not shown) for supplying light to the liquid crystal panel 100, a bezel configured to surround the liquid crystal panel 100 and the driving circuit unit, and an outer case (not shown).

The driving circuit unit includes a gate driving circuit 200, a data driving circuit, a control unit for driving the gate driving circuit 200 and the data driving circuit, and a printed circuit board (PCB) 300 on which a power supply for generating driving power is mounted .

2, the gate driving circuit 200 is formed on the lower substrate of the liquid crystal panel 100 by the GIP method and formed on the left and right sides of the liquid crystal panel 100 as an example. However, the present invention is not limited to this, and the gate driving circuit may be formed as a separate drive IC and disposed on the side surface of the liquid crystal panel 100.

The data driving circuit includes a plurality of data drive ICs 500. The plurality of data drive ICs 500 are formed on a chip on glass (COG) or a chip on flexible printed circuit (COF) And may be disposed on the upper side or the lower side of the liquid crystal panel 100.

Referring to FIG. 3, a plurality of gate lines GL formed in a horizontal direction and a plurality of data lines DL formed in a vertical direction are formed on a lower substrate (TFT array substrate) of the liquid crystal panel 100. The plurality of gate lines and the plurality of data lines intersect to define a plurality of pixels. In FIG. 3, the upper substrate on which the color filter is formed is not shown.

In FIG. 3, the pixels are formed to be short in the horizontal direction and long in the vertical direction, and red, green, and blue pixels are alternately arranged in the horizontal direction.

TFTs are formed as a common electrode to which a common voltage Vcom is applied to each of a plurality of pixels, a pixel electrode to which a data voltage Vdata is applied, a storage capacitor Cst, and a switching element.

Here, the active layer of the TFT may be formed of amorphous silicon (a-Si), low temperature polysilicon (LTPS), or an indium gallium zinc oxide (IGZO) material.

The liquid crystal display device having the above-described configuration changes the alignment state of the liquid crystal in each pixel according to the electric field formed between the pixel electrode and the common electrode, and displays an image by adjusting the transmittance of light supplied from the backlight unit through the arrangement of the liquid crystal do.

Here, as the resistance of the line and the parasitic capacitor are larger, the accuracy of the applied signal is lowered because the signal is delayed by the load of the line.

When the liquid crystal panel 100 is enlarged, the gate line GL becomes long, the load of the gate line increases, and the gate signal may be delayed beyond the normal operation level. Particularly, when the delay of the gate signal supplied to the liquid crystal panel 100 from the gate driving circuit 200 increases, the charging ratio of the pixel voltage decreases, and adjacent pixels may be mixed with each other to generate flicker.

In the present invention, the gate signal is improved as shown in FIG. 4 in order to prevent the delay of the gate signal due to the enlargement of the liquid crystal panel.

FIG. 4 is a diagram illustrating a method of driving a liquid crystal display device according to an embodiment of the present invention, in which waveforms of a gate signal applied to a gate line and a data voltage applied to a pixel are shown.

4, the gate signal supplied to the pixel of the liquid crystal display device according to the embodiment of the present invention includes a first gate high voltage VGH1, a second gate high voltage VGH2 lower than the first gate high voltage ), A first gate low voltage (VGL1) of negative polarity, and a second gate low voltage (VGL2) lower than the first gate low voltage.

Specifically, the gate signal rises in the first period to the first gate low voltage (VGL1) of negative polarity, for example, -5V to the first gate high voltage (VGH1), for example, + 35V. At this time, the first gate high voltage VGH1 is generated with a voltage value (Vgh1> Vgh_ref) higher than the existing gate high voltage VGH, for example, +28 V, thereby reducing the rising time of the gate signal, - Ensure that the on-speed is achieved.

Then, in the second period, the first gate high voltage VGH1 is maintained. At this time, although the time during which the first gate high voltage VGH1 is held may be shorter than the gate high voltage VGH of the related art, the first gate high voltage VGH1 of the present invention is lower than the gate high voltage VGH of the prior art, Has a high voltage value, it is possible to reduce the charging time of the pixel voltage.

Specifically, the first gate high voltage VGH1 allows a large amount of current to flow compared with the conventional technique, so that the pixel voltage can be sufficiently charged even in a short time. That is, the charging ratio of the pixel can be increased. On the other hand, if the charging ratio is set at a level equivalent to that of the prior art, the charging time at which the pixel voltage is charged can be reduced.

Then, in the third period, a gate pulse modulation (GPM) is applied to apply a voltage of the gate signal to the second gate high voltage VGH2, for example, +20 V, which is lower than the first gate high voltage Lower.

At this time, the second gate high voltage VGH2 has a voltage value higher than the turn-on voltage value of the gate of the TFT formed in the pixel of the liquid crystal panel. Lowering the first gate high voltage VGH1 to the second gate high voltage VGH2 by applying a gate pulse modulation (GPM) is to reduce the polling time of the gate signal.

Specifically, the charging time of the pixel voltage is shortened by the first gate high voltage VGH1, and an extra charging time can be ensured. During this extra charging time, gate pulse modulation (GPM) is applied to lower the peak voltage of the gate signal from the first gate high voltage VGH1 to any second gate high voltage VGH2 (Vgh2 <Vgh1).

Here, before the TFT turns off the pixel, the voltage value of the gate signal can be lowered to the second gate high voltage VGH2 of the low voltage value in advance to reduce the polling time of the gate signal.

Here, the lower the second gate high voltage VGH2 can reduce the polling time of the gate signal, but at least the second gate high voltage VGH2 is higher than the maximum value V_data of the data voltage applied to the data line (Vgh2 > V_data).

If the second gate high voltage VGH2 has a voltage value equal to or lower than the pixel voltage V_data, a reverse current flows in the pixel, so that the charging of the pixel voltage may become insufficient. To prevent this, the second gate high voltage VGH2 has a voltage value (Vgh2> V_data) higher than the maximum value (V_data) of the data voltage applied to the data line.

Subsequently, in the fourth period, the voltage of the gate signal is lowered to the second gate low voltage VGL2 having a voltage value lower than the first gate low voltage VGL1 which is a voltage value initially, for example, -15V.

That is, under driving driving is applied to lower the voltage of the gate signal to the second gate-low voltage VGL2 of -15V, which has a voltage value lower than -5V, as an example of a gate-low voltage (VGL) .

Here, in order to turn off the TFT of the pixel, the voltage value of the gate signal is lowered from the high voltage to the low voltage. In a short time, the voltage of the gate signal is lowered to the second gate low voltage VGL2 of- To reduce the polling time of the gate signal.

That is, the TFT of the pixel is turned off with the second gate-low voltage VGL2 having a voltage value lower than that of the conventional one, thereby enhancing the polling characteristic of the gate.

Thereafter, the voltage of the gate signal is raised to the first gate low voltage (VGL1) again to the second gate low voltage (VGL2) so that the TFT of the pixel stably maintains the OFF state.

Fig. 5 is a diagram showing an effect in which the deviation of the pixel voltage is improved.

Referring to Table 1 and FIG. 5, the charging ratio of the pixel voltage of the prior art and the present invention is 97.0 to 97.4%, which is the same level. When the charging ratio of the pixel voltage is the same, the polling time of the gate signal is 4.64 us, whereas the present invention has the effect of reducing the polling time of the gate signal by 54% with respect to the prior art.

As described above, the two gate high voltages VGH1 and VGH2 and the two gate low voltages VGL1 and VGL2 are used, that is, four voltages VGL1, VGL2, VGH1 and VGH2 ), It is possible to prevent the charge ratio of the pixel voltage from decreasing due to the delay of the gate signal generated due to the enlargement of the liquid crystal panel. In addition, it is possible to prevent the flicker from being generated due to the overlap of the data of adjacent pixels due to the delay of the gate signal.

Meanwhile, as shown in FIG. 2, by applying the gate driving circuit 200 of the GIP scheme, it is possible to reduce the manufacturing cost of the liquid crystal display device and to reduce the volume and weight. However, bezel) increases in size.

Since the GIP lines can not be deleted, it is difficult to implement an ideal narrow bezel, and furthermore, there is a problem that it is impossible to implement a borderless panel. In order to solve this problem, as shown in Figs. 6 and 7, the arrangement position of the drive IC in the liquid crystal display device is changed, and the pixel structure is changed as shown in Fig.

FIG. 6 is a schematic view of a liquid crystal display device according to another embodiment of the present invention, and FIG. 7 is a view illustrating a drive IC of a liquid crystal display device according to another embodiment of the present invention.

6 and 7, a liquid crystal display device according to another embodiment of the present invention includes a liquid crystal panel 100 in which a plurality of pixels are arranged in a matrix form, a plurality A printed circuit board (PCB) 300 on which a power supply for generating a driving power is mounted, a liquid crystal panel 100, and a driving IC 400 for driving the plurality of drive ICs 400, A backlight unit (not shown) for supplying light, a bezel configured to surround the liquid crystal panel 100 and the driving circuit, and an outer case (not shown).

Fig. 7 shows one drive IC 400 among the plurality of drive ICs 400. Fig. The plurality of drive ICs 400 may be formed by COG (Chip On Glass) or COF (Chip On Flexible Printed Circuit) method.

Referring to FIG. 7A, a drive IC 400 of a liquid crystal display device according to an embodiment of the present invention is formed by merging gate driver logic and data driver logic into one chip (one chip) .

Referring to FIG. 7B, the drive IC 400 of the liquid crystal display device according to the embodiment of the present invention includes a data drive IC 420 and a gate drive IC 430 integrated into a single chip.

The data drive logic or data drive IC 420 generates an analog data voltage to be supplied to the pixels using the data control signal and digital image data applied from the control unit mounted on the printed circuit board 300.

The gate drive logic or the gate drive IC 430 generates a gate signal (scan signal) for switching TFTs formed in the pixels by using a gate control signal applied from a control unit mounted on the printed circuit board 300 .

On both sides of the drive IC 400, a plurality of link lines 410 are formed. Here, the plurality of link lines 410 includes a plurality of gate link lines 412 and a plurality of data link lines 414.

The drive IC 400 receives a gate signal from a control unit through a plurality of gate link lines 412 and supplies the generated gate signal to the pixels formed on the liquid crystal panel.

The drive IC 400 receives a data control signal and digital image data from a control unit through a plurality of data link lines 414 and outputs analog data voltages generated according to the digital image data to pixels formed in the liquid crystal panel Supply.

Since the data line DL formed in the liquid crystal panel 100 and the plurality of first gate lines VGL and vertical gate lines are not the same number, the gate line line 412 and the plurality of data line lines 414 They are not formed alternately in the same number. May be formed in units of one gate link line 412 and two data link lines 414 depending on the pitch and resolution of the pixel.

Hereinafter, the structure of the liquid crystal panel 100 of the present invention will be described in detail with reference to FIG. 8 is a diagram showing a pixel structure of a liquid crystal display device according to another embodiment of the present invention.

8, a lower substrate (TFT array substrate) of a liquid crystal panel is provided with a plurality of first gate lines (VGL, vertical gate lines), a plurality of second gate lines (HGL, horizontal gate lines) DL) are formed.

A plurality of pixels are defined by a plurality of first gate lines (VGL), a plurality of second gate lines (HGL), and a plurality of data lines (DL). (Not shown) to which a common voltage Vcom is applied to a plurality of pixels, a pixel electrode (not shown) to which a data voltage Vdata is applied, a storage capacitor Cst (not shown), and a switching element, Respectively.

6 and 7, a drive IC 400, in which a gate drive IC (or gate drive logic) and a data drive IC (or data drive logic) are integrated into one chip, 100, respectively. Accordingly, in the present invention, a structure of a new gate line is applied in order to supply a gate signal to the pixels of the liquid crystal panel 100. 6 shows that the drive IC 400 is disposed on the upper side of the liquid crystal panel 100. However, the present invention is not limited to this and the drive IC 400 may be disposed on the lower side of the liquid crystal panel 100 as well.

As shown in FIG. 8, a plurality of first gate lines VGL and a plurality of data lines DL are formed in parallel in the liquid crystal panel 100 in the vertical direction. In other words, a plurality of first gate lines VGL are formed in the same direction as the plurality of data lines DL.

The plurality of second gate lines HGL are formed to cross the plurality of first gate lines VGL and the plurality of data lines DL. That is, the plurality of gate lines HGL are formed in the horizontal direction.

In other words, the plurality of first gate lines VGL and the plurality of data lines extend from the upper side to the lower side in the vertical direction so as to cross the short axis direction of the liquid crystal panel 100. [

The plurality of second gate lines HGL are formed in a horizontal direction from left to right (or from the right to the left) so as to cross the longitudinal axis direction of the liquid crystal panel 100.

Here, a plurality of first gate lines (VGL) formed in the vertical direction and a plurality of second gate lines (HGL) formed in the horizontal direction are formed so as to correspond one to one in the same number.

A plurality of second gate lines HGL formed in the horizontal direction are formed in the first layer and a plurality of first gate lines VGL and a plurality of data lines DL formed in the vertical direction are formed in the second layer .

A plurality of first gate lines VGL and a plurality of second gate lines HGL formed in the vertical direction are formed on different layers with an insulating layer interposed therebetween, Are selectively contacted through the contact CNT in the region where the second gate lines HGL of the first gate lines HGL overlap each other. That is, the plurality of first gate lines (VGL) and the plurality of second gate lines (HGL) are electrically connected through contacts (CNT) in pairs in a line overlapping each other.

Specifically, the first gate line VGL1 formed in the vertical direction and the first gate line HGL1 formed in the horizontal direction are electrically connected to each other through the first contact CNT1 in the overlapping area. Thus, a pair of vertical gate lines and horizontal gate lines, that is, the first vertical gate line VGL1 and the first horizontal gate line HGL1 are electrically connected through the first contact CNT1.

The second first gate line VGL2 formed in the vertical direction and the second gate line HGL2 formed in the horizontal direction are electrically connected to each other through the second contact CNT2 in the overlapping area. Thus, a pair of vertical gate lines and horizontal gate lines, that is, a second vertical gate line VGL2 and a second horizontal gate line HGL2 are electrically connected through the second contact CNT2.

The third first gate line VGL3 formed in the vertical direction and the third gate line HGL3 formed in the horizontal direction are electrically connected to each other through the third contact CNT2 in the overlapping area. In this way, a pair of vertical gate lines and horizontal gate lines, that is, the third vertical gate line VGL3 and the third horizontal gate line HGL3 are electrically connected through the third contact CNT3.

With the same structure as that described above, each of the n first gate lines (VGL) and the n second gate lines (HGL) is electrically connected through the contacts in pairs.

The first, second, and third expressions described in the foregoing description are for describing the order and relationship among a plurality of lines, and do not indicate that the first expression is the first among the entire lines, To explain the present invention. Hereinafter, the meanings of the first, second and third expressions are also applied in the description of the present invention.

A plurality of first gate lines VGL formed in the vertical direction are respectively connected to the plurality of gate link lines 412 shown in FIG. Thus, the gate signal output from the drive IC 400 is applied to the plurality of first gate lines VGL.

The gate signal is supplied to the TFTs of the plurality of pixels formed in the liquid crystal panel 100 via the plurality of second gate lines HGL connected to the plurality of first gate lines VGL so that the TFTs are turned on turn-on. At this time, the gate signal is supplied to all the pixels of the liquid crystal panel, and is sequentially supplied in units of one horizontal line.

On the other hand, the plurality of data lines DL formed in the vertical direction are connected to the plurality of data link lines 414 shown in Fig. 7, respectively. Thus, the data voltage Vdata output from the drive IC 400 is applied to the plurality of data lines DL.

The data voltage Vdata is supplied to the source electrode of the TFT formed on the liquid crystal panel 100 via the data line DL and the data voltage Vdata supplied to the source electrode is supplied to the drain electrode And is supplied to the pixel electrode via the pixel electrode.

A liquid crystal display device according to an embodiment of the present invention applies a scan signal to a pixel through a first gate line formed in a vertical direction and applies a data voltage Vdata to a pixel through a data line formed in a vertical direction, The link lines and the GIP logic formed in the non-display areas on the left and right sides of the liquid crystal panel in the prior art can be eliminated.

Accordingly, only the common voltage link region and the ground link region are formed in the left and right non-display regions of the liquid crystal panel 100, thereby reducing the bezel width to 1.0 mm to 1.6 mm.

6 to 8, in order to reduce the size of the left and right bezels of the liquid crystal panel 100, when the vertical gate lines are additionally formed, the total length of the gate lines becomes longer than before, The delay can be intensified.

4 and 5, a liquid crystal display device according to an embodiment of the present invention includes a first gate high voltage (VGH1), a second gate high voltage A first gate low voltage VGL1 of negative polarity and a second gate low voltage VGL2 lower than the first gate low voltage, Can be improved.

As described above, the gate signal is generated using the two gate high voltages VGH1 and VGH2 and the two gate low voltages VGL1 and VGL2, that is, a total of four voltages VGL1, VGL2, VGH1, and VGH2 It is possible to prevent the charge ratio of the pixel voltage from decreasing due to the delay of the gate signal generated due to the enlargement of the liquid crystal panel. In addition, it is possible to prevent the flicker from being generated due to the overlap of the data of adjacent pixels due to the delay of the gate signal.

Referring to Table 1 and FIG. 5, when the gate signal of the prior art is applied to the pixel structure in which the vertical gate lines are further formed as shown in FIG. 8, The deviation (DELTA Vp1) of the pixel voltage charged in the ON pixels is 0.539V, and the deviation (DELTA Vp2) of the pixel voltage charged in the pixels turned on by the gate signal supplied to the last gate line becomes 0.422V. Therefore, the deviation (? Vp1 -? Vp2) of? Vp2 in? Vp1, that is, the deviation of the pixel voltage charged in all the pixels becomes 0.117V.

On the other hand, as shown in FIG. 8, when the gate signal of the present invention shown in FIG. 4 is applied to the pixel structure in which the vertical gate line is further formed, the pixels turned on by the gate signal supplied to the first gate line The deviation (DELTA Vp1) of the pixel voltage charged in the gate line is 0.390 V and the deviation (DELTA Vp2) of the pixel voltage charged in the pixels turned on by the gate signal supplied to the last gate line becomes 0.397V. Therefore, a deviation of ΔVp2 (ΔVp1 - ΔVp2) from ΔVp, that is, a deviation of the pixel voltage charged in all the pixels becomes 0.011V.

In this way, by applying the vertical gate lines to reduce the size of the left and right bezels of the liquid crystal panel, the design aesthetics of the liquid crystal display device can be enhanced, and the gate signal of the present invention shown in FIG. The occurrence of problems due to delay can be prevented.

It will be understood by those skilled in the art that the present invention can be embodied in other specific forms without departing from the spirit or essential characteristics thereof. It is therefore to be understood that the above-described embodiments are illustrative in all aspects and not restrictive.

The scope of the present invention is defined by the appended claims rather than the detailed description and all changes or modifications derived from the meaning and scope of the claims and their equivalents are to be construed as being included within the scope of the present invention do.

100: liquid crystal panel 200: gate driving circuit
300: printed circuit board 400: drive IC
500: Data drive IC VGH1: First gate high voltage
VGH2: second gate high voltage VGL1: first gate low voltage
VGL2: second gate low voltage

Claims

A first gate high voltage for turning on a TFT formed on a plurality of pixels of the liquid crystal panel;
A second gate high voltage having a voltage value lower than the first gate high voltage;
A first gate-low voltage for maintaining the turn-off state of the TFT; And
And a second gate-low voltage for turning off the TFT with a voltage value lower than the first gate-low voltage,
And switching the TFTs formed in the plurality of pixels of the liquid crystal panel by using the gate signal.

The method according to claim 1,
Wherein the gate signal comprises:
The first gate low voltage of the negative polarity is raised to the first gate high voltage in the first period for turning on the TFT.

The method according to claim 1,
Wherein the gate signal comprises:
And maintaining the first gate high voltage in a second period for maintaining the turn-on of the TFT.

The method according to claim 1,
Wherein the gate signal comprises:
Wherein a gate pulse modulation is applied to a third period for reducing a polling time of the signal to be lowered from the first gate high voltage to the second gate high voltage.

The method according to claim 1,
Wherein the gate signal comprises:
And the second gate-low voltage is lower than the first gate-low voltage in a fourth period for turning off the TFT.

6. The method of claim 5,
By applying under driving,
And lowers the voltage value of the gate signal from the second gate high voltage to the second gate low voltage.

6. The method of claim 5,
Wherein the gate signal comprises:
And rising from the second gate low voltage to the first gate low voltage after the fourth period to maintain the off state of the TFT.

The method according to claim 1,
Wherein the first gate high voltage is +35 V, the second gate high voltage is +20 V, the first gate low voltage is -5 V, and the second gate low voltage is -15 V. A method of driving a liquid crystal display device,

The method according to claim 1,
And the second gate high voltage is a voltage value higher than a maximum value of the data voltage.