KR20040013605A - Liquid crystal display and method for driving thereof - Google Patents

Abstract

PURPOSE: A liquid crystal display and a method for driving the same are provided to prevent flickering by minimizing a difference in a kick-back voltage between frames having inverse polarities. CONSTITUTION: A liquid crystal display panel(100) displays images. A timing controller(200) outputs an image signal, first and second timing signals in response to an external signal. A data driver(300) outputs data signals to a plurality of data lines(D1-Dm) in response to the image signal and the first timing signal. A gate driver(400) outputs gate signals to a plurality of gate lines(G1-Gn) in response to the second timing signal. The gate driver outputs a first gate signal or a second signal having a first voltage and a second voltage for compensating a kick-back voltage for a first period activating the gate lines, and having a third voltage lower than the first voltage and the second voltage, and a fourth voltage lower than the third voltage for a second period non-activating the gate lines.

Description

Liquid crystal display and driving method thereof {LIQUID CRYSTAL DISPLAY AND METHOD FOR DRIVING THEREOF}

The present invention relates to a liquid crystal display device and a driving method thereof, and more particularly, to a liquid crystal display device and a driving method thereof for improving display characteristics.

Recently, an information processing device requires a display device that serves as an interface so that a user may visually check the information processed by the information processing device.

A liquid crystal display is a typical display device. A liquid crystal display is a display device that uses a modulation of light by liquid crystal by applying a voltage to a specific molecular array of liquid crystal to convert it into another molecular array and converting a change in optical properties into a visual change. to be.

Generally, a liquid crystal display device includes a liquid crystal display panel implementing a screen, a driver for driving the liquid crystal display panel, and a light supply unit for providing light to the liquid crystal display panel. In this case, the liquid crystal display panel includes a liquid crystal layer formed between the upper substrate, the lower substrate, and the upper substrate and the lower substrate.

The lower substrate includes a plurality of gate lines transmitting scan signals and data lines crossing the gate lines and transferring image data, and formed in an area surrounded by the gate lines and the data lines, respectively. It includes a pixel in the form of a matrix connected through a thin film transistor (TFT), which is one of lines and switching elements.

In this case, the TFT is connected to the pixel electrode, and is turned on or turned off according to the gate signal applied through the gate line so that a data signal having image information is applied to the pixel electrode. To control. That is, when the gate signal is applied to the TFT, the TFT is turned on and the data signal voltage applied to the pixel electrode is charged. Thereafter, even after the application of the gate signal is terminated and the TFT is turned off, the data signal voltage charged in the pixel electrode is maintained.

However, the parasitic capacitance (Cgd) generated between the gate electrode and the drain electrode of the TFT causes distortion of the data signal applied to the pixel electrode. At this time, the distorted voltage is called a kickback voltage (Vk).

Meanwhile, a method of applying image data to each pixel in such a liquid crystal display device is as follows.

First, a gate signal, which is a scan signal, is sequentially applied to gate lines to sequentially turn on a TFT connected to the gate line, and at the same time, a data signal including an image signal to be applied to a pixel row corresponding to the gate line. Supply to each data line. Then, the image signal supplied to the data line is applied to each pixel through the turned-on TFT. At this time, the gate signal is sequentially applied to all the gate lines for one frame period to apply the pixel signal to all the pixel rows, thereby displaying an image of one frame.

In general, when the electric field in the same direction is continuously applied due to the characteristics of the liquid crystal material, there is a problem in that the liquid crystal material is deteriorated. That is, if the polarity of the applied voltage of one pixel receives the positive signal voltage, the next frame must receive the negative signal voltage.

For this reason, a frame inversion method (FIM) for inverting polarity on a frame-by-frame basis for inverting the liquid crystal display device, and a line inversion method (LIM) for inverting the polarity of adjacent lines for each frame. The column inversion method (CIM) for inverting the polarity of the adjacent column for each frame, and the dot inversion method (DIM) for inverting the polarity of the adjacent dot for each frame are adopted.

Here, the line inversion driving method will be described as an example. In this case, the voltage Vlc applied to the liquid crystal layer is lowered by the kickback voltage Vk in the frame driven in the positive polarity (hereinafter, positive frame), and the frame driven in the negative polarity (hereinafter, negative). The voltage Vlc applied to the liquid crystal layer is increased by the kickback voltage Vk.

However, when the liquid crystal display panel is driven by the line inversion method, the first variation width ΔV1 = Vgh1-Vgl1 of the first gate signal Vg applied to the TFT during the positive frame is the second applied to the TFT during the negative frame. The second variation range ΔV2 = Vgh2-Vgl2 of the gate signal Vg2 is different. This occurs because the first and second gate signals Vg1 and Vg2 swing from the high level to the low level and then swing in the same manner as the common voltage. This difference between the first and second variation ranges ΔV1 and ΔV2 causes a difference between the first kickback voltage Vk1 in the positive frame and the second kickback voltage Vk2 in the negative frame.

As such, when a difference in kickback voltage occurs in each frame, a flicker phenomenon occurs on the screen of the liquid crystal display, thereby deteriorating display characteristics of the liquid crystal display.

SUMMARY OF THE INVENTION An object of the present invention is to provide a liquid crystal display for improving display characteristics by minimizing a difference in kickback voltage for each frame having an inverted polarity.

In addition, another object of the present invention is to provide a method of driving a liquid crystal display device for improving display characteristics by minimizing a difference in kickback voltage for each frame having inverted polarity.

1 is a block diagram illustrating a liquid crystal display according to an exemplary embodiment of the present invention.

2A and 2B are diagrams illustrating a line inversion driving method of the liquid crystal display panel illustrated in FIG. 1.

3 is a cross-sectional view illustrating in detail a structure of the liquid crystal display panel illustrated in FIG. 1.

4 is a diagram illustrating a structure of a lower substrate illustrated in FIG. 3.

FIG. 5 is a circuit diagram illustrating an equivalent circuit of the liquid crystal display panel illustrated in FIG. 1.

6A is a waveform diagram illustrating a gate signal waveform applied to the first frame illustrated in FIG. 2A.

FIG. 6B is a waveform diagram illustrating a gate signal waveform applied to the second frame illustrated in FIG. 2B.

7A is a waveform diagram illustrating a gate signal waveform applied to a first frame according to another embodiment of the present invention.

7B is a waveform diagram illustrating a gate signal waveform applied to a second frame according to another embodiment of the present invention.

<Explanation of symbols for the main parts of the drawings>

100 liquid crystal display panel 122 TFT

123: pixel electrode 124a: gate line

125a: data line 200: timing controller

300: data driver 400: gate driver

500: liquid crystal display

According to an aspect of the present invention, there is provided a liquid crystal display device comprising: a timing controller configured to output an image signal and first and second timing signals for controlling output of the image signal in response to a signal from an external device; A data driver configured to receive the image signal and the first timing signal and output a data signal; In response to the second timing signal, a first gate signal is output in a first frame corresponding to a first polarity, and a first gate signal is output in a second frame corresponding to a second polarity inverted from the first polarity. A gate driver for outputting a different second gate signal; And a plurality of data lines for transmitting the data signal, a plurality of gate lines for transmitting the first or second gate signal, a first end and a second end are connected to the data line and the gate line, and It includes a liquid crystal display panel for displaying an image including a switching element for outputting the data signal in response to a second gate signal.

In this case, the gate driver has a first voltage and a second voltage for kickback compensation during a first period of activating the gate line, and a lower voltage than the first and second voltages during a second period of inactivating the gate line. A first or second gate signal that repeats three voltages and a fourth voltage lower than the third voltage is output.

In addition, the driving method of the liquid crystal display according to the present invention for achieving another object of the present invention described above, a plurality of data lines, a plurality of gate lines, the first end and the second end of the data line and the gate line (A) First and second timing signals for controlling the output of the image signal and the image signal in response to a signal from the outside for driving a liquid crystal display device for displaying an image through the liquid crystal layer, the switching element being connected to each other. Generating a; (b) receiving the image signal and the first timing signal and outputting a data signal to the data line; And (c) outputting a first gate signal in a first frame corresponding to a first polarity in response to the second timing signal, and a second gate in a second frame corresponding to a second polarity opposite to the first polarity. Outputting a signal, and converting one of the first and second gate signals into a signal for kickback compensation in a period for activating the gate line and providing the signal to the gate line.

According to such a liquid crystal display and a driving method thereof, the gate driver of the liquid crystal display converts a signal for kickback compensation during a first period of selecting one of a first gate signal and a second gate signal to activate a gate line. Provides a gate line. Therefore, it is possible to minimize the difference in kickback voltage between frames having polarities inverted from each other, and further improve the display characteristics of the liquid crystal display.

Hereinafter, with reference to the accompanying drawings, it will be described in detail an embodiment of the present invention.

1 is a block diagram illustrating a configuration of a liquid crystal display according to an exemplary embodiment of the present invention. FIG. 2A illustrates a first frame of the liquid crystal display panel illustrated in FIG. 1, and FIG. 2B illustrates a second frame of the liquid crystal display panel illustrated in FIG. 1.

Referring to FIG. 1, the liquid crystal display 500 according to an exemplary embodiment of the present invention includes a liquid crystal display panel 100 displaying an image, an image signal, and first and second timing signals in response to a signal from an external source. A timing controller 200 for controlling the driving of the liquid crystal display panel 100 by outputting the control panel, and a data driver 300 for outputting data signals to the plurality of data lines D1 to Dm in response to the image signal and the first timing signal. ) And a gate driver 400 outputting gate signals to the plurality of gate lines G1 to Gn in response to the second timing signal.

That is, the timing controller 200 generates the image signal and the first and second timing signals in response to a signal provided from the outside, for example, the image signal and the synchronization signal.

Here, the first timing signal includes a horizontal clock signal HCLK for data shift in the data driver 300, data is converted into an analog in the data driver 300, and the converted analog value is converted into a liquid crystal display panel. A signal is defined including a horizontal synchronization start signal STH for instructing 100 to be applied and a load signal LOAD or TP for instructing the loading of data signals to the data driver 300.

The second timing signal may include a gate clock signal for setting a period of the gate-on signal applied to the gate line, a vertical synchronization start signal STV for commanding the start of the gate-on signal, and the gate driver. This signal is defined to include an output enable signal (OE; Out Enable) for enabling the output of 400.

In this case, the data driver 300 generates a data signal applied to each pixel of the liquid crystal display panel 100 in response to the image signal and the first timing signal. Here, the data signal is a charging voltage for charging each pixel.

The gate driver 400 controls the application of the data signal to each pixel by sequentially applying a gate signal having a high level interval to the gate lines G1 to Gn in response to the second timing signal. That is, the gate signal has a voltage level sufficient to drive the TFT connected to the gate line. Therefore, when the TFT is driven by the gate signal, the data signal is applied to the pixel electrode through the TFT to charge the liquid crystal layer.

Here, the gate signal includes a first gate signal output in a first frame corresponding to the first polarity and a second gate signal output in a second frame corresponding to a second polarity opposite to the first polarity. In this case, the gate driver 400 further includes a kickback voltage driving circuit 410 to compensate for a difference in kickback voltage generated between the first and second frames having polarities inverted from each other.

The liquid crystal display 500 according to the exemplary embodiment of the present invention drives the liquid crystal display panel 100 using the line inversion driving method. 2A and 2B, the liquid crystal display panel 100 is inverted in the row direction.

As shown in FIGS. 2A and 2B, odd pixels in the first frame are driven at a first polarity, that is, positive polarity, and even pixels are driven at a second polarity, that is, negative polarity (−). . In contrast, in the second frame having the polarity reversed from the first frame, the odd pixels are driven in the negative polarity (−), and the even pixels are driven in the positive polarity (+).

That is, when the pixels are driven positively (+) during the first frame, they are driven negatively (-) in the second frame, and when they are driven negatively (-) during the first frame, the positive polarity ( Driven by +). As described above, deterioration of the liquid crystal (not shown) formed in the liquid crystal display panel 100 may be prevented by alternately applying positive polarity (+) and negative polarity (−) to each pixel.

2A and 2B illustrate a structure in which polarity is inverted in units of one gate line, but this structure is an embodiment of the present invention, and the polarity is inverted in units of two, three, or more gate lines. Can be. Also, although the polarity is reversed in one frame unit, the polarity may be reversed in two frame or three frame units.

Here, it is assumed that the gate driver 400 outputs the first gate signal to drive the odd-numbered gate line of the first frame and outputs the second gate signal to drive the odd-numbered gate line of the second frame.

The gate driver 400 has a first voltage and a second voltage for kickback compensation during a first period for activating the gate line by the kickback voltage compensation circuit 410, and during the second period for deactivating the gate line. A first or second gate signal that repeats a third voltage lower than the first and second voltages and a fourth voltage lower than the third voltage is output. Therefore, the difference between the kickback voltages in the first and second frames having polarities inverted from each other can be minimized to prevent flicker.

This kickback compensation method will be described in detail with reference to the accompanying drawings.

3 is a cross-sectional view illustrating in detail a liquid crystal display panel shown in FIG. 1, and FIG. 4 is a view showing a lower substrate of the liquid crystal display panel illustrated in FIG. 3.

Referring to FIG. 3, the liquid crystal display panel 100 includes an upper substrate 110, a lower substrate 120, and a liquid crystal layer 130 formed between the upper substrate 110 and the lower substrate 120. .

The upper substrate 110 includes a common electrode 112 formed on the first substrate 111 and made of a transparent and conductive material such as indium tin oxide (ITO).

The lower substrate 120 includes a TFT 122 formed in a matrix form on the second substrate 121 and a pixel electrode 123 coupled to the TFT 122. The gate electrode 122a of the TFT 122 is coupled with the q-th gate line Gq extending in the row direction, and the source electrode 122b is coupled with the p-th data line Dp extending in the column direction. Here, q is any one of natural numbers from 1 to n, and p is any one of natural numbers from 1 to m-1. In addition, the drain electrode 122c is connected to the pixel electrode 123.

The liquid crystal display 500 further includes an auxiliary capacitor Cst connected in parallel with the liquid crystal capacitor Clc to increase the voltage retention of the liquid crystal layer 130 and reduce the kickback voltage Vp. In detail, the storage capacitor Cst is formed by partially overlapping the q-1 th gate line Gq-1 and the pixel electrode 123 connected to the q th gate line Gq.

The upper substrate 110 and the lower substrate 120 are coupled so that the common electrode 112 and the pixel electrode 123 face each other, and the liquid crystal layer 130 is disposed between the upper substrate 110 and the lower substrate 120. Is formed.

Thereafter, when the TFT 122 is driven, a predetermined voltage is applied to the pixel electrode 123, so that an electric field is formed between the pixel electrode 123 and the common electrode 112. Thereby, the image is displayed by changing the array angle of the liquid crystal interposed therebetween, and controlling the transmittance of light.

FIG. 5 is a circuit diagram illustrating an equivalent circuit of the liquid crystal display panel illustrated in FIG. 1.

Referring to FIG. 5, by the q-1 th gate line Gq-1, the q th gate line Gq, the p th data line Dp, and the p + 1 th data line Dp + 1 An equivalent circuit to the formed pixel region is presented. Specifically, in the pixel area, the TFT 122 connected to the q-th gate line Gq and the p-th data line Dp, the liquid crystal capacitor Clc connected in parallel with the TFT 122, and the storage capacitor Cst Is done.

If the filling rate of the liquid crystal layer is 100%, the voltage applied to the liquid crystal layer immediately before the TFT 122 is turned off is the voltage applied to the p-th data line Dp. At this time, when the TFT 122 is turned off, the gate signal varies from the on voltage Vgh to the off voltage Vhl. When the gate signal variation range is 'Vgh-Vgl', the voltage across the liquid crystal layer is TFT. The parasitic capacitance Cgs, the liquid crystal capacitor Clc, and the auxiliary capacitor Cst between the gate electrode 121a and the drain electrode 121c of 122 are shifted by 'Vk'. At this time, 'Vk' is called the kickback voltage.

Therefore, the kickback voltage Vk satisfies the following equation (1).

FIG. 6A is a waveform diagram specifically illustrating a gate signal waveform in the first frame illustrated in FIG. 2A, and FIG. 6B is a waveform diagram specifically illustrating a gate signal waveform in the second frame illustrated in FIG. 2B.

2A and 6A, the pixels driven by the positive polarity (+) in the first frame have a voltage difference between the common voltage Vcom applied to the common electrode and the data voltage Vd applied to the pixel electrode. Is approved. Here, when the common voltage Vcom is lower than the data voltage Vd, the positive voltage is positive, and when the common voltage Vcom is higher than the data voltage Vd, it is negative.

At this time, when the first frame is driven with the positive polarity (+), in which the common voltage Vcom is lower than the data voltage Vd, the first gate signal (1) in the first period T1 for activating a specific gate line. Vg1 is generated with the first voltage Vgh (+ 15v).

Thereafter, the first gate signal Vg1 has a voltage level lower than the first voltage Vgh in the second period T2 for deactivating the specific gate line again. At this time, in the second period T2, the first gate signal Vg1 swings at the same phase and the same magnitude as the common voltage Vcom. That is, the first gate signal Vg1 is generated by repeating the second voltage Vgl1 (−2v) and the third voltage Vgl1 ′; − 7v lower than the second voltage Vhl1.

At this time, when the first gate signal Vg1 transitions from the first period T1 to the second period T2, in the first voltage Vgh1 and the second period T2 in the first period T1. The difference of the second voltage Vgl1 (hereinafter, referred to as the first voltage difference ΔV1) becomes + 17v obtained by subtracting -2v from + 15v.

2B and 6B, when the second frame is driven at a negative polarity (−) where the common voltage Vcom is higher than the data voltage Vd, the first period T1 for activating a specific gate line ), The second gate signal Vg2 is generated with the first voltage Vgh2 (+ 15v). Thereafter, in the second period T2 for deactivating a specific gate line, the second gate signal Vg2 swings in the same manner as the common voltage Vcom. That is, the second gate signal Vg2 is generated by repeating the third voltage Vgh2 '; -7v and the second voltage Vgh2 --2v.

Therefore, when the second gate signal VG2 transitions from the first period T1 to the second period T2, in the first voltage Vgh2 and the second period T2 in the first period T1. The difference of the third voltage Vgh2 'of + 22V is 15v minus -7v.

In this case, the first period T1 of the second gate signal VG2 illustrated in FIG. 6B is divided into a charger period t1 for charging the liquid crystal layer and a compensation period t2 for compensating the kickback voltage. Here, the compensation period t2 preferably satisfies 1/5 or less of the charger t1. For example, when the charger t1 is '100sec', the compensation period t2 has a time of 20 seconds or less, which is 1/5 of '100sec', and the charger t1 is '100sec' to '20sec'. It takes more than 80sec minus'.

It is generated with a voltage sufficient to charge the liquid crystal layer, i.e., + 15v, between the chargers t1 and 10v, which is 5v lower than that between the chargers t1, in the compensation period t2. Therefore, when the second gate signal Vg2 transitions from the first period T1 to the second period T2, the voltage difference (hereinafter referred to as the second voltage difference) ΔV2 of the two periods is the compensation voltage Vgh2 '. The value is obtained by subtracting the third voltage Vgh2 'from. Here, since the compensation voltage Vgh2 'is + 10v and the third voltage Vgh2' is -7v, the second voltage difference ΔV2 becomes + 17V by subtracting -7v from + 10v.

Therefore, the second voltage difference ΔV2 has the same value as the first voltage difference ΔV1, and further, according to Equation 1, the first kickback voltage Vk1 in the first frame and the second in the second frame The kickback voltage Vk2 is also equal to each other.

7A is a waveform diagram illustrating a first gate signal waveform applied to a first frame according to another embodiment of the present invention, and FIG. 7B is a second gate signal waveform applied to a second frame according to another embodiment of the present invention. This is a waveform diagram showing.

Referring to FIG. 7A, when the first frame is driven with a positive polarity (+) in which the common voltage Vcom is lower than the data voltage Vd, the first frame is activated in the first period T1 for activating a specific gate line. The one gate signal Vg1 is generated with the first voltage Vgh + 15v.

Thereafter, the first gate signal Vg1 has a voltage level lower than the first voltage Vgh in the second period T2 for deactivating the specific gate line again. At this time, in the second period T2, the first gate signal Vg1 swings at the same phase and the same magnitude as the common voltage Vcom. That is, the first gate signal Vg1 is generated by repeating the second voltage Vgl1 (−2v) and the third voltage Vgl1 ′; − 7v lower than the second voltage Vhl1.

In this case, the first period T1 of the first gate signal Vg1 is divided into a charger t1 for charging the liquid crystal layer and a compensation period t2 for compensating the kickback voltage. It is generated with a voltage sufficient to charge the liquid crystal layer, that is, + 15v between the chargers t1 and + 20v, which is 5v higher than that between the chargers t1 in the compensation period t2.

Accordingly, when the first gate signal Vg1 transitions from the first period T1 to the second period T2, the voltage difference (hereinafter referred to as the first voltage difference) ΔV1 of the two periods is the compensation voltage Vgh1 ′. The value is obtained by subtracting the second voltage Vgh1 from. Since the compensation voltage Vgh1 'is + 20v and the second voltage Vgh1 is -2v, the second voltage difference ΔV2 becomes + 22V by subtracting -2v from + 20v.

Meanwhile, as shown in FIG. 7B, when the second frame is driven at the negative polarity (−) in which the common voltage Vcom is higher than the data voltage Vd, in the first period T1 for activating a specific gate line. The second gate signal Vg2 is generated with the first voltage Vgh2 (+ 15v).

Thereafter, in the second period T2 for deactivating a specific gate line, the second gate signal Vg2 swings in the same manner as the common voltage Vcom. That is, the second gate signal Vg2 is generated by repeating the third voltage Vgh2 '; -7v and the second voltage Vgh2 --2v.

At this time, when the second gate signal Vg2 transitions from the first period T1 to the second period T2, in the first voltage Vgh2 and the second period T2 in the first period T1. The difference of the second voltage Vgl2 (hereinafter, referred to as a second voltage difference ΔV2) becomes + 22v obtained by subtracting -7v from + 15v.

6A to 7B, only cases where the first and second voltage differences ΔV1 and ΔV2 are completely the same are illustrated, but the first and second voltage differences ΔV1 and ΔV2 do not have to be exactly the same. That is, the difference between the first and second kickback voltages Vk1 and Vk2 may be made small so as not to affect the display characteristics of the liquid crystal display.

According to such a liquid crystal display and a driving method thereof, the gate driver of the liquid crystal display converts a signal for kickback compensation during a first period of selecting one of a first gate signal and a second gate signal to activate a gate line. To the gate line.

Therefore, the flicker phenomenon can be prevented by minimizing the difference in kickback voltage between frames having polarities inverted from each other, and further, the display characteristics of the liquid crystal display can be improved.

Although described with reference to the embodiments above, those skilled in the art will understand that the present invention can be variously modified and changed without departing from the spirit and scope of the invention as set forth in the claims below. Could be.

Claims (9)

A timing controller for outputting an image signal and first and second timing signals for controlling output of the image signal in response to a signal from an external device; A data driver configured to receive the image signal and the first timing signal and output a data signal; The first gate signal is received in the first frame corresponding to the first polarity by receiving the second timing signal, and is different from the first gate signal in the second frame corresponding to the second polarity inverted from the first polarity. A gate driver for outputting a different second gate signal; And A plurality of data lines transferring the data signal, a plurality of gate lines transferring the first or second gate signal, a first end and a second end are connected to the data line and the gate line, and the first or second A liquid crystal display panel displaying an image including a switching element outputting the data signal in response to a two gate signal; The gate driver, A first voltage and a second voltage for kickback compensation during a first period of activating the gate line, and a third voltage and a third voltage lower than the first and second voltages during a second period of inactivation of the gate line. And a first or second gate signal which repeats a fourth voltage lower than the voltage. The liquid crystal display panel of claim 1, further comprising a pixel electrode configured to receive the data signal from the switching element. And the pixel electrode partially overlaps the gate line of the previous stage. The method according to claim 1, wherein when the first polarity is positive polarity (+) and the second polarity is negative polarity (−), And the second gate signal has a second voltage lower than the first voltage in the first period. The liquid crystal display of claim 3, wherein a difference between the first voltage and the second voltage is the same as a difference between the third and fourth voltages. The method according to claim 1, wherein when the first polarity is positive polarity (+) and the second polarity is negative polarity (−), And the first gate signal has a second voltage higher than the first voltage in the first period. The liquid crystal display of claim 5, wherein a difference between the first voltage and the second voltage is equal to a difference between the third voltage and the fourth voltage. A driving method of a liquid crystal display device for displaying an image through a liquid crystal layer, comprising a plurality of data lines, a plurality of gate lines, and first and second ends connected to the data line and the gate line, respectively. (a) generating first and second timing signals for controlling the output of the image signal and the image signal in response to a signal from an external source; (b) receiving the image signal and the first timing signal and outputting a data signal to the data line; And (c) outputting a first gate signal in a first frame corresponding to a first polarity in response to the second timing signal, and a second gate signal in a second frame corresponding to a second polarity inverted from the first polarity; And converting any one of a first and a second gate signal into a signal for kickback compensation in a period for activating the gate line, and providing the converted gate signal to the gate line. The method of claim 7, wherein the kickback compensation signal is inverted by compensating a voltage difference between an on voltage and an off voltage of the second gate signal based on a voltage difference between an on voltage and an off voltage of a first gate signal. A method of driving a liquid crystal display device, characterized in that to reduce the difference in the kickback voltage for each frame having a polarized polarity. The method of claim 7, wherein step (c) is Outputting the first or second gate signal having a first voltage to activate the gate line; Outputting a signal for kickback compensation by converting from the first voltage to a second voltage; And Outputting the first or second gate signal repeating a third voltage lower than the first voltage and the second voltage and a fourth voltage lower than the third voltage to deactivate the gate line. The driving method of the liquid crystal display device.