KR101245942B1 - Liquid crystal panel and Liquid crystal display device and method driving for the same - Google Patents

Abstract

The present invention discloses a liquid crystal panel, a liquid crystal display, and a driving method thereof, which can reduce manufacturing costs by reducing the number of output channels of a data line and a data driver IC electrically connected thereto.

According to an exemplary embodiment of the present invention, a liquid crystal panel includes first, second and third subpixels, a first data line commonly connected to the first and second subpixels, and a second data line electrically connected to the third subpixel. And a gate line arranged to intersect with the first and second data lines.

Data line reduction, subpixel

Description

Liquid crystal panel and Liquid crystal display device and method driving for the same}

1 is a view schematically showing a liquid crystal panel of a conventional liquid crystal display device.

2 is a view illustrating a liquid crystal display device according to an embodiment of the present invention.

3 is a schematic view of the liquid crystal panel of FIG.

4 is a waveform diagram illustrating a gate driving voltage of the gate driver of FIG. 2.

5 is a diagram illustrating a data voltage actually supplied to the liquid crystal panel of FIG. 3.

6 is a view showing another embodiment of the liquid crystal panel of FIG.

7 is a view showing another embodiment of the liquid crystal panel of FIG.

8 is a diagram illustrating a data voltage actually supplied to the liquid crystal panel of FIG. 7.

BRIEF DESCRIPTION OF THE DRAWINGS FIG.

102, 202, 302: Liquid Crystal Panel 104: Gate Driver

106: data driver 108: timing controller

110a to 110c: first to third pixel electrodes

310a to 310d: first to fourth pixel electrodes

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a display device, and more particularly, to a liquid crystal panel, a liquid crystal display device, and a driving method thereof, which can reduce manufacturing costs by reducing the number of lines and the number of output channels of a driver IC.

As the information society develops, the demand for display devices is increasing in various forms. In response to this, various flat panel display devices such as LCD (Liquid Crystal Display Device), PDP (Plasma Display Panel) and ELD (Electro Luminescent Display) have been studied. It is used as a display device.

Among them, liquid crystal displays are the most widely used, replacing CRTs for mobile image display devices because of their excellent image quality, light weight, thinness, and low power consumption. In addition to the mobile use, such as a variety of TV monitors have been developed.

A liquid crystal display device displays an image using the optical anisotropy and polarization property of the liquid crystal. Since the liquid crystal has a long structure, it has a directionality in the arrangement of molecules, and the direction of the molecular arrangement can be controlled by artificially applying an electric field to the liquid crystal.

The liquid crystal display device is divided into a liquid crystal panel for displaying a predetermined image and a driver for driving the liquid crystal panel.

1 is a view schematically showing a liquid crystal panel of a conventional liquid crystal display device.

As shown in FIG. 1, the conventional liquid crystal panel 2 includes first to fourth gate lines GL1 to GL4 and first to fifth data lines DL1 to to define a plurality of pixel regions P. Referring to FIG. DL5) is arranged, and at the intersection thereof, a thin film transistor TFT and a pixel electrode 10 electrically connected to the thin film transistor TFT are formed.

The pixel area P includes first to third subpixels SP1 to SP3, and the first subpixel SP1 includes the first to fourth gate lines GL1 to GL4 and the first and fourth subpixels. It is defined as an area where the data lines DL1 and DL4 intersect, and the second subpixel SP2 is defined as an area where the first to fourth gate lines GL1 to GL4 and the second data line DL2 intersect. The third subpixel SP3 is defined as an area in which the first to fourth gate lines GL1 to GL4 and the third data line DL3 cross each other.

The first pixel electrode 10a corresponding to the red color filter R of the second substrate (not shown) is formed in the first subpixel SP1, and the green color of the second substrate is formed in the second subpixel SP2. A second pixel electrode 10b corresponding to the filter G is formed, and a third pixel electrode 10c corresponding to the blue color filter B of the second substrate is formed in the third subpixel SP3. have.

When a gate scan signal is supplied to the second gate line GL2, the thin film transistor TFT connected to the second gate line GL2 is turned on. When the thin film transistor TFT is turned on, data lines DL1 to DL5 may be formed on the first to third pixel electrodes 10a to 10c formed on the first to third subpixels SP1 to SP3. Is supplied with the data voltage.

Each data voltage supplied to the first to third pixel electrodes 10a to 10c is combined to display a gray level corresponding to one pixel area P. FIG.

As described above, since the subpixels SP of the conventional liquid crystal panel 2 are formed at the intersection of the gate lines GL1 to GL4 and the data lines DL1 to DL5, they are vertical as many as the data lines DL1 to DL5. Form a line. The subpixels SP are arranged in a matrix to form five horizontal lines and four horizontal lines.

As can be seen, conventionally, five data lines DL1 to DL5 are required to drive the subpixels SP. Therefore, five data lines are formed to drive the subpixel SP, which increases the processing time and manufacturing cost.

In addition, the number of output channels of a driver IC for driving each of the data lines increases. As the number of output channels of the driver IC increases, the manufacturing cost also increases.

Accordingly, an object of the present invention is to provide a liquid crystal panel, a liquid crystal display, and a driving method thereof, which can reduce manufacturing costs by reducing the number of lines and the number of output channels of a driver IC.

According to an exemplary embodiment of the present invention, a liquid crystal panel includes first, second and third subpixels, a first data line commonly connected to the first and second subpixels, and the first and second subpixels. And a second data line electrically connected to the three subpixels, and a gate line arranged to intersect the first and second data lines.

According to an exemplary embodiment of the present invention, a liquid crystal display device includes first, second and third subpixels, first data lines commonly connected to the first and second subpixels, A liquid crystal panel including a second data line electrically connected to a third subpixel and a gate line intersecting the first and second data lines, a gate driver supplying first and second scan signals to the gate line; And a data driver for supplying first to third data voltages to the first and second data lines.

In accordance with another aspect of the present invention, there is provided a method of driving a liquid crystal display device, including first, second, and third subpixels, and a first data line commonly connected to the first and second subpixels. And a second data line electrically connected to the third subpixel, and a gate line arranged to intersect the first and second data lines, wherein the first and second scan signals are supplied to the gate lines. Supplying first, second and third data voltages selectively to the first and second data lines according to the driving of the gate line, and supplying the first, second and third data voltages to the first, second and third data voltages. And displaying a corresponding image.

According to a second exemplary embodiment of the present invention, a liquid crystal panel includes: first, second, third and fourth subpixels, a first data line formed between the first and second subpixels; And a second data line formed between the third and fourth subpixels, and a gate line intersecting the first and second data lines.

According to a second exemplary embodiment of the present invention, there is provided a liquid crystal display device including first, second, third and fourth subpixels, a first data line formed between the first and second subpixels; And a liquid crystal panel including a second data line formed between the third and fourth subpixels and a gate line arranged to intersect the first and second data lines, and supplying first and second scan signals to the gate lines. And a data driver for supplying first to fourth data voltages to the first and second data lines.

According to another aspect of the present invention, there is provided a method of driving a liquid crystal display device, including a first, second, third and fourth subpixels, and a first formed between the first and second subpixels. 10. A liquid crystal display device comprising a data line, a second data line formed between the third and fourth subpixels, and a gate line arranged to intersect the first and second data lines, wherein the first and second gate lines are used as the gate lines. Supplying a second scan signal, selectively supplying first, second, third, and fourth data voltages to the first and second data lines according to driving of the gate lines; And displaying an image corresponding to the second, third, and fourth data voltages.

Hereinafter, embodiments according to the present invention will be described with reference to the accompanying drawings.

2 is a diagram illustrating a liquid crystal display according to an exemplary embodiment of the present invention.

As shown in FIG. 2, the liquid crystal display according to the present invention includes a liquid crystal panel 102 in which a plurality of gate lines GL1 to GLn and data lines DL1 to DLm are arranged to display a predetermined image. A gate driver 104 and a data driver 106 for driving the liquid crystal panel 102 and a timing controller 108 for controlling the gate driver 104 and the data driver 106 are included.

The liquid crystal panel 102 is composed of two glass substrates and a liquid crystal layer formed between the two glass substrates. In the liquid crystal panel 102, a plurality of gate lines GL1 to GLn and data lines DL1 to DLm defining a plurality of pixel areas are arranged to display a predetermined image.

A detailed description of the liquid crystal panel 102 will be described later with reference to FIG. 3.

The gate driver 104 supplies a scan signal to the plurality of gate lines GL1 to GLn according to a gate control signal supplied from the timing controller 108.

The data driver 106 supplies a data voltage to the plurality of data lines DL1 to DLm according to a data control signal supplied from the timing controller 108. The data voltage is a voltage obtained by converting the R, G, and B data signals supplied from the timing controller 108 into analog voltages.

The data driver 106 includes a plurality of data driver ICs, which have output channels corresponding to data lines formed on the liquid crystal panel 102.

The timing controller 108 uses the vertical / horizontal synchronization signal Vsync / Hsync, the data enable DE signal, and the predetermined clock signal CLK supplied from a system (not shown). Generate a control signal.

In addition, the timing controller 108 arranges the R, G, and B data signals supplied from the system to match the mode of the liquid crystal panel 102 to supply the data driver 106.

3 is a view showing a liquid crystal panel according to a first embodiment of the present invention.

As shown in FIG. 3, first to fourth gate lines GL1 to GL4 and first to fourth data lines DL1 to DL4 are arranged in the liquid crystal panel 102. The first to fourth gate lines GL1 to GL4 intersect the first to fourth data lines DL1 to DL4 to define first to third subpixels SP1 to SP3.

In detail, the first to fourth gate lines GL1 to GL4 cross the first or third data lines DL1 and DL3 to define first and second subpixels SP1 and SP2, respectively. The first to fourth gate lines GL1 to GL4 intersect the second or fourth data lines DL2 and DL4 to define third subpixels SP3, respectively.

That is, first and second subpixels SP1 and SP2 are formed on the left and right sides of the first data line DL1, and a third subpixel SP3 is formed on the left side of the second data line DL2. .

In FIG. 3, a third subpixel SP3 is formed on the left side of the second data line DL2, but the third subpixel SP3 is formed on the right side of the second data line DL2. It may be.

Similarly, first to third subpixels SP1 to SP3 may be formed on the left and right sides of the third and fourth data lines DL3 and DL4, respectively.

The unit pixel area P is defined by the first to third subpixels SP1 to SP3. For example, the first subpixel SP1 is a region where a red image is displayed, the second subpixel SP2 is a region where a green image is displayed, and the third subpixel SP3 is a region where a blue image is displayed. It may be an area.

The first and second subpixels SP1 and SP2 share the same data line, that is, the first and third data lines DL1 and DL3, whereas the third subpixel SP3 is connected to the second and second subpixels SP3. 4 Connect the data lines DL2 and DL4 independently.

A first pixel electrode 110a corresponding to the red color filter R of the second substrate (not shown) is formed in the first subpixel SP1, and a green color of the second substrate is formed in the second subpixel SP2. A second pixel electrode 110b corresponding to the color filter G is formed, and a third pixel electrode 110c corresponding to the blue color filter B of the second substrate is formed in the third subpixel SP3. do.

Hereinafter, for convenience of description, the description will be limited to the first to third subpixels SP1 to SP3 defined by the second gate line GL2 and the first and second data lines DL1 and DL2. It is apparent that another liquid crystal panel is formed by repeatedly arranging the first to third subpixels by the data line of.

Two thin film transistors, that is, first and second thin film transistors TFT-1 and TFT-2, are formed in the first subpixel SP1.

The first thin film transistor TFT-1 is connected to the source terminal and the pixel electrode R, the drain terminal is connected to the first data line DL1, and the second thin film transistor TFT-2 is connected to the source terminal. The gate terminal of the first thin film transistor TFT-2 is connected, the drain terminal is connected to the next gate line, that is, the third gate line GL3, and the gate terminal is the gate line of the current stage, that is, the second gate line. Connected to GL2.

Accordingly, when the second thin film transistor TFT-2 is turned on by the second scan signal SP2 supplied to the second gate line GL2, the second thin film transistor TFT is turned on. The first scan signal SP1 supplied to the third gate line GL3 is supplied to the first thin film transistor TFT-1 via -2).

In this case, the first thin film transistor TFT-1 is turned on by the second scan signal SP2, and the first thin film transistor TFT-1 is turned on through the first thin film transistor TFT-1. The first data voltage supplied to the first data line DL1 is applied to the first pixel electrode 110a.

Therefore, in order to apply the first data voltage supplied from the first data line DL1 to the first pixel electrode 110a, the first and second thin film transistors TFT-1 and TFT-2 are simultaneously turned on. It should be turned on and for this purpose, the first and second scan signals SP1 and SP2 should overlap for some period.

When the second and first scan signals SP2 and SP1 are simultaneously supplied to the second and third gate lines GL2 and GL3, the first scan signal via the second thin film transistor TFT-2 ( The first thin film transistor TFT-1 is turned on by SP1 so that the first data voltage supplied from the first data line DL1 is the first thin film transistor TFT-1. Is applied to the first pixel electrode 110a via.

In contrast, when the second scan signal SP2 is supplied to the second gate line GL2 and the first scan signal SP1 is not supplied to the third gate line GL3, the second thin film The transistor TFT-2 is turned on, but the first thin film transistor TFT-1 is not supplied because the first scan signal SP1 is not supplied via the second thin film transistor TFT-2. ) Is turned off, so that the first data voltage supplied to the first data line DL1 is not supplied to the first pixel electrode 110a.

As a result, when the second and first scan signals SP2 and SP1 are simultaneously supplied, a first data voltage supplied from the first data line DL1 is applied to the first pixel electrode 110a, and the second scan is applied. When only the signal SP2 is supplied, no data voltage is applied to the first pixel electrode 110a.

One thin film transistor and a third thin film transistor TFT-3 are formed in the second subpixel SP2. In the third thin film transistor TFT-3, a source terminal is connected to the second pixel electrode 110b, a drain terminal is connected to the first data line DL1, and a gate terminal is connected to the second gate line GL2. Connected.

Therefore, the third thin film transistor TFT-3 is turned on only by the second scan signal SP2 supplied to the second gate line GL2, and the third thin film transistor TFT is turned on. When -3) is turned on, the second data voltage supplied from the first data line DL1 via the third thin film transistor TFT-3 is the second pixel electrode 110b. Is applied.

Two thin film transistors, that is, fourth and fifth thin film transistors TFT-4 and TFT-5, are formed in the third subpixel SP3. That is, the third subpixel SP3 is similar to the first subpixel SP1 except that the second data line DL2 is connected.

The fourth thin film transistor TFT-4 has a source terminal connected to the third pixel electrode 110c, a drain terminal connected to the second data line DL2, and the fifth thin film transistor TFT-5 has a source terminal. The gate terminal of the fourth thin film transistor TFT-4 is connected, the drain terminal is connected to the next gate line, that is, the third gate line GL3, and the gate terminal is the gate line of the current stage, that is, the second gate line. Connected to GL2.

Therefore, when the fifth thin film transistor TFT-5 is turned on by the second scan signal SP2 supplied to the second gate line GL2, the fifth thin film transistor TFT is turned on. The first scan signal SP1 supplied from the third gate line GL3 is supplied to the fourth thin film transistor TFT-4 via -5).

In this case, the fourth thin film transistor TFT-4 is turned on by the second scan signal SP2, so that the fourth thin film transistor TFT-4 is turned on by the second thin film transistor TFT-4. The third data voltage supplied from the data line DL2 is applied to the third pixel electrode 110c.

Therefore, the fourth and fifth thin film transistors TFT-4 and TFT-5 are simultaneously turned on to apply the third data voltage supplied from the second data line DL2 to the third pixel electrode 110c. It should be turned on and for this purpose, the second and first scan signals SP2 and SP1 should overlap for some period.

When the second and first scan signals SP2 and SP1 are simultaneously supplied to the second and third gate lines GL2 and GL3, the first scan signal via the fifth thin film transistor TFT-5 is provided. The fourth thin film transistor TFT-4 is turned on by the SP1 so that the third data voltage supplied from the second data line DL2 is the fourth thin film transistor TFT-4. Is applied to the third pixel electrode (110c) via ().

In contrast, when the second scan signal SP2 is supplied to the second gate line GL2 and the first scan signal is not supplied to the third gate line GL3, the fifth thin film transistor TFT− is applied. 5) is turned on, but since the first scan signal SP1 is not supplied via the fifth thin film transistor TFT-5, the fourth thin film transistor TFT-4 is turned on. It is not turned on.

Thus, the third data voltage supplied from the second data line DL2 is not applied to the third pixel electrode 110c.

As a result, when the second and first scan signals SP2 and SP1 are simultaneously supplied, a third data voltage supplied from the second data line DL2 is applied to the third pixel electrode 110c, and the second scan When only the signal SP2 is supplied, no data voltage is supplied to the third pixel electrode 110c.

Therefore, when the second and first scan signals SP2 and SP1 are simultaneously supplied to the second and third gate lines GL2 and GL3 during the first period, the first supplied from the first data line DL1. The data voltage is supplied to the first pixel electrode 110a of the first subpixel SP1 while the third data voltage supplied from the second data line DL2 is the third of the third subpixel SP3. It is applied to the pixel electrode 110c.

Subsequently, when only the second scan signal SP2 is supplied to the second gate line GL2 during the second period, the second data voltage supplied from the first data line DL1 is applied to the second subpixel. It is applied to the second pixel electrode 110b of SP2.

As such, the first and second subpixels SP1 and SP2 are defined by sharing the first data line DL1, which is the same data line DL, and the third subpixel SP3 is defined as the second data line. DL2).

As a result, as the first and second subpixels SP1 and SP2 are defined by sharing the same data line DL1, the pixel area P defined as the first to third subpixels SP1 to SP3 is defined as follows. It can also be defined as two data lines.

정도 감소될 수 있다. As a result, the number of data lines DL1 to DL4 arranged on the liquid crystal panel 102 is lower than that of the conventional liquid crystal panel.

Degree can be reduced.

In addition, the number of output channels of the data driver IC electrically connected to the data line may be reduced. As the number of data lines and the number of output channels of a data driver IC are reduced, manufacturing costs for manufacturing the data lines may be reduced.

4 is a waveform diagram illustrating a gate driving voltage of the gate driver of FIG. 2.

As shown in FIGS. 3 and 4, the gate driver 104 of FIG. 2 sequentially supplies gate scan signals to the first to fourth gate lines GL1 to GL4.

The gate driver 104 supplies a first scan signal SP1 and a second scan signal SP2 to the first to fourth gate lines GL1 to GL4, respectively. The second scan signal SP2 is set to have a wider width than the first scan signal SP1.

The gate driver 104 has a second horizontal interval between the second scan signal SP2 supplied to the first gate line GL1 and the first scan signal SP1 supplied to the second gate line GL2. For example, 1 / 2H). Only the second scan signal SP2 is supplied to the first gate line GL1 during one horizontal section 1H.

The gate driver 104 supplies the second scan signal SP2 to the first gate line GL1 for one horizontal section 1H and ½ horizontal section 1 to the second gate line GL2. / 2H) to supply the first scan signal SP1. Subsequently, the gate driver 104 does not supply the first and second scan signals SP1 and SP2 to the second gate line GL2 for the remaining 1/2 horizontal section 1 / 2H.

In succession, the gate driver 104 supplies the second scan signal SP2 to the second gate line GL2 for one horizontal section 1H and ½ horizontal section to the third gate line GL3. The first scan signal SP1 is supplied during (1 / 2H).

The gate scan signals supplied to the first to fourth gate lines GL1 to GL4 will be described in detail as follows.

The second scan signal SP2 is supplied to the second gate line GL2 for one horizontal section 1H and the first scan signal for 1/2 horizontal section 1 / 2H to the third gate line GL3. A section where SP1 is supplied and overlapped during the 1/2 horizontal section (1 / 2H) is defined as an A section.

The second and fifth thin film transistors TFT-2 and TFT-5 and the second subpixel of the first and third subpixels SP1 and SP3 defined as the second gate line GL2 during the A period. The third thin film transistor TFT-3 of SP2 is turned on.

The second scan signal SP2 is supplied to the gate terminals of the second and third thin film transistors TFT-2 and TFT-3 electrically connected to the second gate line GL2, and at the same time, the third The first scan signal SP1 is supplied to a source terminal of the second thin film transistor TFT-2 electrically connected to a gate line GL3 and a source terminal of the fifth thin film transistor TFT-5.

The source terminal of the second thin film transistor TFT-2 is electrically connected to the gate terminal of the first thin film transistor TFT-1, and the source terminal of the fifth thin film transistor TFT-5 is the fourth thin film transistor. The gate terminal of the first and fourth thin film transistors TFT-1 and TFT-4 of the first and third subpixels SP1 and SP3 is electrically connected to the gate terminal of the TFT-4. As the first scan signal SP1 is supplied, the first and fourth thin film transistors TFT-1 and TFT-4 are turned on.

As a result, first and third data voltages are supplied from the first to fourth data lines DL1 to DL4 to the first to third subpixels SP1 to SP3. The first and third data voltages are supplied to the first and third pixel electrodes R and B formed in the first and third subpixels SP1 and SP3, respectively.

The data voltage is supplied to the first to third subpixels SP1 to SP3 during the A period. In this case, the data voltage supplied to the second subpixel SP2 during the A period is a dummy data voltage. That is, the data voltage supplied to the second subpixel SP2 during the A period is not a voltage for displaying an actual image.

Continuously, a state in which the second scan signal SP2 is supplied to the second gate line GL2 and the first scan signal SP1 is not supplied to the third gate line GL3 are continued. It is defined as the interval B.

Since the second scan signal SP2 is supplied only to the second gate line GL2 during the B period, the second, third and fifth thin film transistors TFT-2, connected to the second gate line GL2, Even if both of the TFT-3 and TFT-5 are turned on, no signal passes through the second and fifth thin film transistors TFT-2 and TFT-5, so that the second and the second 5 The first and fourth thin film transistors TFT-1 and TFT-4 connected to the thin film transistors TFT-2 and TFT-5 are not turned on, and the second subpixel SP2 is not turned on. Only the third thin film transistor TFT-3 formed therein is turned on.

Therefore, a second data voltage is supplied to the second subpixel SP2.

As a result, a second data voltage is supplied to the second pixel electrode B formed in the second subpixel SP2 during the B period. The second data voltage supplied to the second subpixel SP2 during the B period becomes a voltage for displaying an actual image.

Data voltages are supplied to the first to third subpixels SP1 to SP3 during the A and B periods so that a predetermined image is displayed on the liquid crystal panel 102 of FIG. 2.

Subsequently, a section in which the second scan signal SP2 is supplied to the third gate line GL3 and the first scan signal SP1 is supplied to the fourth gate line GL4 is defined as a C section. The first and second scan signals SP1 and SP2 are not supplied to the second gate line GL2 during the C period.

The second and fifth thin film transistors TFT-2 and TFT-5 and the second subpixel formed in the first and third subpixels SP1 and SP3 defined by the third gate line GL3 during the C period. The second scan signal SP2 is supplied to the third thin film transistor TFT-3 formed at SP2. As a result, the second, third and fifth thin film transistors TFT-2, TFT-3, and TFT-5 are turned on.

The first and fourth thin films formed in the first and third subpixels SP1 and SP3 as the second and fifth thin film transistors TFT-2 and TFT-5 are turned on. The transistors TFT-1 and TFT-4 are turned on.

During the C period, the first and fourth thin film transistors TFT-1 and TFT-4 formed in the first and third subpixels SP1 and SP3 are turned on and thus, the first First and third data voltages are supplied to the first and third subpixels SP1 and SP3 through the fourth to fourth data lines DL1 to DL4.

That is, the first and third data voltages are supplied to the first and third pixel electrodes R and B formed in the first and third subpixels SP1 and SP3.

The data voltage supplied to the second subpixel SP2 during the C period is a dummy data voltage. The data voltage supplied to the second pixel electrode B during the C period is not a voltage for displaying an actual image.

Like the period A, the data voltage supplied to the second subpixel SP2 during the period C is a dummy data voltage.

Continuously, the period D where the second scan signal SP2 supplied to the third gate line GL3 continues and the first scan signal SP1 is not supplied to the fourth gate line GL4. It is defined as

Only the third thin film transistor TFT-3 formed in the second subpixel SP2 is turned on during the D period. As the third thin film transistor TFT-3 is turned on, a second data voltage is supplied to the second subpixel SP2.

The second data voltage supplied to the second subpixel SP2 during the D period is a voltage for displaying an actual image.

5 is a diagram illustrating a data voltage actually supplied to the liquid crystal panel of FIG. 3.

4 and 5, a first data voltage R is supplied to the odd data lines DL1 and DL3 and the first data voltage DL1 and DL3 is supplied to the odd data lines DL1 and DL3 during the A period. The data voltage R is supplied to the first subpixel SP1 electrically connected to the odd-numbered data lines DL1 and DL3.

The third data voltage B is supplied to even-numbered data lines DL2 and DL4 and the third data voltage B is supplied to even-numbered data lines DL2 and DL4 during the period A. The third subpixel SP3 is connected to the data lines DL2 and DL4.

Subsequently, during the period B, the second data voltage G is supplied to the odd data lines DL1 and DL3 and the second data voltage G supplied to the odd data lines DL1 and DL3 is the odd number. The second subpixel SP2 is electrically connected to the first data lines DL1 and DL3. In addition, no data voltage is supplied to the even-numbered data lines DL2 and DL4 during the B period.

As a result, in the period B, the second data voltage G is supplied only to the odd-numbered data lines DL1 and DL3.

The first and third data voltages R and B supplied during the A section and the second data voltage G supplied during the B section are supplied to the first to third subpixels SP1 to SP3, respectively. One gradation is displayed.

Similarly to the section A, the first data voltage R is supplied to the odd data lines DL1 and DL3 during the section C, and the first data voltage R is supplied to the odd data lines DL1 and DL3. The first subpixel SP1 is connected to the odd-numbered data lines DL1 and DL3.

The third data voltage B is supplied to even-numbered data lines DL2 and DL4 during the period C, and the third data voltage B is supplied to the even-numbered data lines DL2 and DL4 during the period C. The third subpixel SP3 is connected to the first data lines DL2 and DL4.

Subsequently, the second data voltage G is supplied to the odd data lines DL1 and DL3 and the second data voltage supplied to the odd data lines DL1 and DL3 during the D period similarly to the B period. G is supplied to the second subpixel SP2 connected to the odd-numbered data lines DL1 and DL3. Further, no data voltage is supplied to the even-numbered data lines DL2 and DL4 during the D period.

As a result, in the D period, the second data voltage G is supplied only to the odd-numbered data lines DL1 and DL3.

The first and third data voltages R and B supplied during the C period and the second data voltage G supplied during the D period are respectively supplied to the first to third subpixels SP1 to SP3. One gradation is displayed.

The first and third data voltages R and B are supplied to the first and third subpixels SP1 and SP3 during the A and C periods, and the second data voltage G is the B and D periods. Is supplied to the second subpixel SP2 during the process. First, second, and third data voltages R, G, and B are respectively supplied to the first to third subpixels SP1 to SP3 to provide a predetermined image on the liquid crystal panel 102 of FIG. 3. Can be displayed.

As described above, the liquid crystal panel according to the present invention includes a pixel area including first and second subpixels SP1 and SP2 that share the same data line and a third subpixel SP3 defined as a data line adjacent to the data line. The configuration can reduce the number of data lines. Since only two data lines are required per pixel area, the number of data lines is reduced and the number of output channels of the data driver IC electrically connected to the data lines is also reduced.

As the number of data lines and the number of output channels of a data driver IC electrically connected to the data lines are reduced, a manufacturing cost for manufacturing the data lines may be reduced.

6 is a view showing a liquid crystal panel according to a second embodiment of the present invention.

As illustrated in FIG. 6, the liquid crystal panel 202 according to another embodiment may share the even-numbered data lines DL2 and DL4 with the second and third subpixels SP2 and SP3 and the even-numbered data. A plurality of pixel areas P including the first subpixel SP1 defined by the odd data lines DL1 and DL3 adjacent to the lines DL2 and DL4 are provided.

In the detailed description of the liquid crystal panel 202, the same parts as those of the liquid crystal panel 102 shown in FIG. 3 will be omitted.

In this case, the second subpixel SP2 is formed on the left side of the even-numbered data lines DL2 and DL4, and the third subpixel SP3 is formed on the right side of the even-numbered data lines DL2 and DL4. The first subpixel SP1 is formed on the left side of the odd data lines DL1 and DL3.

First and second thin film transistors TFT-1 and TFT-2 are formed at the first subpixel SP1, and fourth and fifth thin film transistors TFT-4, are formed at the second subpixel SP2. TFT-5 is formed and the third thin film transistor TFT-3 is formed in the third subpixel SP3.

The first to fifth thin film transistors TFT-1 to TFT-5 are the same as the first to fifth thin film transistors TFT-1 to TFT-5 shown in FIG. 3.

7 is a view showing a liquid crystal panel according to a third embodiment of the present invention.

As illustrated in FIG. 7, the liquid crystal panel 302 may share a first data line DL1 with a first and second subpixels SP1 and SP2 with a third data line DL2. And a plurality of pixel areas including the fourth subpixels SP3 and SP4.

In the detailed description of the liquid crystal panel 302, the same parts as those of the liquid crystal panel 102 shown in FIG. 3 will be omitted.

A first pixel electrode 310a corresponding to the red color filter R (not shown) is formed in the first subpixel SP1, and a first green color filter G1 is formed in the second subpixel SP2. A corresponding second pixel electrode 310b is formed, and a third pixel electrode 310c corresponding to the second green color filter G2 is formed in the third subpixel SP3, and the fourth subpixel SP4. ), A fourth pixel electrode 310d corresponding to the blue color filter B is formed.

The first to fourth subpixels SP1 to SP4 define the pixel region P. FIG.

The first and second subpixels SP1 and SP2 share a first data line DL1, and the first subpixel SP1 is formed on the left side of the first data line DL1 and is formed on the second data line DL1. The subpixel SP2 is formed on the right side of the first data line DL1.

The third and fourth subpixels SP3 and SP4 share a second data line DL2, and the third subpixel SP3 is formed on the left side of the second data line DL2 and is located in the fourth. The subpixel SP4 is formed on the right side of the second data line DL2.

First and second thin film transistors TFT-1 and TFT-2 are formed in the first subpixel SP1, and a third thin film transistor TFT-3 is formed in the second subpixel SP2. The fourth thin film transistor TFT-4 is formed in the third subpixel SP3, and the fifth and sixth thin film transistors TFT-5 and TFT-6 are formed in the fourth subpixel SP4. do.

The first to sixth thin film transistors TFT-1 to TFT-3 perform the same functions as the first to third thin film transistors TFT-1 to TFT-3 shown in FIG. 3.

In this case, the second pixel electrode 310b formed on the second subpixel SP2 corresponds to the first green color filter G1 and the third pixel electrode 310c formed on the third subpixel SP3 is the second. It corresponds to the green color filter G2.

When the second scan signal SP2 is supplied to the second gate line GL2 and the first scan signal SP1 is supplied to the third gate line GL3, the first formed in the first subpixel SP1. The first and second thin film transistors TFT-1 and TFT-2 are simultaneously turned on and the first data voltage supplied from the first data line DL1 is the first pixel electrode 310a. Is applied to.

In this case, the fifth and sixth thin film transistors TFT-5 and TFT-6 formed in the fourth subpixel SP4 are turned on at the same time and are supplied from the second data line DL2. A fourth data voltage is applied to the fourth pixel electrode 310d.

Subsequently, when the second scan signal SP2 is supplied to the second gate line GL2 and the first scan signal SP1 is not supplied to the third gate line GL3, the second subpixel SP2 is provided. The third thin film transistor TFT-3 formed at the gate is turned on and a second data voltage supplied from the first data line DL1 is applied to the second pixel electrode 310b.

In this case, the fourth thin film transistor TFT-4 formed in the third subpixel SP3 is also turned on so that the third data voltage supplied from the second data line GL2 is converted into the third data voltage. It is applied to the pixel electrode 310c.

FIG. 8 is a diagram illustrating a data voltage actually supplied to the liquid crystal panel of FIG. 7.

4 and 8, a first data voltage R is supplied to the odd data lines DL1 and DL3 and the first data voltage DL1 and DL3 is supplied to the odd data lines DL1 and DL3 during the A period. The first data voltage R is supplied to the first subpixel SP1.

At the same time, a fourth data voltage B is supplied to the even-numbered data lines DL2 and DL4, and a fourth data voltage B supplied to the even-numbered data lines DL2 and DL4 is a fourth subpixel. SP4).

Subsequently, a second data voltage G1 is supplied to the odd-numbered data lines DL1 and DL3 and the second data voltage G1 supplied to the odd-numbered data lines DL1 and DL3 during the period B is set to the first period. 2 subpixels SP2 are supplied.

At the same time, a third data voltage G2 is supplied to the even-numbered data lines DL2 and DL4 and a third data voltage G2 supplied to the even-numbered data lines DL2 and DL4 is the third subpixel SP3. Is supplied.

The second and third data voltages G1 and G2 are supplied to the second and third subpixels SP2 and SP3, respectively, and the second and third data voltages G1 and G2 are supplied to the second and third subpixels SP2 and SP3, respectively. The three data voltages G1 and G2 represent one green data voltage G.

The first and fourth data voltages R and B supplied during the A section and the second and third data voltages G1 and G2 supplied during the B section are supplied to the first to fourth subpixels, respectively. One gradation is displayed.

Subsequently, a first data voltage R is supplied to the odd-numbered data lines DL1 and DL3 and the first data voltage R supplied to the odd-numbered data lines DL1 and DL3 is a first period during the C period. It is supplied to the subpixel SP1. At the same time, a fourth data voltage B is supplied to the even-numbered data lines DL2 and DL4 and the fourth data voltage B supplied to the even-numbered data lines DL2 and DL4 is a fourth subpixel SP4. Is supplied.

Subsequently, during the D period, the second data voltage G1 is supplied to the odd data lines DL1 and DL3 and the second data voltage G1 supplied to the odd data lines DL1 and DL3 is equal to the second data voltage G1. 2 subpixels SP2 are supplied. At the same time, the third data voltage G2 is supplied to the even-numbered data lines DL2 and DL4 and the third data voltage G2 supplied to the even-numbered data lines DL2 and DL4 is the third subpixel SP3. Is supplied.

The second and third data voltages G1 and G2 are supplied to the second and third subpixels SP2 and SP3, respectively, and the second and third data voltages G1 and G2 are supplied to the second and third subpixels SP2 and SP3, respectively. The three data voltages G1 and G2 represent one green data voltage G.

As a result, the first and fourth data voltages R and B supplied during the C period and the second and third data voltages G1 and G2 supplied during the D period are respectively the first to fourth subpixels ( SP1 to SP4) to display one gray scale.

The first and fourth data voltages R and B are supplied to the first and fourth subpixels SP1 and SP4 during the periods A and C, and the second and third data voltages G1 and G2 are respectively connected to each other. The second and third subpixels SP2 and SP3 are supplied to the B and D periods. First to fourth data voltages R, G1, G2, and B may be respectively supplied to the first to fourth sub-pixels SP1 to SP4 to display a predetermined image on the liquid crystal panel 302. .

As described above, the liquid crystal panel according to the present invention can reduce the data line and reduce the number of output channels of the data driver IC electrically connected to the data line as two subpixels share one data line. As the number of data lines decreases and the number of output channels of a data driver IC decreases, manufacturing costs for manufacturing the data lines and the data driver ICs may be reduced.

In the liquid crystal panel according to the present invention, one pixel area is defined by first and second subpixels sharing the same data line and a third subpixel defined by a data line adjacent to the data line. Since only data lines are required, the number of data lines can be reduced.

In addition, as the number of data lines decreases, the number of output channels of a data driver IC electrically connected to the data lines decreases, thereby reducing manufacturing costs for manufacturing the data lines and the data driver ICs.

The technical scope of the present invention should not be limited to the contents described in the detailed description of the specification but should be defined by the claims.

Claims (37)

delete delete delete delete delete delete delete delete delete delete delete delete delete delete delete delete delete delete delete delete delete delete delete delete delete First, second and third subpixels, a first data line commonly connected to the first and second subpixels, a second data line electrically connected to the third subpixel, and the first and second subpixels A liquid crystal panel including gate lines arranged to intersect with the data lines; A gate driver supplying first and second scan signals to the gate line; And The first data line supplies a first data voltage to the first subpixel during a first period, and the second data line supplies a third data voltage to the third subpixel during the first period. Wherein the first data line supplies a second data voltage to the second subpixel during the second period and the second data line includes a data driver that does not supply any data voltage during the second period. Device. The method of claim 26, And the second scan signal is set to have a wider width than the first scan signal. First, second, third, and fourth subpixels, a first data line formed between the first and second subpixels, a second data line formed between the third and fourth subpixels, and the first subpixel; A liquid crystal panel including gate lines arranged to intersect with the first and second data lines; A gate driver supplying first and second scan signals to the gate line; And The first data line supplies a first data voltage to the first subpixel during a first period, and the second data line supplies a fourth data voltage to the fourth subpixel during the first period. A first data line includes a data driver for supplying a second data voltage to the second subpixel during the second period and the second data line for supplying a third data voltage to the third subpixel during the second period; Liquid crystal display device characterized in that. The method of claim 28, And the second scan signal is set to have a wider width than the first scan signal. First, second and third subpixels, a first data line commonly connected to the first and second subpixels, a second data line electrically connected to the third subpixel, and the first and second subpixels A driving method of a liquid crystal display device including a gate line arranged to intersect with a data line, Supplying first and second scan signals to the gate lines; Selectively supplying first, second and third data voltages to the first and second data lines according to the driving of the gate line; And Displaying an image corresponding to the first, second, and third data voltages; The first data line supplies the first data voltage to the first subpixel during a first period, and the second data line supplies the third data voltage to the third subpixel during the first period, The first data line supplies the second data voltage to the second subpixel during a second period, and the second data line does not supply any data voltage during the second period. Driving method. delete 31. The method of claim 30, And the first section is a section in which the second scan signal is supplied to the gate line and the first scan signal is supplied to another gate line adjacent to the gate line. 31. The method of claim 30, And wherein the second section is a section in which the second scan signal is supplied to a gate line and the first scan signal is not supplied to another gate line adjacent to the gate line. First, second, third, and fourth subpixels, a first data line formed between the first and second subpixels, a second data line formed between the third and fourth subpixels, and the first subpixel; A driving method of a liquid crystal display device including a gate line arranged to intersect with first and second data lines, Supplying first and second scan signals to the gate lines; Selectively supplying first, second, third and fourth data voltages to the first and second data lines according to the driving of the gate line; And Displaying an image corresponding to the first, second, third and fourth data voltages, The first data line supplies the first data voltage to the first subpixel during a first period, and the second data line supplies the fourth data voltage to the fourth subpixel during the first period, Wherein the first data line supplies the second data voltage to the second subpixel during a second period and the second data line supplies the third data voltage to the third subpixel during the second period. A method of driving a liquid crystal display device. delete 35. The method of claim 34, And the first section is a section in which the second scan signal is supplied to the gate line and the first scan signal is supplied to another gate line adjacent to the first gate line. 35. The method of claim 34, And wherein the second section is a section in which the second scan signal is supplied to the gate line and the first scan signal is not supplied to another gate line adjacent to the gate line.

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