CN113393788A - Display panel driving method and device and display device - Google Patents
Display panel driving method and device and display device Download PDFInfo
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- CN113393788A CN113393788A CN202110554994.1A CN202110554994A CN113393788A CN 113393788 A CN113393788 A CN 113393788A CN 202110554994 A CN202110554994 A CN 202110554994A CN 113393788 A CN113393788 A CN 113393788A
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- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
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- G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
- G09G3/28—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using luminous gas-discharge panels, e.g. plasma panels
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Abstract
The invention discloses a driving method and a device of a display panel and a display device, wherein the display panel comprises: the pixel array comprises a plurality of pixel groups, wherein each pixel group comprises two rows of adjacent sub-pixel groups, and the storage capacitors of one sub-pixel in each sub-pixel group and two non-adjacent sub-pixels in the other sub-pixel group are respectively connected with a first common electrode line; the storage capacitors of one sub-pixel in each sub-pixel group and two adjacent sub-pixels in the other sub-pixel group are connected with the other first common electrode wire; each sub-pixel group is connected with a data line with the sub-pixel groups of adjacent rows of adjacent columns; the driving method of the display panel comprises the following steps: controlling the data voltage on each data line to switch the positive polarity and the negative polarity once every two frames; and controlling the voltage level of the common electrode on each first common electrode line to switch high and low by taking two frames as a driving period.
Description
Technical Field
The present invention relates to the technical field of display devices, and in particular, to a method and an apparatus for driving a display panel, and a display device.
Background
At present, a large-sized display panel needs a large viewing angle, and during a pixel driving process, the large viewing angle brightness is rapidly saturated with voltage, so that the viewing angle image quality contrast and the color cast are seriously deteriorated compared with the front-view image quality. The common way to solve the color shift of the viewing angle is to divide each sub-pixel of the display panel into a main pixel and a sub-pixel, and to apply different driving voltages to the main pixel and the sub-pixel, such a design usually needs to design a metal trace or a TFT element to drive the sub-pixel, which results in the sacrifice of the light-permeable opening area, the influence on the panel transmittance, and the direct increase of the backlight cost.
Disclosure of Invention
The invention provides a driving method and a driving device of a display panel and a display device, and aims to solve the problem of image quality color cast caused by visual angle deviation.
To achieve the above object, the present invention provides a driving method of a display panel, the display panel including:
each pixel group comprises two rows of adjacent sub-pixel groups, each two rows of adjacent sub-pixel groups are respectively connected with one scanning line, each sub-pixel group comprises two sub-pixels, and the two sub-pixels are connected with the same scanning line;
in two sub-pixel groups in adjacent rows, the storage capacitors of two adjacent sub-pixels are connected with the same first common electrode wire, and the storage capacitors of two non-adjacent sub-pixels are correspondingly connected with the other two first common electrode wires one by one;
two data lines which are positioned in the same row and are respectively connected with two adjacent sub-pixel groups are adjacent, and two data lines which are positioned in the adjacent row and are respectively connected with two adjacent sub-pixel groups are adjacent;
the polarities of the voltages on the two adjacent first common electrode lines are opposite; the driving method of the display panel includes the steps of:
controlling the data voltage on each data line to switch the positive polarity and the negative polarity once every two frames;
and controlling the voltage level of the common electrode on each first common electrode line to switch high and low by taking two frames as a driving period.
Optionally, the step of controlling the data voltage on each data line to perform one positive and negative polarity switching with two frames as one driving period includes:
the polarity of a data voltage on one data line in the data lines of two adjacent columns of the sub-pixels is positive polarity, negative polarity and negative polarity sequentially in four adjacent frames;
and the polarities of the data voltage on the other data line in the data lines of the two adjacent columns of the sub-pixels are negative polarity, positive polarity and positive polarity in sequence in four adjacent frames.
Optionally, the scan signal on each scan line in each frame includes an on-phase and an off-phase, and the common electrode voltage on the first common electrode line is controlled to perform high-low level switching when the scan signal on each scan line is switched from the on-phase to the off-phase.
Optionally, the step of controlling the common electrode voltage on the first common electrode line to perform high-low level switching when the scanning signal of each scanning line is switched from an on phase to an off phase includes:
two rows of sub-pixels in the same group are respectively an nth row of sub-pixels and an n +1 th row of sub-pixels;
in a first frame of adjacent four frames, when the data voltage of the sub-pixels of the nth row and the sub-pixels of the (n +1) th row are positive, controlling the voltage of the common electrode of the sub-pixels of the nth row to be switched from low level to high level, and controlling the voltage of the common electrode of the sub-pixels of the (n +1) th row to be switched from high level to low level;
in a second frame of adjacent four frames, when the data voltage of the sub-pixels of the nth row and the sub-pixels of the (n +1) th row are controlled to be positive, the voltage of the common electrode of the sub-pixels of the nth row is controlled to be switched from high level to low level, and the voltage of the common electrode of the sub-pixels of the (n +1) th row is controlled to be switched from low level to high level;
in a third frame of adjacent four frames, when the data voltage of the sub-pixels of the nth row and the sub-pixels of the (n +1) th row are controlled to be negative, the voltage of the common electrode of the sub-pixels of the nth row is controlled to be switched from low level to high level, and the voltage of the common electrode of the sub-pixels of the (n +1) th row is controlled to be switched from high level to low level;
in a fourth frame of adjacent four frames, when the data voltage of the sub-pixels of the nth row and the sub-pixels of the (n +1) th row are controlled to be negative polarity, the voltage of the common electrode of the sub-pixels of the nth row is controlled to be switched from high level to low level, and the voltage of the common electrode of the sub-pixels of the (n +1) th row is controlled to be switched from low level to high level.
Optionally, the step of controlling the common electrode voltage on the first common electrode line to perform high-low level switching when the scanning signal of each scanning line is switched from an on phase to an off phase includes:
two rows of sub-pixels in the same group are respectively an nth row of sub-pixels and an n +1 th row of sub-pixels;
in a first frame of adjacent four frames, when the data voltage of the sub-pixels of the nth row and the sub-pixels of the (n +1) th row are positive, controlling the common electrode voltage of the sub-pixels of the nth row to be switched from high level to low level, and controlling the common electrode voltage of the sub-pixels of the (n +1) th row to be switched from low level to high level;
in a second frame of adjacent four frames, when the data voltage of the sub-pixels of the nth row and the sub-pixels of the (n +1) th row are controlled to be positive, the voltage of the common electrode of the sub-pixels of the nth row is controlled to be switched from low level to high level, and the voltage of the common electrode of the sub-pixels of the (n +1) th row is controlled to be switched from high level to low level;
in a third frame of adjacent four frames, when the data voltage of the sub-pixels of the nth row and the sub-pixels of the (n +1) th row are controlled to be negative, the voltage of the common electrode of the sub-pixels of the nth row is controlled to be switched from high level to low level, and the voltage of the common electrode of the sub-pixels of the (n +1) th row is controlled to be switched from low level to high level;
in a fourth frame of adjacent four frames, when the data voltage of the sub-pixels of the nth row and the sub-pixels of the (n +1) th row are controlled to be negative polarity, the voltage of the common electrode of the sub-pixels of the nth row is controlled to be switched from low level to high level, and the voltage of the common electrode of the sub-pixels of the (n +1) th row is controlled to be switched from high level to low level.
Optionally, in the step of controlling the common electrode voltage level on each first common electrode line to perform high-low switching with two frames as one driving period, the high-low switching sequence of two adjacent driving periods is different.
Optionally, the step of controlling the common electrode voltage on the first common electrode line to perform high-low level switching when the scanning signal of each scanning line is switched from an on phase to an off phase includes:
two rows of sub-pixels in the same group are respectively an nth row of sub-pixels and an n +1 th row of sub-pixels;
in a first frame of adjacent four frames, when the data voltage of the sub-pixels of the nth row and the sub-pixels of the (n +1) th row are positive, controlling the voltage of the common electrode of the sub-pixels of the nth row to be switched from low level to high level, and controlling the voltage of the common electrode of the sub-pixels of the (n +1) th row to be switched from high level to low level;
in a second frame of adjacent four frames, when the data voltage of the sub-pixels of the nth row and the sub-pixels of the (n +1) th row are controlled to be positive, the voltage of the common electrode of the sub-pixels of the nth row is controlled to be switched from high level to low level, and the voltage of the common electrode of the sub-pixels of the (n +1) th row is controlled to be switched from low level to high level;
in a third frame of adjacent four frames, when the data voltage for controlling the sub-pixels of the nth row and the sub-pixels of the (n +1) th row is negative, the voltage of the common electrode of the sub-pixels of the nth row is controlled to be switched from high level to low level in the same way as the second frame, and the voltage of the common electrode of the sub-pixels of the (n +1) th row is controlled to be switched from low level to high level in the same way as the second frame;
in a fourth frame of adjacent four frames, when the data voltage of the sub-pixels of the nth row and the sub-pixels of the (n +1) th row are controlled to be negative polarity, the voltage of the common electrode of the sub-pixels of the nth row is controlled to be switched from low level to high level, and the voltage of the common electrode of the sub-pixels of the (n +1) th row is controlled to be switched from high level to low level.
Optionally, the step of controlling the common electrode voltage on the first common electrode line to perform high-low level switching when the scanning signal of each scanning line is switched from an on phase to an off phase includes:
two rows of sub-pixels in the same group are respectively an nth row of sub-pixels and an n +1 th row of sub-pixels;
in a first frame of adjacent four frames, when the data voltage of the sub-pixels of the nth row and the sub-pixels of the (n +1) th row are positive, controlling the common electrode voltage of the sub-pixels of the nth row to be switched from high level to low level, and controlling the common electrode voltage of the sub-pixels of the (n +1) th row to be switched from low level to high level;
in a second frame of adjacent four frames, when the data voltage of the sub-pixels of the nth row and the sub-pixels of the (n +1) th row are controlled to be positive, the voltage of the common electrode of the sub-pixels of the nth row is controlled to be switched from low level to high level, and the voltage of the common electrode of the sub-pixels of the (n +1) th row is controlled to be switched from high level to low level;
in a third frame of adjacent four frames, when the data voltage for controlling the sub-pixels of the nth row and the sub-pixels of the (n +1) th row is negative, the voltage of the common electrode of the sub-pixels of the nth row is controlled to be switched from low level to high level in the same way as the second frame, and the voltage of the common electrode of the sub-pixels of the (n +1) th row is controlled to be switched from high level to low level in the same way as the second frame;
in a fourth frame of adjacent four frames, when the data voltage of the sub-pixels of the nth row and the sub-pixels of the (n +1) th row are controlled to be negative polarity, the voltage of the common electrode of the sub-pixels of the nth row is controlled to be switched from high level to low level, and the voltage of the common electrode of the sub-pixels of the (n +1) th row is controlled to be switched from low level to high level.
Optionally, the driving method of the display panel further includes:
the polarities of the sub-pixels on the same data line are the same, the polarities of the voltages of the adjacent data lines are opposite, and the data lines of the display panel are driven in a row-column inversion mode.
The present invention also provides a driving apparatus of a display panel, the display panel including:
each pixel group comprises two rows of adjacent sub-pixel groups, each two rows of adjacent sub-pixel groups are respectively connected with one scanning line, each sub-pixel group comprises two sub-pixels, and the two sub-pixels are connected with the same scanning line;
in two sub-pixel groups in adjacent rows, the storage capacitors of two adjacent sub-pixels are connected with the same first common electrode wire, and the storage capacitors of two non-adjacent sub-pixels are correspondingly connected with the other two first common electrode wires one by one;
two data lines which are positioned in the same row and are respectively connected with two adjacent sub-pixel groups are adjacent, and two data lines which are positioned in the adjacent row and are respectively connected with two adjacent sub-pixel groups are adjacent;
the polarities of the voltages on the two adjacent first common electrode lines are opposite, and the polarities of the data voltages on the data lines of the sub-pixels in each group positioned in the same column are the same; the driving device of the display panel includes:
the source driving circuit is configured to output data voltages with switched positive and negative polarities to the data lines every two frames;
the output end of the common electrode voltage circuit is connected with each first common electrode wire, and the common electrode voltage circuit is configured to output a common electrode voltage switched by high and low levels to each first common electrode wire by taking two frames as a driving period;
the driving device of the display panel is further provided with a processor, a memory and a driving program of the display panel, which is stored on the memory and can run on the processor, wherein the driving program of the display panel is configured to realize the steps of the driving method of the display panel.
Optionally, the driving apparatus of the display panel further includes a gate driving circuit, and the gate driving circuit is connected to the gate of each of the sub-pixels; the gate driving circuit is configured to output a gate driving signal to each row of sub-pixels, so that corresponding voltages are applied to the second common electrode and the data line, and the sub-pixel capacitors in the corresponding row are charged.
The invention also provides a display device, which comprises a display panel and the driving device of the display panel, wherein the driving device of the display panel is connected with each sub-pixel of the display panel.
In the driving method of the display panel, in each sub-pixel group in one frame, because the same column of data voltage has the same polarity and the common electrode voltage on the first common electrode has different levels, the brightness displayed by the two sub-pixels is different. And when four frames are taken as a driving period, positive and negative polarity switching is carried out every two frames by controlling the data voltage on each data line, and the common electrode voltage level on each first common electrode line is controlled in a matching manner, so that high and low switching is carried out by taking two frames as one driving period. The arrangement is such that within the same group, the display luminance of two sub-pixels in the same column is switched between brighter and darker in units of two frames, and the display luminance of two sub-pixels in adjacent columns in one frame is switched between brighter and darker. And the two adjacent sub-pixels in the same row can have darker and brighter changes, and for the complete row, the whole body is sequentially and alternately changed in brightness and darkness. When the whole display panel shows the brightness difference, the display panel is displayed with relatively uniform brightness, so that the problem of image quality color cast caused by visual angle deviation is solved; in addition, the number of the scanning lines and the number of the common electrode lines are reduced by half through the common scanning lines and the first common electrode lines, so that the effective aperture opening ratio of the display panel is increased, the penetration rate is improved, and the cost is reduced.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below, it is obvious that the drawings in the following description are only some embodiments of the present invention, and for those skilled in the art, other drawings can be obtained according to the structures shown in the drawings without creative efforts.
FIG. 1 is a schematic circuit diagram of an embodiment of a plurality of sub-pixel groups in a driving device of a display panel according to the present invention;
FIG. 2 is a flowchart illustrating a driving method of a display panel according to an embodiment of the present invention;
FIG. 3 is a flowchart illustrating a driving method of a display panel according to another embodiment of the present invention;
FIG. 4 is a flowchart illustrating a driving method of a display panel according to another embodiment of the present invention;
FIG. 5 is a flowchart illustrating a driving method of a display panel according to still another embodiment of the present invention;
FIG. 6 is a schematic diagram illustrating the display effect of the display panel according to the embodiment of the invention in the first frame1 and the second frame2 of the current driving period;
FIG. 7 is a schematic diagram illustrating the display effect of the display panel according to the embodiment of the invention in the third frame3 and the fourth frame4 of the current driving period;
FIG. 8 is a timing diagram of an embodiment of first and second frame frames 1 and 2 of the mth row and nth column scan lines in the current driving period based on the display effect of the display panel shown in FIG. 6 and FIG. 7;
FIG. 9 is a timing diagram of the first frame1 and the second frame2 of the m-th row and n + 1-th row of scan lines in the current driving period based on the display effect of the display panel shown in FIG. 6 and FIG. 7;
FIG. 10 is a timing diagram of an embodiment of a third frame3 and a fourth frame4 of the mth row scanning line in the mth column in the current driving period based on the display effect of the display panel shown in FIG. 6 and FIG. 7;
FIG. 11 is a timing diagram of the embodiment of the third frame3 and the fourth frame4 of the m-th row and n + 1-th row of scan lines in the current driving period based on the display effect of the display panel shown in FIG. 6 and FIG. 7;
FIG. 12 is a schematic diagram illustrating display effects of another embodiment of a display panel according to the present invention in the third frame3 and the fourth frame4 of the current driving period;
FIG. 13 is a timing diagram of another embodiment of the m-th row and n-th column of scan lines in the third frame3 and the fourth frame4 of the current driving period based on the display effect of the display panel shown in FIG. 12;
FIG. 14 is a timing diagram of another embodiment of the m column and n +1 row scan lines in the third frame3 and the fourth frame4 of the current driving period based on the display effect of the display panel shown in FIG. 12;
FIG. 15 is a schematic diagram illustrating the display effect of the display panel according to the present invention in the first frame1 and the second frame2 of the current driving period;
FIG. 16 is a schematic diagram illustrating the display effect of the display panel according to the present invention in the third frame3 and the fourth frame4 of the current driving period;
fig. 17 is a schematic diagram illustrating a driving timing relationship corresponding to the mth row scanning line in the mth column based on the display effect of the display panel shown in fig. 15 and 16;
FIG. 18 is a schematic diagram illustrating a driving timing relationship corresponding to the n +1 th row of scanning lines in the m-th column based on the display effect of the display panel shown in FIG. 15 and FIG. 16;
FIG. 19 is a schematic diagram showing another driving timing relationship corresponding to the m-th row and n-th column of scan lines based on the display effect of the display panel shown in FIG. 15 and FIG. 16;
FIG. 20 is a schematic diagram illustrating another driving timing relationship corresponding to the m-th column and n +1 th row of scan lines based on the display effect of the display panel shown in FIG. 15 and FIG. 16;
FIG. 21 is a schematic diagram illustrating another display effect of the display panel according to another embodiment of the present invention in the first frame1 and the second frame2 of the current driving period;
FIG. 22 is a schematic diagram illustrating another driving timing relationship corresponding to the mth row of scanning lines in the mth column based on the display effect of the display panel shown in FIG. 21;
FIG. 23 is a schematic view illustrating another driving timing relationship corresponding to the n +1 th scan line in the m-th column based on the display effect of the display panel shown in FIG. 21;
FIG. 24 is a schematic circuit diagram of a driving apparatus for a display panel according to an embodiment of the present invention;
fig. 25 is a schematic structural diagram of a display panel according to an embodiment of the invention.
The reference numbers illustrate:
| reference numerals | Name (R) | Reference numerals | Name (R) |
| 10 | |
101 | |
| 20 | Source |
110 | |
| 30 | |
120 | |
| 40 | Power management integrated |
130 | |
| 50 | Common |
140 | |
| 100 | |
150 | Frame glue |
The implementation, functional features and advantages of the objects of the present invention will be further explained with reference to the accompanying drawings.
Detailed Description
The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
It should be noted that, if directional indications (such as up, down, left, right, front, and back … …) are involved in the embodiment of the present invention, the directional indications are only used to explain the relative positional relationship between the components, the movement situation, and the like in a specific posture (as shown in the drawing), and if the specific posture is changed, the directional indications are changed accordingly.
In addition, if there is a description of "first", "second", etc. in an embodiment of the present invention, the description of "first", "second", etc. is for descriptive purposes only and is not to be construed as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include at least one such feature. In addition, technical solutions between various embodiments may be combined with each other, but must be realized by a person skilled in the art, and when the technical solutions are contradictory or cannot be realized, such a combination should not be considered to exist, and is not within the protection scope of the present invention.
The term "and/or" herein is merely an association describing an associated object, meaning that three relationships may exist, e.g., a and/or B, may mean: a exists alone, A and B exist simultaneously, and B exists alone. In addition, the character "/" herein generally indicates that the former and latter related objects are in an "or" relationship.
The invention provides a driving method of a display panel, which is suitable for a display device provided with the display panel.
At present, most of large-sized liquid crystal display panels adopt a negative VA (Vertical Alignment) liquid crystal or IPS (In-Plane Switching) liquid crystal technology, the VA liquid crystal technology has the advantages of higher production efficiency and lower manufacturing cost compared with the IPS liquid crystal technology, but the VA liquid crystal technology has the defect of more obvious optical properties compared with the IPS liquid crystal technology, especially the large-sized panels need a larger viewing angle In the aspect of commercial application, and the VA liquid crystal driving causes the contrast of the viewing angle image quality and the color cast to be seriously deteriorated compared with the front-view image quality due to the rapid saturation of the large-viewing angle brightness along with the voltage. The VA-mode liquid crystal technology solves the color shift of the viewing angle by subdividing each RGB sub-pixel into main/sub-pixels, so that the overall brightness of the large viewing angle is closer to the front view with the voltage variation, and this solves the color shift of the viewing angle by spatially providing different driving voltages to the main and sub-pixels, such a pixel design often needs to redesign a metal trace or a TFT element to drive the sub-pixels, which results in the sacrifice of a light-permeable opening area, affects the transmittance of the panel, and easily causes the increase of the backlight cost.
In order to achieve the purpose of compensating color shift without sacrificing the aperture ratio in pixel design, the invention realizes the spatial high-low level adjacent arrangement by adjusting the driving signal, maintains the original brightness signal, can achieve the optical effect that the brightness of a large visual angle is close to a positive visual angle, improves the color shift of the large visual angle, and further achieves the improvement of the color shift of the visual angle while maintaining the panel characteristic of higher penetration rate. And only through the difference of the driving signals, the switching can be realized on the original display without changing the pixel design under the use environment (making high-low level adjacent driving) that the common display (not making high-low level adjacent driving) and the color cast of the visual angle need to be emphasized.
Referring to fig. 1, in an embodiment of the present invention, the display panel includes:
a plurality of pixel groups 101, each pixel group comprises two rows of adjacent sub-pixel groups (101n, 101n ', 101n + 1'), the two rows of adjacent sub-pixel groups (101n, 101n '), (101n +1, 101n + 1') are respectively connected with one scanning line (Gn, Gn +1), each sub-pixel group comprises two sub-pixels, and the two sub-pixels are connected with the same scanning line;
in two sub-pixel groups in adjacent rows, the storage capacitors of two adjacent sub-pixels are connected with the same first common electrode wire, and the storage capacitors of two non-adjacent sub-pixels are correspondingly connected with the other two first common electrode wires one by one;
two data lines which are positioned in the same row and are respectively connected with two adjacent sub-pixel groups are adjacent, and two data lines which are positioned in the adjacent row and are respectively connected with two adjacent sub-pixel groups are adjacent; and the polarities of the voltages on the two adjacent first common electrode lines are opposite.
Wherein the voltage polarity on the first common electrode lines (Vst1, Vst2) respectively connected to the storage capacitances (Cst1, Cst2) of the two rows of the sub-pixels is opposite; the data voltage polarities of the data lines (Dm-1, Dm +1) of the two sub-pixels positioned in the same column in each group are the same, and the voltage polarities of the data lines (Dm-1, Dm +1) of the two sub-pixels positioned in the adjacent columns in the same row are opposite.
In this embodiment, each sub-pixel group 10 shares one scan line, and two adjacent rows of sub-pixels in two adjacent sub-pixel groups share one first common electrode line. The display panel is provided with a pixel array (not shown), a scanning line (Gn, Gn +1), a data line (Dm-1, Dm +1), a first common electrode line Vst1 and a second common electrode line Vcom, wherein the pixel array comprises a plurality of sub-pixels. Each sub-pixel comprises an active switch (thin film transistor), a pixel capacitor Clc and a storage capacitor Cst, wherein the gate of the active switch is electrically connected to the corresponding scan line (Gn, Gn +1) of the sub-pixel, the source of the active switch is electrically connected to the corresponding data line (Dm-1, Dm +1) of the sub-pixel, the drain of the active switch is electrically connected to one end of the pixel capacitor Clc and the storage capacitor Cst of the sub-pixel through the data line (Dm-1, Dm +1), and the other end of each pixel capacitor Clc is electrically connected to the second common electrode line Vcom. In the present embodiment, two rows of sub-pixels are defined as a sub-pixel group 101, and the other ends of the storage capacitors Cst of the two sub-pixel groups 101 are respectively connected to a first common electrode line Vst 1. Each sub-pixel is divided into three sub-pixel groups 101 of red, green and blue. Every three sub-pixels of red, green and blue form a pixel. A plurality of thin film transistors constitute the thin film transistor array of the present embodiment. It should be noted that the number of the scan lines and the number of the data lines may be set according to the size, the resolution, and the like of the display panel, the embodiment of the present invention is described by taking two rows of scan lines and scan lines (Gn, Gn +1) and two columns of data lines (Dm-1, Dm +1) as an example, and the pixel driving of other rows may refer to each embodiment of the present invention, which is not described herein again.
In FIG. 1, Gn and Gn +1 are two adjacent rows of scan lines, Dm-1, Dm and Dm +1 are three adjacent columns of data lines, and n isstVst1、(n+1)stVst2、(n+2)stThree first common electrode lines adjacent to Vst1, Clc1 and Clc2, which represent pixel capacitances connected to the same scan line in the same group, and Cst1 and Cst2, which represent storage capacitances connected to different first common motor lines in the same group, respectively.
Referring to fig. 2, the driving apparatus of the display panel includes a timing controller 10, a source driving circuit 20, a gate driving circuit 30, a power management integrated circuit 40, and a common electrode voltage circuit 50, and thin film transistors located in the same column are connected to the source driving circuit 20 through a data line (Dm-1, Dm +1), and thin film transistors located in two rows in each group are connected to the gate driving circuit 30 through a scan line (Gn, Gn +1), thereby forming a thin film transistor array. These thin film transistors may be a-Si (non-Silicon) thin film transistors or Poly-Si (polysilicon) thin film transistors, which may be formed using LTPS (Low Temperature polysilicon) or the like. The other end of the storage capacitor Cst is connected to the common electrode voltage circuit 50 via a second common electrode line Vcom.
The timing controller 10 receives data signals, control signals and timing signals output from an external control circuit, such as a control system SOC of a television, and converts the data signals, control signals and timing signals into data signals, control signals and timing signals suitable for the gate driving circuit 30 and the source driving circuit 20, the gate driving circuit 30 outputs gate-on signals and gate-off signals according to the timing signals to scan the sub-pixels of each row line by line, and when the thin film transistors in the sub-pixels of the corresponding row are turned on, the source driving circuit 20 outputs the data signals to the corresponding sub-pixels through the data lines (Dm-1, Dm +1), thereby realizing image display of the display panel. The number of the source driving circuits 20 is plural, and the source driving circuits can be specifically set according to the size of the display panel, and the embodiment is described by taking two examples. The output end of the power management integrated circuit 40 is connected with the gate drive circuit 30 and the source drive circuit 20; the power management integrated circuit 40 integrates a plurality of dc-dc conversion circuits of different circuit functions, each of which outputs a different voltage value. The input terminal of the power management integrated circuit 40 inputs a voltage of typically 5V or 12V, and outputs a voltage including an operating voltage DVDD supplied to the timing controller 10 and an operating voltage supplied to the gate driving circuit 30.
Referring to fig. 2, based on the display panel and the driving apparatus of the display panel, the driving method of the display panel includes the steps of:
step S100, controlling the data voltage on each data line to switch the positive polarity and the negative polarity by taking two frames as a driving period;
it is understood that, in the case where the potential of the second common electrode is kept constant, the ac driving of the liquid crystal molecules is realized as if the potential of the liquid crystal capacitor connected to the second common electrode line is constant, and the potential of the other electrode of the liquid crystal capacitor connected to the drain electrode is changed to be higher or lower than the potential of the common electrode reference voltage Vcom on the second common electrode. That is, the data voltage outputted by the source driver is increased or decreased relative to the common electrode reference voltage Vcom, and the polarity of the data voltage in this embodiment is determined by the voltage value of the data voltage and the common electrode reference voltage Vcom: the positive polarity of the data voltage means that the voltage value of the data voltage loaded by the data line is greater than the common electrode reference voltage Vcom on the second common electrode line; the negative polarity driving means that the voltage value of the data voltage loaded on the data line is smaller than the voltage value of the common electrode reference voltage Vcom on the second common electrode line. When the voltage difference between the two is greater than 0, the polarity is positive, generally indicated by a "+" sign; when the voltage difference between the two is less than 0, the polarity is negative, usually indicated by a "-" sign. Therefore, in this embodiment, controlling the data voltage on each data line to switch the positive and negative polarities every two frames may be understood as: when the voltage on the data line has a positive polarity in the first frame and the second frame, the voltage is switched to a negative polarity in the third frame and the fourth frame. In the driving process of taking four frames as one driving period, the data voltage of each sub-pixel is controlled to be changed alternately in high and low levels, so that the same sub-pixel can not maintain the high level or the low level all the time, and the problems that the granular sensation is easily seen and the resolution is reduced in the image quality because the high level or the low level signal is maintained at the same sub-pixel position in space are avoided. Taking four frames as a driving period, it can be understood that the pixel driving process of the current frame is completed, and the switching can be performed to the pixel driving of the next frame, and the pixel driving process of the next frame is also sequentially switched as the driving process of the current frame, until the pixel driving of all frames is completed.
Step S200, controlling the common electrode voltage level on each first common electrode line to perform high-low switching with two frames as one driving period, and the high-low switching sequence of two adjacent driving periods is different.
In this embodiment, one end of the storage capacitor is connected to the thin film transistor through the pixel electrode, and the other end of the storage capacitor is connected to one first common electrode line, that is, the storage capacitor is formed by overlapping the pixel electrode and the second common electrode line. The voltage on the first common electrode line can realize high-low level switching, and can be specifically controlled by a common electrode voltage circuit, and a memory, a digital-to-analog converter, a signal amplifier and the like are usually integrated in the common electrode voltage circuit. In this embodiment, the voltage required to switch between high and low levels in each frame may be stored in the memory, specifically, may be in communication connection with the upper computer through the communication interface and the communication circuit, and stores the common voltage output by the upper computer. When the display device works, the digital-to-analog converter converts the digital common voltage into the analog common voltage, and the analog common voltage is amplified by the signal amplifier and then output to the corresponding first common electrode line, so that the common electrode line is applied with the high-level common electrode voltage or applied with the low-level common electrode voltage.
It is understood that the storage capacitor and the pixel capacitor are electrically connected through the pixel electrode, and parasitic capacitance, such as pixel parasitic capacitance, may exist on each sub-pixel. Therefore, when the common electrode voltage applied to the second common electrode connected to the storage capacitor is changed, the voltage across the storage capacitor is changed. The voltage is coupled among the pixel capacitor, the storage capacitor and the parasitic capacitor, so that the voltage on the pixel electrode connected with the storage capacitor and the pixel capacitor is changed, and under the condition that the common voltage on the first common electrode wire is not changed, the voltage on the pixel electrode is changed, so that the voltages at two ends of the pixel capacitor are changed, and further the brightness of the sub-pixel corresponding to the pixel capacitor is changed.
The switching between high and low of the voltage level of the common electrode on the first common electrode line in a driving period of two frames can be understood as that, in adjacent four frames, in the first frame, the voltage on the first common electrode line is switched from high level to low level, the second frame is switched from low level to high level, the third frame is also switched from low level to high level, and the fourth frame is switched from high level to low level. Or, in the first frame, the voltage on the first common electrode line is switched from low level to high level, the second frame is switched from high level to low level, the third frame is also switched from high level to low level, and the fourth frame is switched from low level to high level.
In the driving method of the display panel, in each sub-pixel group in one frame, because the same column of data voltage has the same polarity and the common electrode voltage on the first common electrode has different levels, the brightness displayed by the two sub-pixels is different. And when four frames are taken as a driving period, positive and negative polarity switching is carried out every two frames by controlling the data voltage on each data line, and the common electrode voltage level on each first common electrode line is controlled in a matching manner, so that high and low switching is carried out by taking two frames as one driving period. The arrangement is such that within the same group, the display luminance of two sub-pixels in the same column is switched between brighter and darker in units of two frames, and the display luminance of two sub-pixels in adjacent columns in one frame is switched between brighter and darker. And the two adjacent sub-pixels in the same row can have darker and brighter changes, and for the complete row, the whole body is sequentially and alternately changed in brightness and darkness. When the whole display panel shows the brightness difference, the display panel is displayed with relatively uniform brightness, so that the problem of image quality color cast caused by visual angle deviation is solved; in addition, the common scanning lines and the first common electrode lines are basically reduced by half, so that the effective aperture opening ratio of the display panel is increased, the penetration rate is improved, the cost is reduced, and the problem of image quality color cast caused by visual angle deviation is solved under the condition of not sacrificing the aperture opening ratio.
In one embodiment, the step of controlling the data voltage on each data line to switch positive and negative polarities every two frames includes:
in this embodiment, the data voltages on the data lines are switched between positive and negative polarities every two frames with four frames as a driving period, and the polarities of the data voltages on two adjacent columns of data lines are opposite, specifically:
the polarity of the data voltage on one data line in the data lines of the two adjacent columns of the sub-pixels in four adjacent frames is positive polarity, negative polarity and negative polarity;
the polarities of the data voltage on the other data line in the data lines of the two adjacent columns of the sub-pixels in four adjacent frames are negative polarity, positive polarity and positive polarity.
In one embodiment, in one driving period, when the data voltage on the data line is switched from a positive voltage to a negative voltage, the common electrode voltage level of one of the two first common electrode lines with opposite polarities is switched from a high level to a low level, and the common electrode voltage level of the other one of the two first common electrode lines is switched from the low level to the high level. When the data voltage on the data line is switched from negative voltage to positive voltage, the voltage level of the common electrode of one of the two first common electrode lines with opposite polarities is switched from low level to high level, and the voltage level of the common electrode of the other one of the two first common electrode lines is switched from high level to low level.
And after the pixel capacitors of the sub-pixels in the corresponding row are charged, controlling the voltage level of the common electrode on the first common electrode line to switch high and low. Specifically, the scanning signal on each scanning line in each frame comprises an on-phase and an off-phase, and when the scanning signal on each scanning line is switched from the on-phase to the off-phase, the common electrode voltage on the first common electrode line is controlled to perform high-low level switching.
In this embodiment, in each frame, the scan signal of each scan line includes an on-phase and an off-phase, in the on-phase, the sub-pixels in the corresponding row are driven to be charged, and after the charging is completed, the gate driving circuit outputs the gate off-signal, so that the sub-pixels are driven to stop charging. In this embodiment, when the scan signal of each scan line is switched from the on-phase to the off-phase, the common electrode voltage on the first common electrode line is controlled to perform high-low level switching or low-high level switching, in the on-phase, that is, when the sub-pixels of the corresponding row are charged, the voltage on the first common electrode line is maintained at the low level (or the high level), and in the off-phase, the voltage on the first common electrode line is switched from the low level to the high level (or the low level).
When the scanning signal of each scanning line is switched from the on phase to the off phase, the step of controlling the common electrode voltage on the first common electrode line to perform high-low level switching comprises:
two rows of sub-pixels in the same group are respectively an nth row of sub-pixels and an n +1 th row of sub-pixels;
in a first frame of adjacent four frames, when the data voltage of the sub-pixels of the nth row and the sub-pixels of the (n +1) th row are positive, controlling the voltage of the common electrode of the sub-pixels of the nth row to be switched from low level to high level, and controlling the voltage of the common electrode of the sub-pixels of the (n +1) th row to be switched from high level to low level;
in a second frame of adjacent four frames, when the data voltage of the sub-pixels of the nth row and the sub-pixels of the (n +1) th row are controlled to be positive, the voltage of the common electrode of the sub-pixels of the nth row is controlled to be switched from high level to low level, and the voltage of the common electrode of the sub-pixels of the (n +1) th row is controlled to be switched from high level to low level;
in a third frame of adjacent four frames, when the data voltage for controlling the sub-pixels of the nth row and the sub-pixels of the (n +1) th row is negative, the voltage of the common electrode of the sub-pixels of the nth row is controlled to be switched from high level to low level in the same way as the second frame, and the voltage of the common electrode of the sub-pixels of the (n +1) th row is controlled to be switched from low level to high level in the same way as the second frame;
in a fourth frame of adjacent four frames, when the data voltage of the sub-pixels of the nth row and the sub-pixels of the (n +1) th row are controlled to be negative polarity, the voltage of the common electrode of the sub-pixels of the nth row is controlled to be switched from low level to high level, and the voltage of the common electrode of the sub-pixels of the (n +1) th row is controlled to be switched from high level to low level.
Or, when the scanning signal of each scanning line is switched from the on-phase to the off-phase, the step of controlling the common electrode voltage on the first common electrode line to perform high-low level switching includes:
two rows of sub-pixels in the same group are respectively an nth row of sub-pixels and an n +1 th row of sub-pixels;
in a first frame of adjacent four frames, when the data voltage of the sub-pixels of the nth row and the sub-pixels of the (n +1) th row are positive, controlling the common electrode voltage of the sub-pixels of the nth row to be switched from high level to low level, and controlling the common electrode voltage of the sub-pixels of the (n +1) th row to be switched from low level to high level;
in a second frame of adjacent four frames, when the data voltage of the sub-pixels of the nth row and the sub-pixels of the (n +1) th row are controlled to be positive, the voltage of the common electrode of the sub-pixels of the nth row is controlled to be switched from low level to high level, and the voltage of the common electrode of the sub-pixels of the (n +1) th row is controlled to be switched from high level to low level;
in a third frame of adjacent four frames, when the data voltage of the sub-pixels of the nth row and the sub-pixels of the (n +1) th row are controlled to be negative, the voltage of the common electrode of the sub-pixels of the nth row is controlled to be switched from high level to low level, and the voltage of the common electrode of the sub-pixels of the (n +1) th row is controlled to be switched from low level to high level;
in a fourth frame of adjacent four frames, when the data voltage of the sub-pixels of the nth row and the sub-pixels of the (n +1) th row are controlled to be negative polarity, the voltage of the common electrode of the sub-pixels of the nth row is controlled to be switched from low level to high level, and the voltage of the common electrode of the sub-pixels of the (n +1) th row is controlled to be switched from high level to low level.
Referring to fig. 1, for convenience of understanding, the principle thereof is described in detail in conjunction with the above-described embodiments. In order to describe the voltage variation and the pixel brightness variation in this embodiment in more detail, the embodiment uses the m-th row data line Dm, the n-th row and the n + 1-th row (G) scan linesn、Gn+1) And three first common electrode wires (n) with opposite polaritiesstVst1、(n+1)stVst2、(n+2)stVst1), the pixel driving of the entire display panel is described with reference to the present embodiment, which is not repeated herein.
Referring to fig. 6 to 11, in the first frame1 of the current driving period, when scanning to the nth row, the nth row scanning line GnStart to operate with the scanning line GnData of connected sub-pixelsLine Datam-nIs positive polarity, i.e. Data voltage Datam-n>Common electrode reference voltage Vcom, and the scan line Gm-nAfter the pixel capacitors of two adjacent rows of sub-pixels are charged, the scanning line GnThe scanning signal of (2) is turned off; referring to the current frame pixel frame1 driving timing, the pixel holding voltage Vp at the sub-pixel connected to the mth column data line Dm and the nth row scanning line Gn is illustratedm-n_1: at this time, the first common electrode line n connected to the sub-pixelstApplied common electrode voltage Vst of Vst1nSwitching from relatively low level to high level, wherein the pixel holding voltage Vp of the sub-pixel is caused by coupling effect among the parasitic capacitance, the storage capacitance and the pixel capacitance due to the parasitic capacitance of the pixelm-n_1The common electrode voltage Vst loaded by the first common electrode linenBy increasing the voltage Δ V, i.e. the pixel holding voltage Vp, from a relatively low level to a high levelm-n_1The voltage difference with the common electrode reference voltage Vcom on the second common electrode line side is changed from x to x + Δ V, and the increase of the positive polarity voltage increases the luminance of the sub-pixel.
Referring to FIGS. 6 to 11, the scan line G is aligned with the scan linenThe pixel holding voltage Vp of another row of connected sub-pixelsm-n_2A first common electrode line (n +1) connected to the sub-pixelstVst2 applied voltage signal Vstn+1Adjacent first common electrode line nstVst1 applied voltage signal VstnIs opposite, the voltage signal Vst loaded by the first common electrode line (n +1) stVst2 isn+1Switching from relatively high level to low level, wherein the pixel has parasitic capacitance, and the coupling effect among the parasitic capacitance, the storage capacitance and the pixel capacitance makes the pixel holding voltage Vp of the sub-pixelm-n_2Will be due to the first common electrode line (n +1)stVst2 applied voltage signal Vstn+1By a decrease Δ V, i.e. the pixel holding voltage Vp, from a relatively high level to a low levelm-n_2The voltage difference between the reference voltage Vcom of the common electrode on the second common electrode line side is changed from x to x- Δ V, and the decrease of the voltage with positive polarity makes the sub-imageThe brightness of the pixel decreases.
Referring to fig. 6 to 11, when progressive scanning is performed to the (n +1) th row, the (n +1) th row scans a line Gn+1Start to operate with the scanning line Gn+1Data lines of connected sub-pixelsm-n+1Is positive polarity, i.e. the Data voltage Datam-n+1>Common electrode reference voltage Vcom, and the scan line Gn+1And after the pixel capacitors of the two rows of connected sub-pixels are charged, the scanning signals are closed. Referring to the current frame pixel frame1 driving timing, the m-th column data line Dm n +1 th row scanning line G is illustratedn+1Pixel holding voltage Vp of connected sub-pixelsm-n+1_1. The sub-pixel and the previous adjacent sub-pixel share a first common electrode line (n +1)stVst2, first common electrode voltage Vstn+1When the voltage level is switched from a relatively high level to a low level, the pixel holding voltage Vp of the sub-pixel is caused by the parasitic capacitance of the pixel and the coupling effect among the parasitic capacitance, the storage capacitance and the pixel capacitancem-n+1_1The voltage signal Vst loaded by the common electrode linen+1By a decrease Δ V, i.e. Vp, from a relatively high level to a low levelm-n+1_1The voltage difference with the common electrode reference voltage Vcom on the second common electrode line side is changed from x to x- Δ V, and the decrease of the positive polarity voltage decreases the luminance of the sub-pixel.
Referring to FIGS. 6 to 11, the scan line G is aligned with the scan linen+1The pixel holding voltage Vp of another row of connected sub-pixelsm-n+1_2A first common electrode line (n +2) connected to the sub-pixelstVst1 applied voltage signal Vstn+2Adjacent first common electrode line (n +1)stVst2 applied voltage signal Vstn+1Is opposite, the first common electrode line (n +2)stVst1 applied voltage signal Vstn+2Switching from relatively low level to high level, wherein the pixel holding voltage Vp of the sub-pixel is caused by coupling effect among the parasitic capacitance, the storage capacitance and the pixel capacitance due to the parasitic capacitance of the pixelm-n+1_2Will be due to the first common electrode line (n +2)stVst1 applied voltage signal Vstn+2By relatively comparingLow level switches to high level and increases by Δ V, i.e., Vpm-n+1_2The voltage difference with the common electrode reference voltage Vcom on the second common electrode line side is changed from x to x + Δ V, and the increase of the positive polarity voltage increases the luminance of the sub-pixel.
Referring to fig. 6 to 11, in the second frame2 of the current driving period, when scanning to the nth row, the nth row scanning line GnStart to operate with the scanning line GnData lines of connected sub-pixelsm-nIs positive polarity, i.e. Data voltage Datam-n>Common electrode reference voltage Vcom, and the scan line Gm-nAfter the pixel capacitors of two adjacent rows of sub-pixels are charged, the scanning line GnThe scanning signal of (2) is off. Referring to the current frame pixel frame2 driving timing, the nth row scanning line G is illustrated as being connected to the mth column data line DmnPixel holding voltage Vp across connected subpixelsm-n_1: at this time, the first common electrode line n connected to the sub-pixelstApplied common electrode voltage Vst of Vst1nSwitching from a relatively high level to a low level. The pixel holding voltage Vpm-n of the sub-pixel is caused by the parasitic capacitance of the pixel and the coupling effect among the parasitic capacitance, the storage capacitance and the pixel capacitance _1 will be due to the first common electrode line nstVst1 applied common electrode voltage VstnBy a decrease Δ V, i.e. the pixel holding voltage Vp, from a relatively high level to a low levelm-n_1The voltage difference with the common electrode reference voltage Vcom on the second common electrode line side is changed from x to x- Δ V, and the decrease of the positive polarity voltage decreases the luminance of the sub-pixel.
Referring to FIGS. 6 to 11, the scan line G is aligned with the scan linem-nThe pixel holding voltage Vp of another row of connected sub-pixelsm-n_2A first common electrode line (n +1) connected to the sub-pixelstVst2 applied voltage signal Vstn+1Adjacent first common electrode line nstVst1 applied voltage signal VstnIs opposite, the first common electrode line (n +1)stVst2 applied voltage signal Vstn+1From a relatively low level to a high level. Due to the fact thatThe pixel has parasitic capacitance, and the pixel holding voltage Vp of the sub-pixel is caused by coupling effect among the parasitic capacitance, the storage capacitance and the pixel capacitancem-n_2Will be due to the first common electrode line (n +1)stVst2 applied voltage signal Vstn+1By an increase of Δ V, i.e. Vp, from a relatively low level to a high levelm-n_2The voltage difference with the common electrode reference voltage Vcom on the second common electrode line side is changed from x to x + Δ V, and the increase of the positive polarity voltage increases the luminance of the sub-pixel.
Referring to fig. 6 to 11, when progressive scanning is performed to the (n +1) th row, the (n +1) th row scans a line Gn+1Start to operate with the scanning line Gn+1Data lines of connected sub-pixelsm-n+1Is positive polarity, i.e. the Data voltage Datam-n+1>Common electrode reference voltage Vcom, and the scan line Gn+1And after the pixel capacitors of the two rows of connected sub-pixels are charged, the scanning signals are closed. Referring to the current frame pixel frame2 driving timing, the m-th column data line Dm n +1 th row scanning line G is illustratedn+1Pixel holding voltage Vp of connected sub-pixelsm-n+1_1: the sub-pixel and the previous adjacent sub-pixel share a first common electrode line (n +1)stVst2, first common electrode voltage Vstn+1Switching from relatively low level to high level, wherein the pixel holding voltage Vp of the sub-pixel is caused by parasitic capacitance of the pixel and coupling effect among the parasitic capacitance, the storage capacitance and the pixel capacitancem-n+1_1Will be due to the first common electrode line (n +1)stVst2 applied voltage signal Vstn+1By an increase of Δ V, i.e. Vp, from a relatively low level to a high levelm-n+1_1The voltage difference with the common electrode reference voltage Vcom on the second common electrode line side is changed from x to x + Δ V, and the increase of the positive polarity voltage increases the luminance of the sub-pixel.
Referring to FIGS. 6 to 11, the scan line G is aligned with the scan linen+1The pixel holding voltage Vp of another row of connected sub-pixelsm-n+1_2A first common electrode line (n +2) connected to the sub-pixelstVst1 applied voltage signal Vstn+2And adjacent first common electrode line(n+1)stVst2 applied voltage signal Vstn+1Is opposite, the first common electrode line (n +2)stVst1 applied voltage signal Vstn+2Switching from relatively high level to low level, wherein the pixel holding voltage Vp of the sub-pixel is generated due to the parasitic capacitance of the pixel and the coupling effect among the parasitic capacitance, the storage capacitance and the pixel capacitancem-n+1_2Will be due to the first common electrode line (n +2)stVst1 applied voltage signal Vstn+2By a decrease Δ V, i.e. Vp, from a relatively high level to a low levelm-n+1_2The voltage difference with the common electrode reference voltage Vcom on the second common electrode line side is changed from x to x- Δ V, and the decrease of the positive polarity voltage decreases the luminance of the sub-pixel.
Referring to fig. 6 to 11, in the third frame3 of the current driving period, when scanning to the nth row, the nth row scanning line GnStart to operate with the scanning line GnData lines of connected sub-pixelsm-nHas a negative polarity, i.e. the Data voltage Datam-n<Common electrode reference voltage Vcom, and the scan line Gm-nAfter the pixel capacitors of two adjacent rows of sub-pixels are charged, the scanning line GmThe scanning signal of (2) is turned off; referring to the current frame pixel frame3 driving timing, the pixel holding voltage Vp at the sub-pixel connected to the mth column data line Dm and the nth row scanning line Gn is illustratedm-n_1: at this time, the first common electrode line n connected to the sub-pixelstApplied common electrode voltage Vst of Vst1nSwitching from relatively low level to high level, wherein the pixel holding voltage Vp of the sub-pixel is caused by parasitic capacitance of the pixel and coupling effect among the parasitic capacitance, the storage capacitance and the pixel capacitancem-n_1Will be caused by the first common electrode line nstVst1 applied common electrode voltage VstnBy an increase Δ V from a relatively high level to a low level, i.e. the pixel holding voltage Vpm-n_1The voltage difference between the common electrode reference voltage Vcom on the second common electrode line side is changed from x to-x + Δ V, and the increase of the negative polarity voltage decreases the luminance of the sub-pixel.
Referring to FIGS. 6 to 11, the scan line G is aligned with the scan linem-nThe pixel holding voltage Vp of another row of connected sub-pixelsm-n_2A first common electrode line (n +1) connected to the sub-pixelstVst2 applied voltage signal Vstn+1Adjacent first common electrode line nstVst1 applied voltage signal Vstm-n_1Is opposite, the first common electrode line (n +1)stThe voltage signal Vstn +1 applied to the Vst2 switches from a relatively high level to a low level, and the pixel holding voltage Vp of the sub-pixel is also due to the parasitic capacitance of the pixel and the coupling effect among the parasitic capacitance, the storage capacitance, and the pixel capacitancem-n_2Will be due to the first common electrode line (n +1)stVst2 applied voltage signal Vstn+1By an increase of Δ V, i.e. Vp, from a relatively low level to a high levelm-n_2The voltage difference between the common electrode reference voltage Vcom on the second common electrode line side is changed from x to-x- Δ V, and the decrease of the negative polarity voltage increases the brightness of the sub-pixel.
Referring to fig. 6 to 11, when progressive scanning is performed to the (n +1) th row, the (n +1) th row scans a line Gn+1Start to operate with the scanning line Gn+1Data lines of connected sub-pixelsm-nIs a negative polarity, i.e. the Data voltage Datam-n<Common electrode reference voltage Vcom, and the scan line Gn+1After the pixel capacitors of the two rows of connected sub-pixels are charged, the scanning signal is turned off, and the pixel holding voltage Vp of the sub-pixel connected with the n +1 th row of scanning line Gn +1 of the m column data line Dm is described by referring to the current frame pixel frame3 driving time sequencem-n+1_1The sub-pixel and the previous adjacent sub-pixel share a first common electrode line (n +1)stVst2, first common electrode voltage Vstn+1When the voltage level is switched from a relatively high level to a low level, the pixel holding voltage Vp of the sub-pixel is caused by the parasitic capacitance of the pixel and the coupling effect among the parasitic capacitance, the storage capacitance and the pixel capacitancem-n+1_1The voltage signal Vst loaded by the common electrode linen+1By a decrease Δ V, i.e. Vp, from a relatively high level to a low levelm-n+1_1The voltage difference between the common electrode reference voltage Vcom on the second common electrode line side is changed from-x to-x- Δ V, and the decrease of the negative polarity voltage increases the brightness of the sub-pixel.
Referring to FIGS. 6 to 11, the scan line G is aligned with the scan linen+1The pixel holding voltage Vp of another row of connected sub-pixelsm-n+1_2A first common electrode line (n +2) connected to the sub-pixelstVst1 applied voltage signal Vstn+2Adjacent first common electrode line (n +1)stVst2 applied voltage signal Vstn+1Is opposite, the first common electrode line (n +2)stVst1 applied voltage signal Vstn+2Switching from relatively low level to high level, wherein the pixel holding voltage Vp of the sub-pixel is generated due to the parasitic capacitance of the pixel and the coupling effect among the parasitic capacitance, the storage capacitance and the pixel capacitancem-n+1_2Will be due to the first common electrode line (n +2)stVst1 applied voltage signal Vstn+2By an increase of Δ V, i.e. Vp, from a relatively low level to a high levelm-n+1_2The voltage difference between the common electrode reference voltage Vcom on the second common electrode line side is changed from-x to-x + Δ V, and the increase of the negative polarity voltage decreases the luminance of the sub-pixel.
Referring to fig. 6 to 11, in the fourth frame4 of the current driving period, when scanning to the nth row, the nth row scanning line GnStart to operate with the scanning line GnData lines of connected sub-pixelsm-nHas a negative polarity, i.e. the Data voltage Datam-n<Common electrode reference voltage Vcom, and the scan line GnAfter the pixel capacitors of two adjacent rows of sub-pixels are charged, the scanning line GmThe scanning signal of (2) is turned off; referring to the current frame pixel frame4 driving timing, the pixel holding voltage Vp at the sub-pixel connected to the mth column data line Dm and the nth row scanning line Gn is illustratedm-n_1: at this time, the first common electrode line n connected to the sub-pixelstApplied common electrode voltage Vst of Vst1nSwitching from relatively high level to low level, wherein the pixel has parasitic capacitance, and the parasitic capacitance, the storage capacitance, and the pixel capacitance are coupledThe resultant effect is that the pixel holding voltage Vp of the sub-pixelm-n_1Will be caused by the first common electrode line nstVst1 applied common electrode voltage VstnBy increasing the voltage Δ V, i.e. the pixel holding voltage Vp, from a relatively high level to a low levelm-n_1The voltage difference between the common electrode reference voltage Vcom on the second common electrode line side is changed from-x to-x- Δ V, and the decrease of the negative polarity voltage increases the brightness of the sub-pixel.
Referring to FIGS. 6 to 11, the scan line G is aligned with the scan linem-nThe pixel holding voltage Vp of another row of connected sub-pixelsm-n_2A first common electrode line (n +1) connected to the sub-pixelstVst2 applied voltage signal Vstn+1Adjacent first common electrode line nstVst1 applied voltage signal VstnIs opposite, the voltage signal Vst loaded by the first common electrode line (n +1) stVst2 isn+1Switching from relatively high level to low level, wherein the pixel has parasitic capacitance, and the coupling effect among the parasitic capacitance, the storage capacitance and the pixel capacitance makes the pixel holding voltage Vp of the sub-pixelm-n_2Will be due to the first common electrode line (n +1)stVst2 applied voltage signal Vstn+1By a decrease Δ V, i.e. Vp, from a relatively high level to a low levelm-n_2The voltage difference between the common electrode reference voltage Vcom on the second common electrode line side is changed from-x to-x- Δ V, and the decrease of the negative polarity voltage increases the brightness of the sub-pixel.
Referring to fig. 6 to 11, when progressive scanning is performed to the (n +1) th row, the (n +1) th row scans a line Gn+1Start to operate with the scanning line Gn+1Data lines of connected sub-pixelsm-n+1Is a negative polarity, i.e. the Data voltage Datam-n+1<Common electrode reference voltage Vcom, and the scan line Gn+1And after the pixel capacitors of the two rows of connected sub-pixels are charged, the scanning signals are closed. Referring to the current frame pixel frame4 driving timing, the pixel holding voltage Vp of the sub-pixel connected to the mth column data line Dm, the n +1 th row scanning line Gn +1 is illustratedm-n+1_1: at this time, the sub-pixel and the previous adjacent sub-pixel share oneFirst common electrode line strip (n +1)stVst2, first common electrode voltage Vstn+1From a relatively low level to a high level. The pixel holding voltage Vp of the sub-pixel is caused by the parasitic capacitance of the pixel and the coupling effect among the parasitic capacitance, the storage capacitance and the pixel capacitancem-n+1_1Will be due to the first common electrode line (n +1)stVst2 applied voltage signal Vstn+1By increasing Δ V, i.e. Vp, from a relatively low level to a high levelm-n+1_1The voltage difference between the common electrode reference voltage Vcom on the second common electrode line side is changed from-x to-x + Δ V, and the increase of the negative polarity voltage decreases the luminance of the sub-pixel.
Referring to FIGS. 6 to 11, the scan line G is aligned with the scan linen+1The pixel holding voltage Vp of another row of connected sub-pixelsm-n+1_2A first common electrode line (n +2) connected to the sub-pixelstVst1 applied voltage signal Vstn+2Adjacent first common electrode line (n +1)stVst2 applied voltage signal Vstn+1Is opposite to the polarity of the common electrode line, the voltage signal Vst loaded by the common electrode linem-n+1_2Switching from relatively high level to low level, wherein the pixel holding voltage Vp of the sub-pixel is caused by coupling effect among the parasitic capacitance, the storage capacitance and the pixel capacitance due to the parasitic capacitance of the pixelm-n+1_2Will be due to the first common electrode line (n +2)stVst1 applied voltage signal Vstn+2By a decrease Δ V, i.e. Vp, from a relatively high level to a low levelm-n+1_2The voltage difference between the common electrode reference voltage Vcom on the second common electrode line side is changed from-x to-x- Δ V, and the decrease of the negative polarity voltage increases the brightness of the sub-pixel.
Referring to fig. 3, in an embodiment, in step S300, in the step of controlling the common electrode voltage level on each of the first common electrode lines to perform high-low switching in one driving period of two frames, the high-low switching sequence of two adjacent driving periods is different.
In this embodiment, the common electrode voltage level on the first common electrode line is switched between high level and low level in a first frame, a second frame is switched between low level and high level, a third frame is also switched between low level and high level, and a fourth frame is switched between high level and low level. Or, in the first frame, the voltage on the first common electrode line is switched from low level to high level, the second frame is switched from high level to low level, the third frame is also switched from high level to low level, and the fourth frame is switched from low level to high level.
When the scanning signal of each scanning line is switched from the on phase to the off phase, the step of controlling the common electrode voltage on the first common electrode line to perform high-low level switching comprises:
two rows of sub-pixels in the same group are respectively an nth row of sub-pixels and an n +1 th row of sub-pixels;
in a first frame of adjacent four frames, when the data voltage of the sub-pixels of the nth row and the sub-pixels of the (n +1) th row are positive, controlling the voltage of the common electrode of the sub-pixels of the nth row to be switched from low level to high level, and controlling the voltage of the common electrode of the sub-pixels of the (n +1) th row to be switched from high level to low level;
in a second frame of adjacent four frames, when the data voltage of the sub-pixels of the nth row and the sub-pixels of the (n +1) th row are controlled to be positive, the voltage of the common electrode of the sub-pixels of the nth row is controlled to be switched from high level to low level, and the voltage of the common electrode of the sub-pixels of the (n +1) th row is controlled to be switched from low level to high level;
in a third frame of adjacent four frames, when the data voltage for controlling the sub-pixels of the nth row and the sub-pixels of the (n +1) th row is negative, the voltage of the common electrode of the sub-pixels of the nth row is controlled to be switched from high level to low level in the same way as the second frame, and the voltage of the common electrode of the sub-pixels of the (n +1) th row is controlled to be switched from low level to high level in the same way as the second frame;
in a fourth frame of adjacent four frames, when the data voltage of the sub-pixels of the nth row and the sub-pixels of the (n +1) th row are controlled to be negative polarity, the voltage of the common electrode of the sub-pixels of the nth row is controlled to be switched from low level to high level, and the voltage of the common electrode of the sub-pixels of the (n +1) th row is controlled to be switched from high level to low level.
Or, when the scanning signal of each scanning line is switched from the on-phase to the off-phase, the step of controlling the common electrode voltage on the first common electrode line to perform high-low level switching includes:
two rows of sub-pixels in the same group are respectively an nth row of sub-pixels and an n +1 th row of sub-pixels;
in a first frame of adjacent four frames, when the data voltage of the sub-pixels of the nth row and the sub-pixels of the (n +1) th row are positive, controlling the common electrode voltage of the sub-pixels of the nth row to be switched from high level to low level, and controlling the common electrode voltage of the sub-pixels of the (n +1) th row to be switched from low level to high level;
in a second frame of adjacent four frames, when the data voltage of the sub-pixels of the nth row and the sub-pixels of the (n +1) th row are controlled to be positive, the voltage of the common electrode of the sub-pixels of the nth row is controlled to be switched from low level to high level, and the voltage of the common electrode of the sub-pixels of the (n +1) th row is controlled to be switched from high level to low level;
in a third frame of adjacent four frames, when the data voltage for controlling the sub-pixels of the nth row and the sub-pixels of the (n +1) th row is negative, the voltage of the common electrode of the sub-pixels of the nth row is controlled to be switched from low level to high level in the same way as the second frame, and the voltage of the common electrode of the sub-pixels of the (n +1) th row is controlled to be switched from high level to low level in the same way as the second frame;
in a fourth frame of adjacent four frames, when the data voltage of the sub-pixels of the nth row and the sub-pixels of the (n +1) th row are controlled to be negative polarity, the voltage of the common electrode of the sub-pixels of the nth row is controlled to be switched from high level to low level, and the voltage of the common electrode of the sub-pixels of the (n +1) th row is controlled to be switched from low level to high level. It is understood that the third frame3 is the same as the second frame2, and the fourth frame4 is the same as the first frame1 at the time of the high-low switching. The driving method of the first frame1 and the second frame2 can refer to the above embodiments, and the third frame3 and the fourth frame4 are taken as examples in this embodiment. Referring to fig. 12 and 14, in the third frame3 of the current driving period, when scanning to the nth row, the nth row scanning line GnStart to operate with the scanning line GnData lines of connected sub-pixelsm-nHas a negative polarity, i.e. the Data voltage Datam-n<Common electrode reference voltage Vcom, and the scan line Gm-nAfter the pixel capacitors of two adjacent rows of sub-pixels are charged, the scanning line GnThe scanning signal of (2) is turned off; referring to the current frame pixel frame3 driving timing, the pixel holding voltage Vp at the sub-pixel connected to the mth column data line Dm and the nth row scanning line Gn is illustratedm-n_1: at this time, the first common electrode line n connected to the sub-pixelstApplied common electrode voltage Vst of Vst1nWhen the voltage level is switched from a relatively high level to a low level, the pixel holding voltage Vp of the sub-pixel is caused by the parasitic capacitance of the pixel and the coupling effect among the parasitic capacitance, the storage capacitance and the pixel capacitancem-n_1Will be caused by the first common electrode line nstVst1 applied common electrode voltage VstnBy a decrease Δ V, i.e. the pixel holding voltage Vp, from a relatively high level to a low levelm-n_1The voltage difference between the common electrode reference voltage Vcom on the second common electrode line side is changed from-x to-x- Δ V, and the decrease of the negative polarity voltage increases the brightness of the sub-pixel.
Referring to fig. 12 and 14, the scanning line GnThe pixel holding voltage Vp of another row of connected sub-pixelsm-n_2A first common electrode line (n +1) connected to the sub-pixelstVst2 applied voltage signal Vstn+1Adjacent first common electrode line nstVst1 applied voltage signal Vstm-n_1When the polarities of the voltage signals Vstn +1 loaded on the first common electrode line (n +1) stVst2 are opposite, the voltage signal Vstn +1 is switched from a relatively low level to a high level, and at this time, due to the parasitic capacitance of the pixel, and due to the coupling effect among the parasitic capacitance, the storage capacitance and the pixel capacitance, the pixel holding voltage Vp of the sub-pixel is maintainedm-n_2Will be due to the first common electrode line (n +1)stVst2 applied voltage signal Vstn+1By an increase of Δ V, i.e. Vp, from a relatively low level to a high levelm-n_2Common electrode reference electrode on the line side of the second common electrodeThe voltage difference between the voltages Vcom changes from x to-x + Δ V, and the increase of the negative polarity voltage decreases the brightness of the sub-pixel.
Referring to fig. 12 and 14, when progressive scanning is performed to the (n +1) th row, the (n +1) th row scans a line Gn+1Start to operate with the scanning line Gn+1Data lines of connected sub-pixelsm-nIs a negative polarity, i.e. the Data voltage Datam-n<Common electrode reference voltage Vcom, and the scan line Gn+1After the pixel capacitors of the two rows of connected sub-pixels are charged, the scanning signal is turned off, and the pixel holding voltage Vp of the sub-pixel connected with the n +1 th row of scanning line Gn +1 of the m column data line Dm is described by referring to the current frame pixel frame3 driving time sequencem-n+1_1The sub-pixel and the previous adjacent sub-pixel share a first common electrode line (n +1)stVst2, first common electrode voltage Vstn+1Switching from relatively low level to high level, wherein the pixel holding voltage Vp of the sub-pixel is caused by parasitic capacitance of the pixel and coupling effect among the parasitic capacitance, the storage capacitance and the pixel capacitancem-n+1_1The voltage signal Vst loaded by the common electrode linen+1By an increase of Δ V, i.e. Vp, from a relatively low level to a high levelm-n+1_1The voltage difference between the common electrode reference voltage Vcom on the second common electrode line side is changed from-x to-x + Δ V, and the increase of the negative polarity voltage decreases the luminance of the sub-pixel.
Referring to fig. 12 and 14, the scanning line Gn+1The pixel holding voltage Vp of another row of connected sub-pixelsm-n+1_2A first common electrode line (n +2) connected to the sub-pixelstVst1 applied voltage signal Vstn+2Adjacent first common electrode line (n +1)stVst2 applied voltage signal Vstn+1Is opposite, the first common electrode line (n +2)stVst1 applied voltage signal Vstn+2Switching from relatively high level to low level, wherein the pixel holding voltage Vp of the sub-pixel is generated due to the parasitic capacitance of the pixel and the coupling effect among the parasitic capacitance, the storage capacitance and the pixel capacitancem-n+1_2Will be caused by the first common electrode line (n +2))stVst1 applied voltage signal Vstn+2By a decrease Δ V, i.e. Vp, from a relatively high level to a low levelm-n+1_2The voltage difference between the common electrode reference voltage Vcom on the second common electrode line side is changed from-x to-x- Δ V, and the decrease of the negative polarity voltage increases the brightness of the sub-pixel.
Referring to fig. 12 and 14, in the fourth frame4 of the current driving period, when scanning to the nth row, the nth row scanning line GnStart to operate with the scanning line GnData lines of connected sub-pixelsm-nHas a negative polarity, i.e. the Data voltage Datam-n<Common electrode reference voltage Vcom, and the scan line GnAfter the pixel capacitors of two adjacent rows of sub-pixels are charged, the scanning line GmThe scanning signal of (2) is turned off; referring to the current frame pixel frame4 driving timing, the pixel holding voltage Vp at the sub-pixel connected to the mth column data line Dm and the nth row scanning line Gn is illustratedm-n_1: at this time, the first common electrode line n connected to the sub-pixelstApplied common electrode voltage Vst of Vst1nSwitching from relatively low level to high level, wherein the pixel holding voltage Vp of the sub-pixel is caused by coupling effect among the parasitic capacitance, the storage capacitance and the pixel capacitance due to the parasitic capacitance of the pixelm-n_1Will be caused by the first common electrode line nstVst1 applied common electrode voltage VstnBy increasing the voltage Δ V, i.e. the pixel holding voltage Vp, from a relatively low level to a high levelm-n_1The voltage difference between the common electrode reference voltage Vcom on the second common electrode line side is changed from-x to-x + Δ V, and the increase of the negative polarity voltage decreases the luminance of the sub-pixel.
Referring to fig. 12 and 14, the scanning line GnThe pixel holding voltage Vp of another row of connected sub-pixelsm-n_2A first common electrode line (n +1) connected to the sub-pixelstVst2 applied voltage signal Vstn+1Adjacent first common electrode line nstVst1 applied voltage signal VstnIs opposite, the voltage signal Vst loaded by the first common electrode line (n +1) stVst2 isn+1Switching from relatively high level to low level, wherein the pixel has parasitic capacitance, and the coupling effect among the parasitic capacitance, the storage capacitance and the pixel capacitance makes the pixel holding voltage Vp of the sub-pixelm-n_2Will be due to the first common electrode line (n +1)stVst2 applied voltage signal Vstn+1By a decrease Δ V, i.e. Vp, from a relatively high level to a low levelm-n_2The voltage difference between the common electrode reference voltage Vcom on the second common electrode line side is changed from x to-x- Δ V, and the decrease of the negative polarity voltage increases the brightness of the sub-pixel.
Referring to fig. 12 and 14, when progressive scanning is performed to the (n +1) th row, the (n +1) th row scans a line Gn+1Start to operate with the scanning line Gn+1Data lines of connected sub-pixelsm-n+1Is a negative polarity, i.e. the Data voltage Datam-n+1<Common electrode reference voltage Vcom, and the scan line Gn+1And after the pixel capacitors of the two rows of connected sub-pixels are charged, the scanning signals are closed. Referring to the current frame pixel frame1 driving timing, the pixel holding voltage Vp of the sub-pixel connected to the mth column data line Dm, the n +1 th row scanning line Gn +1 is illustratedm-n+1_1: at this time, the sub-pixel shares a first common electrode line (n +1) with the previous adjacent sub-pixelstVst2, first common electrode voltage Vstn+1Switching from a relatively high level to a low level. The pixel holding voltage Vp of the sub-pixel is caused by the parasitic capacitance of the pixel and the coupling effect among the parasitic capacitance, the storage capacitance and the pixel capacitancem-n+1_1Will be due to the first common electrode line (n +1)stVst2 applied voltage signal Vstn+1By a decrease Δ V, i.e. Vp, from a relatively high level to a low levelm-n+1_1The voltage difference between the common electrode reference voltage Vcom on the second common electrode line side is changed from-x to-x- Δ V, and the decrease of the negative polarity voltage increases the brightness of the sub-pixel.
Referring to fig. 12 and 14, the scanning line Gn+1The pixel holding voltage Vp of another row of connected sub-pixelsm-n+1_2A first common electrode line (n +2) connected to the sub-pixelstVst1Voltage signal Vst of loadn+2Adjacent first common electrode line (n +1)stVst2 applied voltage signal Vstn+1Is opposite to the polarity of the common electrode line, the voltage signal Vst loaded by the common electrode linem-n+1_2Switching from relatively low level to high level, wherein the pixel holding voltage Vp of the sub-pixel is caused by coupling effect among the parasitic capacitance, the storage capacitance and the pixel capacitance due to the parasitic capacitance of the pixelm-n+1_2Will be due to the first common electrode line (n +2)stVst1 applied voltage signal Vstn+2By an increase of Δ V, i.e. Vp, from a relatively low level to a high levelm-n+1_2The voltage difference between the common electrode reference voltage Vcom on the second common electrode line side is changed from-x to-x + Δ V, and the increase of the negative polarity voltage decreases the luminance of the sub-pixel.
Referring to fig. 4, in an embodiment, in step S400, in controlling the data voltages on the data lines to switch positive and negative polarities every two frames, the data voltages on the data lines of two adjacent groups of the sub-pixel groups are controlled to switch positive and negative polarities in the same frame.
In the same frame, the scanning mode of the gate driving circuit to the display panel is usually progressive scanning to complete the pixel scanning of the sub-pixels of all rows, and when the sub-pixels of the current row are scanned, the pixel capacitance of each sub-pixel is charged. In this embodiment, the polarities of the data voltages of the two rows of sub-pixels in the current group are opposite to the polarities of the data voltages of the two rows of sub-pixels in the previous group and the data voltages of the two rows of sub-pixels in the next group. For example, when the polarity of the data voltage of the two rows of sub-pixels of the previous group is positive (or negative), the data voltage of the two rows of sub-pixels of the next group is switched to negative (or positive) when the two rows of sub-pixels of the next group connected to the same data line are scanned.
Referring to fig. 15 and 20, in the first frame1 of the current driving period, when scanning to the nth row, the nth row scanning line GnStart to operate with the scanning line GnData lines of connected sub-pixelsm-nIs positive polarity, i.e. Data voltage Datam-n>Common electricityA polar reference voltage Vcom, and the scan lines Gm-nAfter the pixel capacitors of two adjacent rows of sub-pixels are charged, the scanning line GnThe scanning signal of (2) is turned off; referring to the current frame pixel frame1 driving timing, the pixel holding voltage Vp at the sub-pixel connected to the mth column data line Dm and the nth row scanning line Gn is illustratedm-n_1: at this time, the first common electrode line n connected to the sub-pixelstApplied common electrode voltage Vst of Vst1nSwitching from relatively low level to high level, wherein the pixel holding voltage Vp of the sub-pixel is caused by coupling effect among the parasitic capacitance, the storage capacitance and the pixel capacitance due to the parasitic capacitance of the pixelm-n_1The common electrode voltage Vst loaded by the first common electrode linenBy increasing the voltage Δ V, i.e. the pixel holding voltage Vp, from a relatively low level to a high levelm-n_1The voltage difference with the common electrode reference voltage Vcom on the second common electrode line side is changed from x to x + Δ V, and the increase of the positive polarity voltage increases the luminance of the sub-pixel.
Referring to fig. 15 and 20, the scanning line GnThe pixel holding voltage Vp of another row of connected sub-pixelsm-n_2A first common electrode line (n +1) connected to the sub-pixelstVst2 applied voltage signal Vstn+1Adjacent first common electrode line nstVst1 applied voltage signal VstnIs opposite, the voltage signal Vst loaded by the first common electrode line (n +1) stVst2 isn+1Switching from relatively high level to low level, wherein the pixel has parasitic capacitance, and the coupling effect among the parasitic capacitance, the storage capacitance and the pixel capacitance makes the pixel holding voltage Vp of the sub-pixelm-n_2Will be due to the first common electrode line (n +1)stVst2 applied voltage signal Vstn+1By a decrease Δ V, i.e. the pixel holding voltage Vp, from a relatively high level to a low levelm-n_2The voltage difference with the common electrode reference voltage Vcom on the second common electrode line side is changed from x to x- Δ V, and the decrease of the positive polarity voltage decreases the luminance of the sub-pixel.
Referring to fig. 15 and 20, the rows are arranged one after anotherWhen scanning to the (n +1) th row, the (n +1) th row scans the line Gn+1Start to operate with the scanning line Gn+1Data lines of connected sub-pixelsm-n+1Is a negative polarity, i.e. the Data voltage Datam-n+1<Common electrode reference voltage Vcom, and the scan line Gn+1And after the pixel capacitors of the two rows of connected sub-pixels are charged, the scanning signals are closed. Referring to the current frame pixel frame1 driving timing, the m-th column data line Dm n +1 th row scanning line G is illustratedn+1Pixel holding voltage Vp of connected sub-pixelsm-n+1_1. The sub-pixel and the previous adjacent sub-pixel share a first common electrode line (n +1)stVst2, first common electrode voltage Vstn+1When the voltage level is switched from a relatively high level to a low level, the pixel holding voltage Vp of the sub-pixel is caused by the parasitic capacitance of the pixel and the coupling effect among the parasitic capacitance, the storage capacitance and the pixel capacitancem-n+1_1The voltage signal Vst loaded by the common electrode linen+1By a decrease Δ V, i.e. Vp, from a relatively high level to a low levelm-n+1_1The voltage difference between the common electrode reference voltage Vcom on the second common electrode line side is changed from-x to-x- Δ V, and the decrease of the negative polarity voltage increases the brightness of the sub-pixel.
Referring to fig. 15 and 20, the scanning line Gn+1The pixel holding voltage Vp of another row of connected sub-pixelsm-n+1_2A first common electrode line (n +2) connected to the sub-pixelstVst1 applied voltage signal Vstn+2Adjacent first common electrode line (n +1)stVst2 applied voltage signal Vstn+1Is opposite, the first common electrode line (n +2)stVst1 applied voltage signal Vstn+2Switching from relatively low level to high level, wherein the pixel holding voltage Vp of the sub-pixel is caused by coupling effect among the parasitic capacitance, the storage capacitance and the pixel capacitance due to the parasitic capacitance of the pixelm-n+1_2Will be due to the first common electrode line (n +2)stVst1 applied voltage signal Vstn+2By an increase of Δ V, i.e. Vp, from a relatively low level to a high levelm-n+1_2And a secondThe voltage difference between the common electrode reference voltage Vcom on the common electrode line side changes from-x to-x + Δ V, and the increase in the negative polarity voltage decreases the luminance of the sub-pixel.
Referring to fig. 15 and 20, in the second frame2 of the current driving period, when scanning to the nth row, the nth row scanning line GnStart to operate with the scanning line GnData lines of connected sub-pixelsm-nIs positive polarity, i.e. Data voltage Datam-n>Common electrode reference voltage Vcom, and the scan line Gm-nAfter the pixel capacitors of two adjacent rows of sub-pixels are charged, the scanning line GnThe scanning signal of (2) is off. Referring to the current frame pixel frame2 driving timing, the nth row scanning line G is illustrated as being connected to the mth column data line DmnPixel holding voltage Vp across connected subpixelsm-n_1: at this time, the first common electrode line n connected to the sub-pixelstApplied common electrode voltage Vst of Vst1nSwitching from a relatively high level to a low level. The pixel holding voltage Vpm-n of the sub-pixel is caused by the parasitic capacitance of the pixel and the coupling effect among the parasitic capacitance, the storage capacitance and the pixel capacitance _1 will be due to the first common electrode line nstVst1 applied common electrode voltage VstnBy a decrease Δ V, i.e. the pixel holding voltage Vp, from a relatively high level to a low levelm-n_1The voltage difference with the common electrode reference voltage Vcom on the second common electrode line side is changed from x to x- Δ V, and the decrease of the positive polarity voltage decreases the luminance of the sub-pixel.
Referring to fig. 15 and 20, the scanning line Gm-nThe pixel holding voltage Vp of another row of connected sub-pixelsm-n_2A first common electrode line (n +1) connected to the sub-pixelstVst2 applied voltage signal Vstn+1Adjacent first common electrode line nstVst1 applied voltage signal VstnIs opposite, the first common electrode line (n +1)stVst2 applied voltage signal Vstn+1From a relatively low level to a high level. The parasitic capacitance of the pixel, and the parasitic capacitance, the storage capacitance, and the pixel capacitanceDue to coupling effect, the pixel holding voltage Vp of the sub-pixelm-n_2Will be due to the first common electrode line (n +1)stVst2 applied voltage signal Vstn+1By an increase of Δ V, i.e. Vp, from a relatively low level to a high levelm-n_2The voltage difference with the common electrode reference voltage Vcom on the second common electrode line side is changed from x to x + Δ V, and the increase of the positive polarity voltage increases the luminance of the sub-pixel.
Referring to fig. 15 and 20, when progressive scanning is performed to the (n +1) th row, the (n +1) th row scans a line Gn+1Start to operate with the scanning line Gn+1Data lines of connected sub-pixelsm-n+1Is a negative polarity, i.e. the Data voltage Datam-n+1<Common electrode reference voltage Vcom, and the scan line Gn+1And after the pixel capacitors of the two rows of connected sub-pixels are charged, the scanning signals are closed. Referring to the current frame pixel frame2 driving timing, the m-th column data line Dm n +1 th row scanning line G is illustratedn+1Pixel holding voltage Vp of connected sub-pixelsm-n+1_1: the sub-pixel and the previous adjacent sub-pixel share a first common electrode line (n +1)stVst2, first common electrode voltage Vstn+1Switching from relatively low level to high level, wherein the pixel holding voltage Vp of the sub-pixel is caused by parasitic capacitance of the pixel and coupling effect among the parasitic capacitance, the storage capacitance and the pixel capacitancem-n+1_1Will be due to the first common electrode line (n +1)stVst2 applied voltage signal Vstn+1By an increase of Δ V, i.e. Vp, from a relatively low level to a high levelm-n+1_1The voltage difference between the common electrode reference voltage Vcom on the second common electrode line side is changed from x to-x + Δ V, and the increase of the negative polarity voltage decreases the luminance of the sub-pixel.
Referring to fig. 15 and 20, the scanning line Gn+1The pixel holding voltage Vp of another row of connected sub-pixelsm-n+1_2A first common electrode line (n +2) connected to the sub-pixelstVst1 applied voltage signal Vstn+2Adjacent first common electrode line (n +1)stVst2 applied voltage signal Vstn+1Polar phase ofOn the contrary, the first common electrode line (n +2)stVst1 applied voltage signal Vstn+2Switching from relatively high level to low level, wherein the pixel holding voltage Vp of the sub-pixel is generated due to the parasitic capacitance of the pixel and the coupling effect among the parasitic capacitance, the storage capacitance and the pixel capacitancem-n+1_2Will be due to the first common electrode line (n +2)stVst1 applied voltage signal Vstn+2By a decrease Δ V, i.e. Vp, from a relatively high level to a low levelm-n+1_2The voltage difference between the common electrode reference voltage Vcom on the second common electrode line side is changed from x to-x- Δ V, and the decrease of the negative polarity voltage increases the brightness of the sub-pixel.
Referring to fig. 15 and 20, in the third frame3 of the current driving period, when scanning to the nth row, the nth row scanning line GnStart to operate with the scanning line GnData lines of connected sub-pixelsm-nHas a negative polarity, i.e. the Data voltage Datam-n<Common electrode reference voltage Vcom, and the scan line Gm-nAfter the pixel capacitors of two adjacent rows of sub-pixels are charged, the scanning line GmThe scanning signal of (2) is turned off; referring to the current frame pixel frame3 driving timing, the pixel holding voltage Vp at the sub-pixel connected to the mth column data line Dm and the nth row scanning line Gn is illustratedm-n_1: at this time, the first common electrode line n connected to the sub-pixelstApplied common electrode voltage Vst of Vst1nSwitching from relatively low level to high level, wherein the pixel holding voltage Vp of the sub-pixel is caused by parasitic capacitance of the pixel and coupling effect among the parasitic capacitance, the storage capacitance and the pixel capacitancem-n_1Will be caused by the first common electrode line nstVst1 applied common electrode voltage VstnBy an increase Δ V from a relatively high level to a low level, i.e. the pixel holding voltage Vpm-n_1The voltage difference between the common electrode reference voltage Vcom on the second common electrode line side is changed from x to-x + Δ V, and the increase of the negative polarity voltage decreases the luminance of the sub-pixel.
Referring to fig. 15 and 20, the scanning line Gm-nAnother one connected toPixel holding voltage Vp of row sub-pixelsm-n_2A first common electrode line (n +1) connected to the sub-pixelstVst2 applied voltage signal Vstn+1Adjacent first common electrode line nstVst1 applied voltage signal Vstm-n_1Is opposite, the first common electrode line (n +1)stThe voltage signal Vstn +1 applied to the Vst2 switches from a relatively high level to a low level, and the pixel holding voltage Vp of the sub-pixel is also due to the parasitic capacitance of the pixel and the coupling effect among the parasitic capacitance, the storage capacitance, and the pixel capacitancem-n_2Will be due to the first common electrode line (n +1)stVst2 applied voltage signal Vstn+1By an increase of Δ V, i.e. Vp, from a relatively low level to a high levelm-n_2The voltage difference between the common electrode reference voltage Vcom on the second common electrode line side is changed from x to-x- Δ V, and the decrease of the negative polarity voltage increases the brightness of the sub-pixel.
Referring to fig. 15 and 20, when progressive scanning is performed to the (n +1) th row, the (n +1) th row scans a line Gn+1Start to operate with the scanning line Gn+1Data lines of connected sub-pixelsm-nIs a negative polarity, i.e. the Data voltage Datam-n>Common electrode reference voltage Vcom, and the scan line Gn+1After the pixel capacitors of the two rows of connected sub-pixels are charged, the scanning signal is turned off, and the pixel holding voltage Vp of the sub-pixel connected with the n +1 th row of scanning line Gn +1 of the m column data line Dm is described by referring to the current frame pixel frame3 driving time sequencem-n+1_1The sub-pixel and the previous adjacent sub-pixel share a first common electrode line (n +1)stVst2, first common electrode voltage Vstn+1When the voltage level is switched from a relatively high level to a low level, the pixel holding voltage Vp of the sub-pixel is caused by the parasitic capacitance of the pixel and the coupling effect among the parasitic capacitance, the storage capacitance and the pixel capacitancem-n+1_1The voltage signal Vst loaded by the common electrode linen+1By a decrease Δ V, i.e. Vp, from a relatively high level to a low levelm-n+1_1The voltage difference with the common electrode reference voltage Vcom on the second common electrode line sidex becomes x- Δ V and the decrease in positive polarity voltage decreases the brightness of the sub-pixel.
Referring to fig. 15 and 20, the scanning line Gn+1The pixel holding voltage Vp of another row of connected sub-pixelsm-n+1_2A first common electrode line (n +2) connected to the sub-pixelstVst1 applied voltage signal Vstn+2Adjacent first common electrode line (n +1)stVst2 applied voltage signal Vstn+1Is opposite, the first common electrode line (n +2)stVst1 applied voltage signal Vstn+2Switching from relatively low level to high level, wherein the pixel holding voltage Vp of the sub-pixel is generated due to the parasitic capacitance of the pixel and the coupling effect among the parasitic capacitance, the storage capacitance and the pixel capacitancem-n+1_2Will be due to the first common electrode line (n +2)stVst1 applied voltage signal Vstn+2By an increase of Δ V, i.e. Vp, from a relatively low level to a high levelm-n+1_2The voltage difference with the common electrode reference voltage Vcom on the second common electrode line side is changed from x to x + Δ V, and the increase of the positive polarity voltage increases the luminance of the sub-pixel.
Referring to fig. 15 and 20, in the fourth frame4 of the current driving period, when scanning to the nth row, the nth row scan line GnStart to operate with the scanning line GnData lines of connected sub-pixelsm-nHas a negative polarity, i.e. the Data voltage Datam-n<Common electrode reference voltage Vcom, and the scan line GnAfter the pixel capacitors of two adjacent rows of sub-pixels are charged, the scanning line GmThe scanning signal of (2) is turned off; referring to the current frame pixel frame4 driving timing, the pixel holding voltage Vp at the sub-pixel connected to the mth column data line Dm and the nth row scanning line Gn is illustratedm-n_1: at this time, the first common electrode line n connected to the sub-pixelstApplied common electrode voltage Vst of Vst1nSwitching from relatively high level to low level, wherein the pixel holding voltage Vp of the sub-pixel is caused by coupling effect among the parasitic capacitance, the storage capacitance and the pixel capacitance due to the parasitic capacitance of the pixelm-n_1Will be caused by the first common electrode line nstVst1 applied common electrode voltage VstnBy increasing the voltage Δ V, i.e. the pixel holding voltage Vp, from a relatively high level to a low levelm-n_1The voltage difference between the common electrode reference voltage Vcom on the second common electrode line side is changed from-x to-x- Δ V, and the decrease of the negative polarity voltage increases the brightness of the sub-pixel.
Referring to fig. 15 and 20, the scanning line Gm-nThe pixel holding voltage Vp of another row of connected sub-pixelsm-n_2A first common electrode line (n +1) connected to the sub-pixelstVst2 applied voltage signal Vstn+1Adjacent first common electrode line nstVst1 applied voltage signal VstnIs opposite, the voltage signal Vst loaded by the first common electrode line (n +1) stVst2 isn+1Switching from relatively low level to high level, wherein the pixel has parasitic capacitance, and the pixel holding voltage Vp of the sub-pixel is caused by coupling effect among the parasitic capacitance, the storage capacitance and the pixel capacitancem-n_2Will be due to the first common electrode line (n +1)stVst2 applied voltage signal Vstn+1By increasing Δ V, i.e. Vp, from a relatively high level to a low levelm-n_2The voltage difference between the common electrode reference voltage Vcom on the second common electrode line side is changed from-x to-x + Δ V, and the increase of the negative polarity voltage decreases the luminance of the sub-pixel.
Referring to fig. 15 and 20, when progressive scanning is performed to the (n +1) th row, the (n +1) th row scans a line Gn+1Start to operate with the scanning line Gn+1Data lines of connected sub-pixelsm-n+1Is positive polarity, i.e. the Data voltage Datam-n+1>Common electrode reference voltage Vcom, and the scan line Gn+1And after the pixel capacitors of the two rows of connected sub-pixels are charged, the scanning signals are closed. Referring to the current frame pixel frame4 driving timing, the pixel holding voltage Vp of the sub-pixel connected to the mth column data line Dm, the n +1 th row scanning line Gn +1 is illustratedm-n+1_1: at this time, the sub-pixel shares a first common electrode line (n +1) with the previous adjacent sub-pixelstVst2, first common electrodeVoltage Vstn+1From a relatively low level to a high level. The pixel holding voltage Vp of the sub-pixel is caused by the parasitic capacitance of the pixel and the coupling effect among the parasitic capacitance, the storage capacitance and the pixel capacitancem-n+1_1Will be due to the first common electrode line (n +1)stVst2 applied voltage signal Vstn+1By increasing Δ V, i.e. Vp, from a relatively low level to a high levelm-n+1_1The voltage difference with the common electrode reference voltage Vcom on the second common electrode line side is changed from x to x + Δ V, and the increase of the positive polarity voltage increases the luminance of the sub-pixel.
Referring to fig. 15 and 20, the scanning line Gn+1The pixel holding voltage Vp of another row of connected sub-pixelsm-n+1_2A first common electrode line (n +2) connected to the sub-pixelstVst1 applied voltage signal Vstn+2Adjacent first common electrode line (n +1)stVst2 applied voltage signal Vstn+1Is opposite to the polarity of the common electrode line, the voltage signal Vst loaded by the common electrode linem-n+1_2Switching from relatively high level to low level, wherein the pixel holding voltage Vp of the sub-pixel is caused by coupling effect among the parasitic capacitance, the storage capacitance and the pixel capacitance due to the parasitic capacitance of the pixelm-n+1_2Will be due to the first common electrode line (n +2)stVst1 applied voltage signal Vstn+2By a decrease Δ V, i.e. Vp, from a relatively high level to a low levelm-n+1_2The voltage difference with the common electrode reference voltage Vcom on the second common electrode line side is changed from x to x- Δ V, and the increase of the positive polarity voltage decreases the luminance of the sub-pixel.
Referring to fig. 5, in an embodiment, the method for driving the display panel includes the following steps:
step S500, controlling the data voltage on each data line to switch the positive polarity and the negative polarity once every two frames, and controlling the data voltage on the data lines of two groups of sub-pixels of adjacent columns and adjacent rows to switch the positive polarity and the negative polarity in the same frame;
step S600, controlling the common electrode voltage level on each first common electrode line to perform high-low switching with two frames as one driving period, and the high-low switching sequence of two adjacent driving periods is different.
For the specific working processes of step S500 and step S600 in this embodiment, reference may be made to the above embodiments, and details are not described here.
In this embodiment, it can be understood that, in the case of high-low switching between the third frame3 and the fourth frame4, the driving manner of the first frame1 and the second frame2 may refer to the above-mentioned embodiment, which takes the third frame3 and the fourth frame4 as examples, as opposed to the first frame1 and the second frame 2.
Referring to fig. 21 and 23, in the third frame3 of the current driving period, when scanning to the nth row, the nth row scanning line GnStart to operate with the scanning line GnData lines of connected sub-pixelsm-nHas a negative polarity, i.e. the Data voltage Datam-n<Common electrode reference voltage Vcom, and the scan line Gm-nAfter the pixel capacitors of two adjacent rows of sub-pixels are charged, the scanning line GmThe scanning signal of (2) is turned off; referring to the current frame pixel frame3 driving timing, the pixel holding voltage Vp at the sub-pixel connected to the mth column data line Dm and the nth row scanning line Gn is illustratedm-n_1: at this time, the first common electrode line n connected to the sub-pixelstApplied common electrode voltage Vst of Vst1nWhen the voltage level is switched from a relatively high level to a low level, the pixel holding voltage Vp of the sub-pixel is caused by the parasitic capacitance of the pixel and the coupling effect among the parasitic capacitance, the storage capacitance and the pixel capacitancem-n_1Will be caused by the first common electrode line nstVst1 applied common electrode voltage VstnBy a decrease Δ V, i.e. the pixel holding voltage Vp, from a relatively high level to a low levelm-n_1The voltage difference between the common electrode reference voltage Vcom on the second common electrode line side is changed from x to-x- Δ V, and the decrease of the negative polarity voltage increases the brightness of the sub-pixel.
Referring to fig. 21 and 23, the scanning line Gm-nThe pixel holding voltage Vp of another row of connected sub-pixelsm-n_2A first common electrode line (n +1) connected to the sub-pixelstVst2 applied voltage signal Vstn+1Adjacent first common electrode line nstVst1 applied voltage signal Vstm-n_1When the polarities of the voltage signals Vstn +1 loaded on the first common electrode line (n +1) stVst2 are opposite, the voltage signal Vstn +1 is switched from a relatively low level to a high level, and at this time, due to the parasitic capacitance of the pixel, and due to the coupling effect among the parasitic capacitance, the storage capacitance and the pixel capacitance, the pixel holding voltage Vp of the sub-pixel is maintainedm-n_2Will be due to the first common electrode line (n +1)stVst2 applied voltage signal Vstn+1By an increase of Δ V, i.e. Vp, from a relatively low level to a high levelm-n_2The voltage difference between the common electrode reference voltage Vcom on the second common electrode line side is changed from x to-x + Δ V, and the increase of the negative polarity voltage decreases the luminance of the sub-pixel.
Referring to fig. 21 and 23, when progressive scanning is performed to the (n +1) th row, the (n +1) th row scans a line Gn+1Start to operate with the scanning line Gn+1Data lines of connected sub-pixelsm-nIs positive polarity, i.e. the Data voltage Datam-n>Common electrode reference voltage Vcom, and the scan line Gn+1After the pixel capacitors of the two rows of connected sub-pixels are charged, the scanning signal is turned off, and the pixel holding voltage Vp of the sub-pixel connected with the n +1 th row of scanning line Gn +1 of the m column data line Dm is described by referring to the current frame pixel frame3 driving time sequencem-n+1_1The sub-pixel and the previous adjacent sub-pixel share a first common electrode line (n +1)stVst2, first common electrode voltage Vstn+1Switching from relatively low level to high level, wherein the pixel holding voltage Vp of the sub-pixel is caused by parasitic capacitance of the pixel and coupling effect among the parasitic capacitance, the storage capacitance and the pixel capacitancem-n+1_1The voltage signal Vst loaded by the common electrode linen+1By an increase of Δ V, i.e. Vp, from a relatively low level to a high levelm-n+1_1The voltage difference between the reference voltage Vcom of the common electrode on the second common electrode line side is changed from x to x + Δ V, and the increase of the positive polarity voltage allows the reference voltage to be increasedThe luminance of the sub-pixel increases.
Referring to fig. 21 and 23, the scanning line Gn+1The pixel holding voltage Vp of another row of connected sub-pixelsm-n+1_2A first common electrode line (n +2) connected to the sub-pixelstVst1 applied voltage signal Vstn+2Adjacent first common electrode line (n +1)stVst2 applied voltage signal Vstn+1Is opposite, the first common electrode line (n +2)stVst1 applied voltage signal Vstn+2Switching from relatively high level to low level, wherein the pixel holding voltage Vp of the sub-pixel is generated due to the parasitic capacitance of the pixel and the coupling effect among the parasitic capacitance, the storage capacitance and the pixel capacitancem-n+1_2Will be due to the first common electrode line (n +2)stVst1 applied voltage signal Vstn+2By a decrease Δ V, i.e. Vp, from a relatively high level to a low levelm-n+1_2The voltage difference with the common electrode reference voltage Vcom on the second common electrode line side is changed from x to x- Δ V, and the decrease of the positive polarity voltage decreases the luminance of the sub-pixel.
Referring to fig. 21 and 23, in the fourth frame4 of the current driving period, when scanning to the nth row, the nth row scanning line GnStart to operate with the scanning line GnData lines of connected sub-pixelsm-nHas a negative polarity, i.e. the Data voltage Datam-n<Common electrode reference voltage Vcom, and the scan line GnAfter the pixel capacitors of two adjacent rows of sub-pixels are charged, the scanning line GmThe scanning signal of (2) is turned off; referring to the current frame pixel frame4 driving timing, the pixel holding voltage Vp at the sub-pixel connected to the mth column data line Dm and the nth row scanning line Gn is illustratedm-n_1: at this time, the first common electrode line n connected to the sub-pixelstApplied common electrode voltage Vst of Vst1nSwitching from relatively low level to high level, wherein the pixel holding voltage Vp of the sub-pixel is caused by coupling effect among the parasitic capacitance, the storage capacitance and the pixel capacitance due to the parasitic capacitance of the pixelm-n_1Will be caused by the first common electrode line nstVst1Loaded common electrode voltage VstnBy increasing the voltage Δ V, i.e. the pixel holding voltage Vp, from a relatively low level to a high levelm-n_1The voltage difference between the common electrode reference voltage Vcom on the second common electrode line side is changed from-x to-x + Δ V, and the increase of the negative polarity voltage decreases the luminance of the sub-pixel.
Referring to fig. 21 and 23, the scanning line Gm-nThe pixel holding voltage Vp of another row of connected sub-pixelsm-n_2A first common electrode line (n +1) connected to the sub-pixelstVst2 applied voltage signal Vstn+1Adjacent first common electrode line nstVst1 applied voltage signal VstnIs opposite, the voltage signal Vst loaded by the first common electrode line (n +1) stVst2 isn+1Switching from relatively high level to low level, wherein the pixel has parasitic capacitance, and the coupling effect among the parasitic capacitance, the storage capacitance and the pixel capacitance makes the pixel holding voltage Vp of the sub-pixelm-n_2Will be due to the first common electrode line (n +1)stVst2 applied voltage signal Vstn+1By a decrease Δ V, i.e. Vp, from a relatively high level to a low levelm-n_2The voltage difference between the common electrode reference voltage Vcom on the second common electrode line side is changed from x to-x- Δ V, and the decrease of the negative polarity voltage increases the brightness of the sub-pixel.
Referring to fig. 21 and 23, when progressive scanning is performed to the (n +1) th row, the (n +1) th row scans a line Gn+1Start to operate with the scanning line Gn+1Data lines of connected sub-pixelsm-n+1Is a negative polarity, i.e. the Data voltage Datam-n+1<Common electrode reference voltage Vcom, and the scan line Gn+1And after the pixel capacitors of the two rows of connected sub-pixels are charged, the scanning signals are closed. Referring to the current frame pixel frame1 driving timing, the pixel holding voltage Vp of the sub-pixel connected to the mth column data line Dm, the n +1 th row scanning line Gn +1 is illustratedm-n+1_1: at this time, the sub-pixel shares a first common electrode line (n +1) with the previous adjacent sub-pixelstVst2, first common electrode voltage Vstn+1Switching from a relatively high levelTo a low level. The pixel holding voltage Vp of the sub-pixel is caused by the parasitic capacitance of the pixel and the coupling effect among the parasitic capacitance, the storage capacitance and the pixel capacitancem-n+1_1Will be due to the first common electrode line (n +1)stVst2 applied voltage signal Vstn+1By a decrease Δ V, i.e. Vp, from a relatively high level to a low levelm-n+1_1The voltage difference with the common electrode reference voltage Vcom on the second common electrode line side is changed from x to x- Δ V, and the decrease of the positive polarity voltage decreases the luminance of the sub-pixel.
Referring to fig. 21 and 23, the scanning line Gn+1The pixel holding voltage Vp of another row of connected sub-pixelsm-n+1_2A first common electrode line (n +2) connected to the sub-pixelstVst1 applied voltage signal Vstn+2Adjacent first common electrode line (n +1)stVst2 applied voltage signal Vstn+1Is opposite to the polarity of the common electrode line, the voltage signal Vst loaded by the common electrode linem-n+1_2Switching from relatively low level to high level, wherein the pixel holding voltage Vp of the sub-pixel is caused by coupling effect among the parasitic capacitance, the storage capacitance and the pixel capacitance due to the parasitic capacitance of the pixelm-n+1_2Will be due to the first common electrode line (n +2)stVst1 applied voltage signal Vstn+2By an increase of Δ V, i.e. Vp, from a relatively low level to a high levelm-n+1_2The voltage difference with the common electrode reference voltage Vcom on the second common electrode line side is changed from x to x + Δ V, and the increase of the positive polarity voltage increases the luminance of the sub-pixel.
In one embodiment, the data line voltages of two adjacent columns are opposite in polarity.
In this embodiment, the sub-pixels in adjacent rows may be arranged in positive and negative polarities, and the two sub-pixels in the same row and the two sub-pixels in adjacent rows in each pixel group are connected to a data line, so that the polarities of the two sub-pixels in the same row are different, and the polarities of the two adjacent sub-pixels in the same row are also different. By the arrangement, the display of the resolution in the display panel space is increased, and the defect of color cast of the display panel visual angle is improved. In addition, the invention adopts the design of sharing the scanning lines and the common electrode lines, reduces half of the scanning driving electrodes and the common electrode driving electrodes, increases the effective aperture opening rate of the display panel and improves the penetration rate.
In an embodiment, the driving method of the display panel further includes:
and performing column inversion driving on each sub-pixel.
In this embodiment, each pixel group includes two rows of sub-pixels, the two rows of sub-pixels are connected to a scan line, the storage capacitors of the two rows of sub-pixels are respectively connected to a driving structure of a first common electrode line Vstn, Vstn +1, and the data signal Datam is driven by dot inversion in a column inversion manner, which avoids the need of switching the positive and negative polarities when the data voltages on the same data line are scanned line by line, so that the distortion of the data voltage signal due to the existence of the pixel parasitic capacitance is reduced, and solves the problem that the data voltage of the source driver needs to be switched between positive polarity and negative polarity continuously when the line-by-line scanning is performed, the display device generates large power consumption due to the large voltage switching frequency, and the driving chip may be damaged due to the high temperature in severe cases.
The present invention also provides a driving apparatus of a display panel, the display panel including:
a plurality of pixel groups 101, each pixel group comprises two rows of adjacent sub-pixel groups (101n, 101n ', 101n + 1'), the two rows of adjacent sub-pixel groups (101n, 101n '), (101n +1, 101n + 1') are respectively connected with one scanning line (Gn, Gn +1), each sub-pixel group comprises two sub-pixels, and the two sub-pixels are connected with the same scanning line;
in two sub-pixel groups in adjacent rows, the storage capacitors of two adjacent sub-pixels are connected with the same first common electrode wire, and the storage capacitors of two non-adjacent sub-pixels are correspondingly connected with the other two first common electrode wires one by one;
two data lines which are positioned in the same row and are respectively connected with two adjacent sub-pixel groups are adjacent, and two data lines which are positioned in the adjacent row and are respectively connected with two adjacent sub-pixel groups are adjacent; and the polarities of the voltages on the two adjacent first common electrode lines are opposite.
In this embodiment, the display panel is provided with a pixel array (not shown), a scan line (Gn, Gn +1), a data line (Dm-1, Dm +1), a first common electrode line Vst1 and a second common electrode line Vcom, and the pixel array includes a plurality of sub-pixels. Each sub-pixel comprises an active switch (thin film transistor), a pixel capacitor Clc and a storage capacitor Cst, wherein the gate of the active switch is electrically connected to the corresponding scan line (Gn, Gn +1) of the sub-pixel, the source of the active switch is electrically connected to the corresponding data line (Dm-1, Dm +1) of the sub-pixel, the drain of the active switch is electrically connected to one end of the pixel capacitor Clc and the storage capacitor Cst of the sub-pixel through the data line (Dm-1, Dm +1), and the other end of each pixel capacitor Clc is electrically connected to the second common electrode line Vcom. In the present embodiment, two rows of sub-pixels are defined as a sub-pixel group 10, and the other ends of the storage capacitors Cst of the two sub-pixel groups 10 are respectively connected to a first common electrode line Vst 1. Wherein each sub-pixel is divided into three sub-pixel groups 10 of red, green and blue. Every three sub-pixels of red, green and blue form a pixel. A plurality of thin film transistors constitute the thin film transistor array of the present embodiment.
Referring to fig. 1, in fig. 1, Gn and Gn +1 are illustrated as two adjacent rows of scan lines, Dm-1, Dm and Dm +1 are illustrated as three adjacent columns of data lines, and nstVst1、(n+1)stVst2、(n+2)stThree first common electrode lines adjacent to Vst1, Clc1 and Clc2, which represent pixel capacitances connected to the same scan line in the same group, and Cst1 and Cst2, which represent storage capacitances connected to different first common motor lines in the same group, respectively.
Referring to fig. 15, the driving apparatus of the display panel further includes:
a source driver circuit 20, a plurality of output terminals of the source driver circuit 20 being connected to the data lines, the source driver circuit 20 being configured to output data voltages with positive and negative polarities switched to the data lines every two frames;
a common electrode voltage circuit 50, an output end of the common electrode voltage circuit 50 and each of the first common electrode lines, wherein the common electrode voltage circuit 50 is configured to output a common electrode voltage switched between high and low levels to each of the first common electrode lines with two frames as a driving period;
the driving device of the display panel is further provided with a processor, a memory and a driving program of the display panel, which is stored on the memory and can run on the processor, wherein the driving program of the display panel is configured to realize the steps of the driving method of the display panel.
In this embodiment, the processor may be a timing controller 10, and the timing controller 10 is connected to the source driving circuit 20 and the gate driving circuit 30 respectively to provide timing control signals for the source driving circuit 20 and the gate driving circuit 30, in this embodiment, a timing signal for controlling the data voltage on each data line to switch the positive and negative polarities every two frames is stored in the timing controller 10, in the driving of each frame, the timing controller 10 receives the image data of the picture to be displayed sent from the front end, and the timing controller 10 converts the image data and the control signals received from the front end into data signals, control signals, and clock signals suitable for the source driver 20 and the gate driver 30. The source driver 20 converts the received digital signals into corresponding gray scale voltage signals, when the gate driver 30 scans line by line, all the column data signal lines transmit data signals to the pixel row, and charge the capacitors of the sub-pixels in the pixel row, so as to implement writing and maintaining of the signal voltage of the pixel, and the liquid crystal molecules of the sub-pixels rotate under the voltage, so that the transmittance of incident light passing through the liquid crystal molecules is changed, that is, the light valve effect on the incident light is implemented, the change of the brightness of the incident light is implemented, and finally, the image display of the display panel 100 is implemented. The signals Output to the gate driver include a Start Vertical (STV) signal, a Clock Pulse Vertical (CPV) signal, an Enable signal (OE), and the like.
Common electrode voltage circuit 50 and first common electrode line (n)stVst1、(n+1)stVst2、(n+2)stVst1) andthe two common electrode lines Vcom are connected to provide a common electrode reference voltage for the second common electrode line Vcom, and the common electrode voltage circuit 50 also provides two adjacent first common electrode lines (n)stVst1、(n+1)stVst2、(n+2)stVst1) and the common electrode voltage circuit 50 controls the common electrode voltages on the adjacent two first common electrode lines to perform polarity inversion with two frames as a driving period.
Referring to fig. 24, in some embodiments, the memory may be implemented using an EEPROM (Electrically Erasable Programmable read only memory) or a Flash memory Flash. The memory, the Timing Controller 10 and the common electrode circuit 50 may be disposed on a Timing Controller (TCON) PCB, the memory may store control signals for driving the gate driver 20 and the source driver 30 to operate, and is in communication connection with the Timing Controller 10 through a serial communication bus, and when the display device is powered on and operated, the Timing Controller 10 reads the control signals in the memory and performs initial setting on other set data to generate corresponding Timing control signals, so as to drive the display panel 100 in the display device to operate, that is, the data stored in the memory is the initialization data of the display panel 100.
Referring to fig. 24, in this embodiment, the processor may be a timing controller 10, and the timing controller 10 is respectively connected to the source driving circuit 20 and the gate driving circuit 30 to provide timing control signals for the source driving circuit 20 and the gate driving circuit 30, in this embodiment, timing signals for controlling the data voltage on each of the data lines to switch the positive and negative polarities in a driving period of two frames are stored in the timing controller 10, in each frame of driving, the timing controller 10 receives image data of a picture to be displayed sent from a front end, and the timing controller 10 converts the image data and the control signals received from the front end into data signals, control signals, and clock signals suitable for the source driver 20 and the gate driver 30. The source driver 20 converts the received digital signals into corresponding gray scale voltage signals, when the gate driver 30 scans line by line, all the column data signal lines transmit data signals to the pixel row, and charge the capacitors of the sub-pixels in the pixel row, so as to implement writing and maintaining of the signal voltage of the pixel, and the liquid crystal molecules of the sub-pixels rotate under the voltage, so that the transmittance of incident light passing through the liquid crystal molecules is changed, that is, the light valve effect on the incident light is implemented, the change of the brightness of the incident light is implemented, and finally, the image display of the display panel 100 is implemented. The signals Output to the gate driver include a Start Vertical (STV) signal, a Clock Pulse Vertical (CPV) signal, an Enable signal (OE), and the like.
Common electrode voltage circuit 50 and first common electrode line (n)stVst1、(n+1)stVst2、(n+2)stVst1) and a second common electrode line Vcom to provide a common electrode reference voltage for the second common electrode line Vcom, and the common electrode voltage circuit 50 also provides two adjacent first common electrode lines (n)stVst1、(n+1)stVst2、(n+2)stVst1) and the common electrode voltage circuit 50 controls the common electrode voltages on the adjacent two first common electrode lines to perform polarity inversion with two frames as a driving period.
Referring to fig. 24, in some embodiments, the memory may be implemented using an EEPROM (Electrically Erasable Programmable read only memory) or a Flash memory Flash. The memory, the Timing Controller 10 and the common electrode circuit 50 may be disposed on a Timing Controller (TCON) PCB, the memory may store control signals for driving the gate driver 20 and the source driver 30 to operate, and is in communication connection with the Timing Controller 10 through a serial communication bus, and when the display device is powered on and operated, the Timing Controller 10 reads the control signals in the memory and performs initial setting on other set data to generate corresponding Timing control signals, so as to drive the display panel 100 in the display device to operate, that is, the data stored in the memory is the initialization data of the display panel 100.
Referring to fig. 24, in an embodiment, the driving apparatus of the display panel further includes a gate driving circuit 30, where the gate driving circuit 30 is connected to a gate of each of the sub-pixels; the gate driving circuit 30 is configured to output a gate driving signal to each row of sub-pixels, so that the second common electrode Vcom and the data line are applied with corresponding voltages, and pixel capacitance charging of the sub-pixels in the corresponding row is achieved.
Referring to fig. 24, in an embodiment, the driving circuit of the display panel further includes a gamma circuit 60 configured to generate a plurality of gamma voltages and output the gamma voltages to the source driver 30, and the source driver 30 charges corresponding pixels according to the timing control signal and the gamma voltages output by the timing controller 10, so that the source driver 30 outputs data signals to the corresponding pixels to display the image to be displayed. The gamma circuit 60 may be implemented by a programmable gamma chip, or by discrete components such as a resistor string and a memory, and may generate a set of gamma voltages (V γ 1 to V γ 14) that can be used as pixel grayscale reference voltages.
Referring to fig. 25, in an embodiment, the display panel 100 further includes:
a first substrate 110 having a display area AA and a peripheral area, i.e., a non-display area BB; the pixel array 140 is disposed on the first substrate 110 and located in the display area AA; the N array substrate row driving circuits 10 and the auxiliary circuits 20 arranged in cascade are arranged on the first substrate 110 and located in the peripheral region;
a second substrate 120 disposed opposite to the first substrate 110;
the liquid crystal layer 130 is disposed between the first substrate 110 and the second substrate, the liquid crystal layer 130 includes a plurality of liquid crystal molecules, and the pixel array 140 is configured to control the actions of the plurality of liquid crystal molecules.
In this embodiment, the first substrate 110 and the second substrate are both generally transparent substrates such as glass substrates or plastic substrates. The second substrate is disposed opposite to the first substrate 110, and a corresponding circuit may be disposed between the first substrate 110 and the second substrate. The first substrate 110 is an array substrate, the second substrate is a color film substrate, and the first substrate 110 and the second substrate may be flexible transparent substrates. The pixel array 140 is disposed on the first substrate 110 and located in the display area AA.
It is understood that, in the above embodiment, the display panel 100 further includes the sealant 150 disposed in the display area BB between the first substrate 110 and the second substrate 120 and surrounding the liquid crystal layer 130, and the array substrate row driving circuit 10 is located between the sealant 150 and the display area AA. The sealant 150 may be coated on the first substrate 110 or the second substrate 120 by using a sealant to connect the first substrate 110 and the second substrate 120, so as to implement the assembling process of the display panel 100.
The display panel is divided into a System On Chip (SOC) type and a Gate On Array (GOA) type by a Gate driver design (Gate driver design). The GOA directly manufactures a Gate driver IC (Gate driver IC) on an Array substrate of a display device, instead of a process technology of manufacturing a driver chip from an external silicon chip. The application of the technology can reduce the production process procedures, reduce the product process cost and improve the integration level of the display panel. With the development of liquid crystal televisions and computers towards the direction of super-large size and high resolution, more and more liquid crystal display panels adopt narrow-frame design to increase the display area of the display screen.
The GOA is generally disposed at a side frame of the display panel, and a gate line scanning driving signal circuit is fabricated on an array substrate of the display panel by using a Thin Film Transistor (TFT) liquid crystal display array process to realize a driving method of scanning a gate line by line, which has the advantages of reducing production cost and realizing a narrow frame design of the panel, and is used for various displays. In an exemplary architecture of the GOA-type display panel, LC (Liquid Crystal) molecules are filled between upper and lower glass substrates and sealed with a sealing material at the periphery; among them, liquid crystal is a polymer material, and is widely used in light and thin display technologies due to its special physical, chemical and optical properties. According to the size of the display panel, the GOA circuits may be disposed on one side of the display panel, or on both sides of the display panel, and when disposed on both sides of the display panel, the GOA circuits on both sides may simultaneously drive one row of sub-pixels to be turned on, or alternatively control each row of sub-pixels to be turned on.
The invention also comprises a display device, which comprises a display panel and the driving device of the display panel, wherein the driving device of the display panel is connected with each sub-pixel of the display panel. The detailed structure of the driving device of the display panel can refer to the above embodiments, and is not described herein again; it can be understood that, since the display device of the present invention uses the driving device of the display panel, the embodiment of the display device of the present invention includes all the technical solutions of all the embodiments of the driving device of the display panel, and the achieved technical effects are also completely the same, and are not described herein again.
In the above embodiments, the display panel includes, but is not limited to, a liquid crystal display panel, an organic light emitting diode display panel, a field emission display panel, a plasma display panel, a curved panel, and the liquid crystal panel includes a thin film transistor liquid crystal display panel, a TN panel, a VA panel, an IPS panel, and the like.
The above description is only an alternative embodiment of the present invention, and not intended to limit the scope of the present invention, and all modifications and equivalents of the present invention, which are made by the contents of the present specification and the accompanying drawings, or directly/indirectly applied to other related technical fields, are included in the scope of the present invention.
Claims (13)
1. A driving method of a display panel, the display panel comprising:
each pixel group comprises two rows of adjacent sub-pixel groups, each two rows of adjacent sub-pixel groups are respectively connected with one scanning line, each sub-pixel group comprises two sub-pixels, and the two sub-pixels are connected with the same scanning line;
in two sub-pixel groups in adjacent rows, the storage capacitors of two adjacent sub-pixels are connected with the same first common electrode wire, and the storage capacitors of two non-adjacent sub-pixels are correspondingly connected with the other two first common electrode wires one by one;
two data lines which are positioned in the same row and are respectively connected with two adjacent sub-pixel groups are adjacent, and two data lines which are positioned in the adjacent row and are respectively connected with two adjacent sub-pixel groups are adjacent;
the polarities of the voltages on the two adjacent first common electrode lines are opposite; the driving method of the display panel includes the steps of:
controlling the data voltage on each data line to switch the positive polarity and the negative polarity once every two frames;
and controlling the voltage level of the common electrode on each first common electrode line to switch high and low by taking two frames as a driving period.
2. The method for driving a display panel according to claim 1, wherein the step of controlling the data voltage on each data line to perform one positive/negative polarity switching for one driving period of two frames comprises:
the polarity of a data voltage on one data line in the data lines of two adjacent columns of the sub-pixels is positive polarity, negative polarity and negative polarity sequentially in four adjacent frames;
and the polarities of the data voltage on the other data line in the data lines of the two adjacent columns of the sub-pixels are negative polarity, positive polarity and positive polarity in sequence in four adjacent frames.
3. The method according to claim 2, wherein the scan signal on each of the scan lines in each frame comprises an on-phase and an off-phase, and the common electrode voltage on the first common electrode line is controlled to switch between high and low levels when the scan signal on each of the scan lines is switched from the on-phase to the off-phase.
4. The method according to claim 3, wherein the step of controlling the common electrode voltage on the first common electrode line to switch between high and low levels when the scan signal of each scan line is switched from an on phase to an off phase comprises:
two rows of sub-pixels in the same group are respectively an nth row of sub-pixels and an n +1 th row of sub-pixels;
in a first frame of adjacent four frames, when the data voltage of the sub-pixels of the nth row and the sub-pixels of the (n +1) th row are positive, controlling the voltage of the common electrode of the sub-pixels of the nth row to be switched from low level to high level, and controlling the voltage of the common electrode of the sub-pixels of the (n +1) th row to be switched from high level to low level;
in a second frame of adjacent four frames, when the data voltage of the sub-pixels of the nth row and the sub-pixels of the (n +1) th row are controlled to be positive, the voltage of the common electrode of the sub-pixels of the nth row is controlled to be switched from high level to low level, and the voltage of the common electrode of the sub-pixels of the (n +1) th row is controlled to be switched from low level to high level;
in a third frame of adjacent four frames, when the data voltage of the sub-pixels of the nth row and the sub-pixels of the (n +1) th row are controlled to be negative, the voltage of the common electrode of the sub-pixels of the nth row is controlled to be switched from low level to high level, and the voltage of the common electrode of the sub-pixels of the (n +1) th row is controlled to be switched from high level to low level;
in a fourth frame of adjacent four frames, when the data voltage of the sub-pixels of the nth row and the sub-pixels of the (n +1) th row are controlled to be negative polarity, the voltage of the common electrode of the sub-pixels of the nth row is controlled to be switched from high level to low level, and the voltage of the common electrode of the sub-pixels of the (n +1) th row is controlled to be switched from low level to high level.
5. The method according to claim 3, wherein the step of controlling the common electrode voltage on the first common electrode line to switch between high and low levels when the scan signal of each scan line is switched from an on phase to an off phase comprises:
two rows of sub-pixels in the same group are respectively an nth row of sub-pixels and an n +1 th row of sub-pixels;
in a first frame of adjacent four frames, when the data voltage of the sub-pixels of the nth row and the sub-pixels of the (n +1) th row are positive, controlling the common electrode voltage of the sub-pixels of the nth row to be switched from high level to low level, and controlling the common electrode voltage of the sub-pixels of the (n +1) th row to be switched from low level to high level;
in a second frame of adjacent four frames, when the data voltage of the sub-pixels of the nth row and the sub-pixels of the (n +1) th row are controlled to be positive, the voltage of the common electrode of the sub-pixels of the nth row is controlled to be switched from low level to high level, and the voltage of the common electrode of the sub-pixels of the (n +1) th row is controlled to be switched from high level to low level;
in a third frame of adjacent four frames, when the data voltage of the sub-pixels of the nth row and the sub-pixels of the (n +1) th row are controlled to be negative, the voltage of the common electrode of the sub-pixels of the nth row is controlled to be switched from high level to low level, and the voltage of the common electrode of the sub-pixels of the (n +1) th row is controlled to be switched from low level to high level;
in a fourth frame of adjacent four frames, when the data voltage of the sub-pixels of the nth row and the sub-pixels of the (n +1) th row are controlled to be negative polarity, the voltage of the common electrode of the sub-pixels of the nth row is controlled to be switched from low level to high level, and the voltage of the common electrode of the sub-pixels of the (n +1) th row is controlled to be switched from high level to low level.
6. The display panel driving method according to claim 3, wherein in the step of controlling the common electrode voltage level on each of the first common electrode lines to perform the high-low switching in one driving period of two frames, the high-low switching sequence of two adjacent driving periods is different.
7. The method according to claim 6, wherein the step of controlling the common electrode voltage on the first common electrode line to switch between high and low levels when the scan signal of each scan line is switched from an on phase to an off phase comprises:
two rows of sub-pixels in the same group are respectively an nth row of sub-pixels and an n +1 th row of sub-pixels;
in a first frame of adjacent four frames, when the data voltage of the sub-pixels of the nth row and the sub-pixels of the (n +1) th row are positive, controlling the voltage of the common electrode of the sub-pixels of the nth row to be switched from low level to high level, and controlling the voltage of the common electrode of the sub-pixels of the (n +1) th row to be switched from high level to low level;
in a second frame of adjacent four frames, when the data voltage of the sub-pixels of the nth row and the sub-pixels of the (n +1) th row are controlled to be positive, the voltage of the common electrode of the sub-pixels of the nth row is controlled to be switched from high level to low level, and the voltage of the common electrode of the sub-pixels of the (n +1) th row is controlled to be switched from low level to high level;
in a third frame of adjacent four frames, when the data voltage for controlling the sub-pixels of the nth row and the sub-pixels of the (n +1) th row is negative, the voltage of the common electrode of the sub-pixels of the nth row is controlled to be switched from high level to low level in the same way as the second frame, and the voltage of the common electrode of the sub-pixels of the (n +1) th row is controlled to be switched from low level to high level in the same way as the second frame;
in a fourth frame of adjacent four frames, when the data voltage of the sub-pixels of the nth row and the sub-pixels of the (n +1) th row are controlled to be negative polarity, the voltage of the common electrode of the sub-pixels of the nth row is controlled to be switched from low level to high level, and the voltage of the common electrode of the sub-pixels of the (n +1) th row is controlled to be switched from high level to low level.
8. The method according to claim 6, wherein the step of controlling the common electrode voltage on the first common electrode line to switch between high and low levels when the scan signal of each scan line is switched from an on phase to an off phase comprises:
two rows of sub-pixels in the same group are respectively an nth row of sub-pixels and an n +1 th row of sub-pixels;
in a first frame of adjacent four frames, when the data voltage of the sub-pixels of the nth row and the sub-pixels of the (n +1) th row are positive, controlling the common electrode voltage of the sub-pixels of the nth row to be switched from high level to low level, and controlling the common electrode voltage of the sub-pixels of the (n +1) th row to be switched from low level to high level;
in a second frame of adjacent four frames, when the data voltage of the sub-pixels of the nth row and the sub-pixels of the (n +1) th row are controlled to be positive, the voltage of the common electrode of the sub-pixels of the nth row is controlled to be switched from low level to high level, and the voltage of the common electrode of the sub-pixels of the (n +1) th row is controlled to be switched from high level to low level;
in a third frame of adjacent four frames, when the data voltage for controlling the sub-pixels of the nth row and the sub-pixels of the (n +1) th row is negative, the voltage of the common electrode of the sub-pixels of the nth row is controlled to be switched from low level to high level in the same way as the second frame, and the voltage of the common electrode of the sub-pixels of the (n +1) th row is controlled to be switched from high level to low level in the same way as the second frame;
in a fourth frame of adjacent four frames, when the data voltage of the sub-pixels of the nth row and the sub-pixels of the (n +1) th row are controlled to be negative polarity, the voltage of the common electrode of the sub-pixels of the nth row is controlled to be switched from high level to low level, and the voltage of the common electrode of the sub-pixels of the (n +1) th row is controlled to be switched from low level to high level.
9. The display panel driving method according to claim 1, wherein in said step of controlling the data voltage on each of said data lines to switch between positive and negative polarities every two frames,
and in the same frame, controlling the data voltages on the data lines of two adjacent groups of the sub-pixel groups to switch the positive polarity and the negative polarity.
10. The method for driving a display panel according to claim 1, wherein the data voltages on the data lines of two adjacent columns have opposite polarities.
11. The method of driving a display panel according to any one of claims 1 to 10, further comprising:
the polarities of the sub-pixels on the same data line are the same, and the data lines of the display panel are driven in a row-column inversion mode.
12. A driving apparatus of a display panel, the display panel comprising:
each pixel group comprises two rows of adjacent sub-pixel groups, each two rows of adjacent sub-pixel groups are respectively connected with one scanning line, each sub-pixel group comprises two sub-pixels, and the two sub-pixels are connected with the same scanning line;
in two sub-pixel groups in adjacent rows, the storage capacitors of two adjacent sub-pixels are connected with the same first common electrode wire, and the storage capacitors of two non-adjacent sub-pixels are correspondingly connected with the other two first common electrode wires one by one;
two data lines which are positioned in the same row and are respectively connected with two adjacent sub-pixel groups are adjacent, and two data lines which are positioned in the adjacent row and are respectively connected with two adjacent sub-pixel groups are adjacent;
the polarities of the voltages on the two adjacent first common electrode lines are opposite; the driving device of the display panel further includes:
the source driving circuit is configured to output data voltages with switched positive and negative polarities to the data lines every two frames;
the output end of the common electrode voltage circuit is connected with each first common electrode wire, and the common electrode voltage circuit is configured to output a common electrode voltage switched by high and low levels to each first common electrode wire by taking two frames as a driving period;
the driving apparatus of a display panel is further provided with a processor, a memory, and a driver of a display panel stored on the memory and operable on the processor, the driver of the display panel being configured to implement the steps of the driving method of a display panel according to any one of claims 1 to 11.
13. A display device comprising a display panel and a driving device of the display panel according to claim 12, wherein the driving device of the display panel is connected to each sub-pixel of the display panel.
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| CN114822409A (en) * | 2022-06-24 | 2022-07-29 | 惠科股份有限公司 | Pixel driving circuit, display panel and display device |
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