KR102530894B1 - Display device - Google Patents

Abstract

The present invention relates to a display device. The pixels of the display panel include two sub-pixels having different colors among sub-pixels. A red subpixel, a green subpixel, and a blue subpixel are disposed in a line direction and a column direction that cross each other in the pixel array of the display panel. Adjacent subpixels on each line of the display panel are offset from each other by a width smaller than the width of one line, and island pattern color filters are connected between the adjacent subpixels of the same color, so that the adjacent subpixels of the same color are connected to each other. The color filter of the island pattern is shared between them. The thin film transistor includes first and second thin film transistors connected between one data line and one pixel electrode in each of the subpixels.

Description

Display device {DISPLAY DEVICE}

The present invention relates to a display device in which each of the pixels is divided into two sub-pixels having different colors.

Liquid Crystal Display Device (LCD), Organic Light Emitting Diode Display (OLED Display), Plasma Display Panel (PDP), Electrophoretic Display Device (EPD) Various flat panel display devices such as these are being developed. A liquid crystal display device displays an image by controlling light transmittance of pixels according to an electric field applied to liquid crystal molecules according to a data voltage. A thin film transistor (hereinafter referred to as "TFT") is formed in each pixel of an active matrix driving type liquid crystal display device.

The liquid crystal display device includes a liquid crystal display panel, a backlight unit for irradiating light to the liquid crystal display panel, a source drive integrated circuit (hereinafter referred to as "IC") for supplying data voltage to data lines of the liquid crystal display panel, liquid crystal A gate drive IC for supplying gate pulses (or scan pulses) to the gate lines (or scan lines) of the display panel, a control circuit for controlling the ICs, and a light source driving circuit for driving the light source of the backlight unit. provide

In order to reduce power consumption, as shown in FIG. 1, an RGBW type display device in which a white sub-pixel is added in addition to a red (R) sub-pixel, a green (G) sub-pixel, and a blue (B) sub-pixel. is being developed.

In the RGBW type display device shown in FIG. 1, R sub-pixels, G sub-pixels, and B sub-pixels are separated for each line. Due to this, each of the R color filter, the G color filter, and the B color filter is formed in an island pattern. Since the sub-pixel size island pattern is very small, it cannot be applied to a high resolution, high PPI (Pixel Per Inch) display device. For example, in the current process, the minimum horizontal length of a manufacturable island pattern is 12 μm, but in the case of a high PPI model of 1000 PPI or more, since the horizontal pitch of subpixels becomes smaller than 12 μm, the island pattern has a high PPI model. The color filter of the pattern cannot be applied.

Accordingly, an object of the present invention is to provide a display device capable of applying an island pattern color filter at high resolution and high PPI.

A display device of the present invention includes a plurality of data lines, a plurality of gate lines, a plurality of red subpixels, a plurality of green subpixels, a plurality of blue subpixels, and thin film transistors disposed on each of the subpixels. and a display panel having a pixel array, and a display panel driving circuit for writing data of an input image to sub-pixels of the display panel. The pixels of the display panel include two sub-pixels having different colors among the sub-pixels. A red sub-pixel, a green sub-pixel, and a blue sub-pixel are disposed in each of a line direction and a column direction crossing each other in the pixel array. Adjacent subpixels on each line of the display panel are offset from each other by a width smaller than the width of one line, and island pattern color filters are connected between the adjacent subpixels of the same color, so that the adjacent subpixels of the same color are connected to each other. The color filter of the island pattern is shared between them. The thin film transistor includes first and second thin film transistors connected between one data line and one pixel electrode in each of the subpixels.

In another display device of the present invention, sub-pixels of the same color among neighboring pixels share the same color filter.

The display device of the present invention configures one pixel with two sub-pixels of different colors without a white sub-pixel using the Pentile rendering algorithm to increase the size of each sub-pixel, thereby providing an island image at high PPI. Enables the application of color filters for patterns.

In the display device of the present invention, R sub-pixels, G sub-pixels, and B sub-pixels are arranged to be adjacent to each other in the line direction and the column direction, respectively, so that high PPI and high resolution can be certified.

Furthermore, since the display device of the present invention shares the same color filter among neighboring pixels, the island pattern color filter can be applied at high PPI without problems in the manufacturing process by making the size of the color filter larger.

1 is a diagram showing a sub-pixel arrangement for each color in an RGBW type display device.
2 is a diagram showing a display device according to an exemplary embodiment of the present invention.
3 is a plan view comparing a pixel of the prior art and a pixel of the present invention.
4 is a diagram showing a pixel array according to a first embodiment of the present invention.
FIG. 5 is a diagram showing expressions of horizontal lines and vertical lines in the pixel array shown in FIG. 4 .
6 to 8 are diagrams showing an example of a data compensating method in the pixel array shown in FIG. 4 .
9 is a diagram showing a pixel array according to a second embodiment of the present invention.
FIG. 10 is a diagram showing expressions of horizontal lines and vertical lines in the pixel array shown in FIG. 9 .
11 to 14 are diagrams illustrating an example of a data compensating method in the pixel array shown in FIG. 9 .
15 and 16 are views showing a planar and cross-sectional structure of one sub-pixel in the display device of the present invention.
FIG. 17 is a plan view showing a planar structure of 2*2 subpixels in the pixel array shown in FIG. 4 .
FIG. 18 is an equivalent circuit diagram of 3*3 subpixels in the pixel array shown in FIG. 4 .
FIG. 19 is a plan view showing a planar structure of 2*2 subpixels in the pixel array shown in FIG. 9 .
FIG. 20 is an equivalent circuit diagram of 3*3 subpixels in the pixel array shown in FIG. 9 .

The display device of the present invention may be implemented as a flat panel display capable of implementing color, such as a liquid crystal display (LCD) or an organic light emitting diode display (OLED display). Hereinafter, embodiments of the present invention will be described focusing on the liquid crystal display, but it should be noted that the present invention is not limited to the liquid crystal display.

In the present invention, in an RGB type display device without a W sub-pixel, a pixel array of a display device is configured with a pentile pixel structure in which pixels are composed of two sub-pixels having different colors.

Hereinafter, preferred embodiments according to the present invention will be described in detail with reference to the accompanying drawings. Like reference numbers throughout the specification indicate substantially the same elements. In the following description, if it is determined that a detailed description of a known function or configuration related to the present invention may unnecessarily obscure the subject matter of the present invention, the detailed description will be omitted.

Referring to FIGS. 2 and 3 , the display device of the present invention includes a display panel 100 on which a pixel array is formed, and a display panel driving circuit for writing data of an input image on the display panel 100 . A backlight unit for uniformly irradiating light to the display panel 100 may be disposed below the display panel 100 .

The display panel 100 includes an upper substrate and a lower substrate facing each other with a liquid crystal layer interposed therebetween. The pixel array of the display panel 100 includes pixels arranged in a matrix form by crossing data lines S1 to Sm and gate lines G1 to Gn.

The pixel array of the display panel 100 includes RGB sub-pixels without a W sub-pixel and implements one pixel with two sub-pixels of different colors. The display device according to the present invention applies a Pentile rendering algorithm according to the RGB sub-pixel structure to compensate for color by distributing data values of colors lacking in each pixel to one or more adjacent pixels.

In the display device of the present invention, a pixel array is composed of only RGB sub-pixels without W sub-pixels. Therefore, since each of the pixels includes only two color subpixels of different colors among RGB subpixels as shown in FIG. Therefore, it is possible to manufacture island-patterned color filters with current process technology without any problems.

Subpixels of different colors are disposed between subpixels of the same color in each of a column direction (Y axis) and a line direction (X axis) that cross each other in the pixel array. For example, as shown in FIGS. 4 and 9 , subpixels are arranged in the order of R subpixel, G subpixel, and B subpixel along the line direction X, and R subpixel and B subpixel along the column direction Y. Sub-pixels may be arranged in the order of pixel and G sub-pixel, but are not limited thereto. The sub-pixels may be fabricated in a structure with excellent readability, that is, a structure in which a vertical length is longer than a horizontal length.

The pixel array includes an opening through which light is transmitted and a non-opening area. As shown in FIGS. 4 and 9 , the opening is a portion through which light is transmitted in each of the subpixels. Components that block light, such as signal lines such as data lines and gate lines, TFTs, spacers, and capacitors, are disposed in the non-opening area, and a black matrix (BM) is applied so that these components are not visible.

The color filter of the pixel array is patterned into an island type as shown in FIGS. 4 and 9 . Sub-pixels of the same color are separated in the column direction (Y-axis) of the pixel array, and sub-pixels of different colors are disposed between them.

On the lower substrate of the display panel 100, data lines S1 to Sm, gate lines G1 to Gn, TFTs, pixel electrodes 1 connected to the TFTs, and storage connected to the pixel electrodes 1 are provided. A TFT array such as a storage capacitor (Cst) may be formed. Each of the RGB sub-pixels is transmitted through the opening using liquid crystal molecules driven by the voltage difference between the pixel electrode PXL charging the data voltage through the TFT and the common electrode COM to which the common voltage Vcom is applied. Adjust the amount of light.

The TFTs formed on the lower substrate of the display panel 100 may be implemented as amorphose Si (a-Si) TFTs, low temperature poly silicon (LTPS) TFTs, oxide TFTs (TFTs), and the like. In order to reduce leakage current when the TFT is off, each of the sub-pixels may include two TFTs connected in series.

A color filter array including a black matrix (BM) and color filters may be formed on the upper substrate of the display panel 100 . In a display panel having a color filter on TFT (COT) structure, a black matrix and color filters may be disposed on a TFT array. The common electrode (COM) is formed on the upper substrate in the case of vertical electric field driving methods such as TN (Twisted Nematic) mode and VA (Vertical Alignment) mode, and IPS (In-Plane Switching) mode and FFS (Fringe Field Switching) In the case of a horizontal electric field driving method such as the mode, it may be formed on the lower substrate together with the pixel electrode PXL. A polarizer is attached to each of the upper and lower substrates of the display panel 100 and an alignment layer for setting a pre-tilt angle of liquid crystal is formed.

The display device of the present invention may be implemented in any form such as a transmissive liquid crystal display, a transflective liquid crystal display, or a reflective liquid crystal display. A backlight unit is required in a transmissive liquid crystal display and a transflective liquid crystal display. The backlight unit may be implemented as a direct type backlight unit or an edge type backlight unit.

The display panel driving circuit writes data of an input image to pixels. Data written to pixels includes R data, G data, and B data. The display panel driving circuit includes a data driver 102 , a gate driver 104 , and a timing controller 106 .

The data driver 102 includes a plurality of source drive ICs. The data output channels of the source drive ICs are connected 1:1 to the data lines S1 to Sm of the pixel array. The source drive ICs receive data of an input image from the timing controller 106. Each of the pixel data of the input image transmitted to the source drive ICs includes R data, G data, and B data. The source drive ICs convert data of an input image into positive/negative polarity gamma compensation voltages under the control of the timing controller 106 and output positive/negative polarity data voltages. Data voltages output from the source drive ICs are supplied to the data lines S1 to Sm.

Each of the source drive ICs inverts the polarity of the data voltage to be supplied to the pixels under the control of the timing controller 106 and outputs it to the data lines S1 to Sm.

The gate driver 104 sequentially supplies gate pulses to the gate lines G1 to Gn under the control of the timing controller 106 . The gate pulse output from the gate driver 104 is synchronized with the data voltage to be charged in the pixels. The gate driver 104 may be directly formed on the lower substrate of the display panel 100 together with the pixel array in the same manufacturing process to reduce IC cost.

The timing controller 106 transmits the RGB data of the input image received from the host system 110 to the source driver ICs of the data driver 102 . An interface for data transmission between the timing controller 106 and the source drive ICs of the data driver 102 may use a mini low-voltage differential signaling (LVDS) interface or an embedded panel interface (EPI) interface. The EPI interface is disclosed in Korean Patent Application No. 10-2008-0127458 (2008-12-15), US Application No. 12/543,996 (2009-08-19), and Korean Patent Application No. 10-2008-0127456 (2008-12) filed by the present applicant. -15), US application 12/461,652 (2009-08-19), Korean patent application 10-2008-0132466 (2008-12-23), US application 12/537,341 (2009-08-07), etc.

The timing controller 106 receives timing signals synchronized with input image data from the host system 110 . The timing signals include a vertical synchronizing signal Vsync, a horizontal synchronizing signal Hsync, a data enable signal DE, and a dot clock DCLK. The timing controller 106 controls operation timings of the data driver 102 and the gate driver 104 based on timing signals Vsync, Hsync, DE, and DCLK received together with pixel data of an input image. The timing controller 106 may transmit a polarity control signal for controlling the polarity of the pixel array to each of the source drive ICs of the data driver 102 . The Mini LVDS interface transmits a polarity control signal through a separate control line. The EPI interface is an interface technology that encodes polarity control information in a control data packet transmitted between a clock training pattern for CDR (Clok and Data Recovery) and RGBW data packets and transmits it to each of the source driver ICs.

The timing controller 106 or the host system 110 may execute a preset pentile rendering algorithm to distribute data values of colors lacking in each pixel to neighboring pixels.

The host system 110 may be any one of a TV (Television) system, a set-top box, a navigation system, a DVD player, a Blu-ray player, a personal computer (PC), a home theater system, and a phone system. The host system 110 may transmit a timing signal synchronized with the data of the input image to the timing controller 106.

4 is a diagram showing a pixel array according to a first embodiment of the present invention. FIG. 5 is a diagram showing representations of horizontal and vertical lines in the pixel array shown in FIG. 4. In FIGS. 4 and 5, “R” denotes an R sub-pixel and “G” denotes a G sub-pixel. and “B” is the B sub-pixel. Island-patterned color filters are formed in these sub-pixels.

4 and 5, subpixels are arranged in the order of R subpixel, G subpixel, and B subpixel in the line direction (X) of the pixel array, and R subpixel and B subpixel in the column direction (Y). and G subpixels are arranged in order. Also, subpixels of the same color are disposed along a diagonal direction.

In the pixel array, 3*3 pixels P1 to P9 having a color arrangement as shown in FIG. 4(A) may be repeatedly arranged along a line direction and a column direction. Each of the pixels P1 to P9 is composed of two sub-pixels having different colors and does not include the W sub-pixel. 4(B) shows apertures AP of subpixels disposed along a straight line in each of the line direction (X) and column direction (Y) of the pixel array. 4(C) shows a black matrix (BM) applied to non-opening areas.

First to third pixels P1 to P3 are disposed on the first line L1. The first pixel P1 includes an R sub-pixel and a G sub-pixel. The B data of the first pixel P1 is distributed in B sub-pixels of other pixels close to the first pixel P1. The second pixel P2 includes a B sub-pixel and an R sub-pixel. The G data of the second pixel P2 is distributed in B sub-pixels of other pixels close to the second pixel P2. The third pixel P3 includes a G sub-pixel and a B sub-pixel. R data of the third pixel P3 is distributed in R sub-pixels of other pixels close to the third pixel P3.

The fourth to sixth pixels P4 to P6 are disposed on the second line L2. The fourth pixel P4 includes a B sub-pixel and an R sub-pixel. The fifth pixel P5 includes a G sub-pixel and a B sub-pixel. The sixth pixel P6 includes an R sub-pixel and a G sub-pixel.

The seventh to ninth pixels P7 to P9 are disposed on the third line L3. The seventh pixel P7 includes a G sub-pixel and a B sub-pixel. The eighth pixel P8 includes an R sub-pixel and a G sub-pixel. The ninth pixel P9 includes a B sub-pixel and an R sub-pixel.

FIG. 5 shows horizontal and vertical lines in which white and black colors alternate in line and column directions in the pixel array of FIG. 4 . According to the color arrangement shown in FIG. 4 , since subpixels are arranged in the order of RGB in the line direction (X) and in the order of RBG in the column direction (Y), white can be expressed in each of the line direction (X) and the column direction (Y). can In VESA (Video-Electronics Standards Association), resolution certification is determined by how precisely white patterns and black patterns can be expressed in horizontal and vertical lines. Therefore, since white and black horizontal lines of 1 pixel thickness are well expressed in the pixel array of FIG. 4 , there is no problem in verifying the resolution of pixels as shown in FIG. 4 .

6 to 8 are diagrams showing an example of a data compensating method in the pixel array shown in FIG. 4 .

6 to 8, the present invention multiplies the area ratio occupied by three pixels in the unit pixel group area PG partitioned by virtual diagonal lines BL by the same color data for each pixel, and the sum thereof Compensation data can be determined by

Virtual diagonal lines BL pass through half points between sub-pixels of the same color between adjacent pixels. The positions of the diagonal lines BL are shifted according to the color. The examples of FIGS. 6 to 8 are unit pixel regions PG when determining compensation data of R data.

The horizontal length of the unit pixel group region PG is the length between two adjacent diagonal lines BL and is equal to the sum of the horizontal lengths of three subpixels. The vertical length of the unit pixel group region PG is equal to the width W of one line of the display panel 100 . The first to third pixels Pa, Pb, and Pc are present in the unit pixel group area PG.

Pixel areas within the unit pixel group area PG are defined by horizontal pixel boundary lines PL and vertical pixel boundary lines PL shown in FIG. 7 . If the horizontal pixel boundary lines PL and the vertical pixel boundary lines are straight lines, two color subpixels exist in one pixel area.

In FIG. 6 , R data to be written in the R sub-pixel of the second pixel Pb may be calculated and generated in the following manner.

R = (Ra*A) + (Rb*B)+ (Rc*C)

Here, Ra is R data of the first pixel Pa, Rb is R data of the second pixel Pb, and Rc is R data of the third pixel Pc. A is the area ratio occupied by the first pixel Pa in the unit pixel group area PG, and B is the area ratio occupied by the first pixel Pc in the unit pixel group area PG.

In FIGS. 7 and 8 , numbers indicate area ratios of first to third subpixels existing in the pixel group regions PG when R compensation data ①, ②, and ③ are calculated. FIG. 8 is an example in which the vertical pixel boundary line PL is shifted by 1 sub-pixel compared to FIG. 7 .

A method of determining compensation data for G and B data is also substantially the same as the method for compensating R data. When calculating compensation data of G data, virtual diagonal lines BL are shifted to 1/2 points between neighboring G sub-pixels. When calculating compensation data of B data, virtual diagonal lines BL are shifted to 1/2 points between neighboring B sub-pixels.

9 is a diagram showing a pixel array according to a second embodiment of the present invention. FIG. 10 is a diagram showing expressions of horizontal lines and vertical lines in the pixel array shown in FIG. 9. In the description of this embodiment, detailed descriptions of substantially the same parts as those of the first embodiment will be omitted.

Referring to FIGS. 9 and 10 , pixels having a color arrangement as shown in FIG. 9(A) may be repeatedly arranged along a line direction and a column direction in a pixel array. Each of the pixels is composed of two sub-pixels of different colors and does not include the W sub-pixel. 9(B) shows openings AP1 and AP2 of subpixels arranged along a straight line in each of the line direction (X) and column direction (Y) of the pixel array. 9(C) shows a black matrix (BM) applied to non-opening areas.

Color filters of sub-pixels of the same color meet between neighboring pixels in the line direction (X). Since subpixels of the same color meet on the left and right sides, the subpixels may share a color filter of the same color. The color filter size of the island pattern shared by neighboring pixels is increased. These color filters are larger than those of the prior art of FIG. 1 as well as those of the first embodiment described above. In FIG. 9 , P1 to P6 are pixels showing these characteristics.

In order to connect the color filters of adjacent sub-pixels of the same color in the line direction (X), even-numbered (or odd-numbered) sub-pixels in each of the lines L1 to L3 move up (or down) the width of 1 line. Shifted by a smaller width, adjacent sub-pixels of the same color overlap at least partially in the line direction X and are displaced from each other, and color filters of the sub-pixels are connected to each other. 9 is an example in which the even-th sub-pixels C2, C4, and C6 are shifted upward by a width of 1/2 of one line. In this case, at 1000 PPI or more, the horizontal length of the island pattern color filter becomes 24 μm, twice as large as the conventional 12 μm.

As shown in FIG. 9 , in order to arrange the openings AP1 and AP2 in a straight line in a structure in which subpixels of the same color meet on adjacent lines, the locations of the openings in the adjacent subpixels are asymmetrical. In the example of FIG. 9 , the opening AP1 in the odd-numbered subpixels C1 , C3 , and C5 is shifted upward from the center of the corresponding subpixel. On the other hand, in the even-th sub-pixels C2, C4, and C6, the opening AP2 is shifted downward from the center of the corresponding sub-pixel.

FIG. 10 shows horizontal and vertical lines in which white and black colors alternate in line and column directions in the pixel array shown in FIG. 9 . According to the color arrangement shown in FIG. 9 , since subpixels are arranged in the order of RGB in the line direction (X) and in the order of RBG in the column direction (Y), white can be expressed in each of the line direction (x) and the column direction (Y). can In VESA (Video-Electronics Standards Association), resolution certification is determined by how precisely white patterns and black patterns can be expressed in horizontal and vertical lines. Therefore, since white and black horizontal lines of 1 pixel thickness are well expressed in the pixel array of FIG. 9 , there is no problem in verifying the resolution of the pixels as shown in FIG. 9 .

11 to 14 are diagrams illustrating an example of a data compensating method in the pixel array shown in FIG. 9 .

11 to 14, the present invention multiplies the area ratio occupied by three pixels by the same color data of the three pixels in the unit pixel group area PG partitioned by virtual diagonal lines BL, Compensation data can be determined by the sum.

Virtual diagonal lines BL pass through 1/2 points between sub-pixels of the same color. The positions of the diagonal lines BL are shifted according to the color. Examples of FIGS. 11 to 14 are unit pixel areas PG when determining compensation data of R data.

The horizontal length of the unit pixel group region PG is the length between two adjacent diagonal lines BL and is equal to the sum of the horizontal lengths of three subpixels. The vertical length of the unit pixel group region PG is equal to the width (W) of 2 lines of the display panel 100 . Three pixels exist in this unit pixel group area PG. As in the above-described embodiment, the method of generating the RGB compensation data may be generated by summing the result obtained by multiplying the same color data of pixels existing in the unit pixel area PG by the area ratio.

In FIGS. 11 to 14 , numbers represent area ratios of pixels existing in the pixel group regions PG when calculating the R compensation data ①, ②, ③. One pixel area has a size of two sub-pixels defined by horizontal pixel boundary lines PL and vertical pixel boundary lines in FIGS. 11 to 14 . As shown in FIGS. 11 to 14 , if the horizontal pixel boundary lines PL and the vertical pixel boundary lines are straight, one pixel area is a rectangle unlike the actual pixel shape, and thus three color subpixels exist in that pixel area.

11 to 14 show area ratios that vary when the pixel group area PG is the same and the pixel boundary lines PL defining the pixel area are shifted. Therefore, if the method of setting the pixel group area PG and the pixel area is changed, the compensation value of the data may be different. Data compensation methods can be optimized through image quality experiments.

Hereinafter, a pixel structure of a display device according to an embodiment of the present invention will be described based on a Fringe Field Switching (FFS) mode of a liquid crystal display device. Meanwhile, it should be noted that the display device of the present invention is not limited to a liquid crystal display device because it can be applied to any display device having an island pattern color filter at high PPI as well as a liquid crystal display device.

15 is a plan view showing a structure of one sub-pixel in the display device of the present invention. FIG. 16 is a cross-sectional view of a subpixel taken along line “I-I” in FIG. 15 .

Referring to FIGS. 15 and 16 , a subpixel is defined by a gate line GL and a data line DL crossing the lower substrate GLS with the intermediate insulating layer INT interposed therebetween. The pixel electrode PXL and the common electrode COM overlap with the fourth passivation layer PAS4 therebetween so that a fringe field can be applied between the pixel electrode PXL and the common electrode COM. One or more pixel electrodes PXL may be separated from the opening AP of the subpixel. The sub-pixel size of high PPI displays is small. For this reason, the pixel electrode PXL may be formed as one electrode pattern without being separated from the opening AP as shown in FIG. 15 .

In each sub-pixel, the data line DL and the pixel electrode PXL are connected to a TFT. Basically, only one TFT can be implemented, but two TFTs ( T1, T2) are preferably connected in series.

The first TFT T1 includes a source connected to the data line DL, a drain connected to the source of the second TFT T2, and a gate integrated with the gate line GL. The second TFT T2 includes a source connected to the data line DL, a source connected to the drain of the first TFT T1, and a gate integrated with the gate line GL. The drain of the first TFT T1 and the source of the second TFT T2 are connected through the semiconductor pattern SEMI.

The gates of the first and second TFTs T1 and T2 are not branched from the gate line GL and are used as part of the gate line in order to increase the aperture ratio AP of the subpixel. To this end, the semiconductor pattern SEMI in the sub-pixel is formed in a pattern crossing the two TFT channel regions A1 and A2 on the same gate line GL. The semiconductor pattern SEMI contacts the data line DL through the first contact hole CN1 and intersects the gate line GL at two channel regions A1 and A2.

A light blocking layer LS is formed on the substrate GLS. Each of the TFTs T1 and T2 may be implemented as an LTPS TFT. The LTPS TFT may be formed with a top gate structure. In this case, a photo current may flow due to back light introduced from the bottom to the top of the substrate GLS. To prevent this problem, a light blocking layer LS may be disposed in a portion where the channel regions A1 and A2 of each of the TFTs T1 and T2 are to be formed.

The buffer layer BUF is formed on the entire surface of the substrate GLS to cover the light blocking layer LS. A semiconductor pattern SEMI is formed on the buffer layer BUF.

A gate insulating material is deposited and patterned on the entire surface of the substrate GLS on which the semiconductor pattern SEMI is formed, so that a gate insulating layer GI covering the semiconductor pattern SEMI is formed on the buffer layer BUF. A gate metal is deposited and patterned on the gate insulating film GI to form a gate metal pattern on the gate insulating film GI. The gate metal pattern includes a gate line GL.

The semiconductor pattern SEMI is divided into a region overlapping the gate line GL and an exposed region otherwise. In order to lower the resistance of the exposed region of the semiconductor pattern SEMI without overlapping with the gate line GL, impurities may be implanted into the exposed region to make a portion of the semiconductor pattern SEMI a conductor. The doped portion of the semiconductor pattern SEMI includes a source contact region and a drain contact region. The semiconductor pattern SEMI overlapping the gate line GL is defined as the channel regions A1 and A2 of the TFTs T1 and T2.

An intermediate insulating layer INT is deposited on the entire surface of the substrate GLS on which the gate line GL is formed. First and second contact holes CN1 and CN2 are formed in the intermediate insulating layer INT and the gate insulating layer GI. The first contact hole CN1 exposes a source contact region of the semiconductor pattern SEMI. The second contact hole CN2 exposes a drain contact region of the semiconductor pattern SEMI.

A first source-drain metal is deposited and patterned on the intermediate insulating layer INT to form a first source-drain metal pattern SD1 on the intermediate insulating layer INT. The first source-drain metal pattern SD1 includes a data line DL and a source of the first TFT T1 connected to the data line DL. The first source-drain metal pattern SD1 contacts the source contact region of the semiconductor pattern SEMI through the first contact hole CN1. A first passivation layer PAS1 is deposited on the intermediate insulating layer INT to cover the first source-drain metal pattern SD1.

A second source-drain metal is deposited and patterned on the first passivation layer PAS1 to form a second source-drain metal pattern SD2 on the first passivation layer PAS1. The second source-drain metal pattern SD2 includes the drain of the second TFT T2. The second source-drain metal pattern SD2 contacts the drain contact region of the semiconductor pattern SEMI through the second contact hole CN2. A second passivation layer PAS2 is deposited on the first passivation layer PAS1 to cover the second source-drain metal pattern SD2.

In the sub-pixel of the high resolution/high PPI model, since the size of the sub-pixel is small, if the first and second source-drain metal patterns SD1 and SD2 are formed as the same metal pattern on the same layer, the process margin is It is small and can be short circuited. Therefore, in the case of a high resolution/high PPI model, it is preferable to separate the first and second source-drain metal patterns SD1 and SD2 with the first passivation layer PAS1 interposed therebetween.

A third passivation layer PAS3 is formed on the second passivation layer PAS2. The third passivation layer PAS3 is formed on the second passivation layer PAS2 to cover the second source-drain metal pattern SD2. The third passivation layer PAS3 includes the first passivation layer hole PH1. The first passivation layer hole PH1 exposes a portion of the second passivation layer PAS2 on the pixel electrode contact area on the second source-drain metal pattern SD2. The third passivation layer PAS3 may be formed of an organic insulating layer having a low dielectric constant such as photo acryl.

A common electrode COM is formed on the third passivation layer PAS3. A fourth passivation layer PAS4 is deposited on the third passivation layer PAS3 to cover the common electrode COM. The second and fourth passivation layers PAS2 and PAS4 are etched to form a second passivation layer hole PH2 penetrating the fourth passivation layer PAS4 and the second passivation layer PAS2. A pixel electrode contact area of the second source-drain metal pattern SD2 is exposed through the second passivation layer hole PH2.

A pixel electrode PXL is formed on the fourth passivation layer PAS4 . The pixel electrode PXL is in contact with the pixel electrode contact area of the second source-drain metal pattern SD2 through the second passivation layer hole PH2.

In each of the above embodiments, one sub-pixel structure may be implemented as shown in FIGS. 15 and 16 . FIG. 17 is a plan view showing a planar structure of 2*2 subpixels in the pixel array shown in FIG. 4 . FIG. 18 is an equivalent circuit diagram of 3*3 subpixels in the pixel array shown in FIG. 4 . FIG. 19 is a plan view showing a planar structure of 2*2 subpixels in the pixel array shown in FIG. 9 . FIG. 20 is an equivalent circuit diagram of 3*3 subpixels in the pixel array shown in FIG. 9 .

Through the above description, those skilled in the art will understand that various changes and modifications are possible without departing from the spirit of the present invention. Therefore, the technical scope of the present invention should not be limited to the contents described in the detailed description of the specification, but should be determined by the claims.

100: display panel 102: data driving unit
104: gate driver 106: timing controller
110: host system

Claims (13)

A display having a pixel array in which a plurality of data lines, a plurality of gate lines, and a plurality of red sub-pixels, a plurality of green sub-pixels, a plurality of blue sub-pixels, and thin film transistors disposed in each of the sub-pixels are disposed. panel; and
a display panel driving circuit for writing data of an input image to sub-pixels of the display panel;
The pixels of the display panel include two sub-pixels having different colors among the sub-pixels;
Red sub-pixels, green sub-pixels, and blue sub-pixels are disposed in each of a line direction and a column direction crossing each other in the pixel array;
Adjacent subpixels on each line of the display panel are offset from each other by a width smaller than the width of one line, and island pattern color filters are connected between the adjacent subpixels of the same color, so that the adjacent subpixels of the same color are connected to each other. The color filter of the island pattern is shared between them,
In each of the sub-pixels, the thin film transistor includes first and second thin film transistors connected between one data line and one pixel electrode. According to claim 1,
Sub-pixels are arranged in the order of the red sub-pixel, the green sub-pixel, and the blue sub-pixel along the line direction;
Sub-pixels are arranged in the order of the red sub-pixel, the blue sub-pixel, and the green sub-pixel along the column direction;
A display device in which the adjacent sub-pixels of the same color are connected to each other in a diagonal direction. According to claim 2,
A display device in which openings of the subpixels are disposed along a straight line in each of the line direction and the column direction. According to claim 1,
A first line of the display panel includes a first pixel having the red subpixel and the green subpixel, a second pixel having the blue subpixel and the red subpixel, and a green subpixel and the blue subpixel. The pixels are arranged in order of a third pixel,
The second line of the display panel includes a fourth pixel having the blue subpixel and the red subpixel, a fifth pixel having the green subpixel and the blue subpixel, and a red subpixel and the green subpixel. The pixels are arranged in order of a sixth pixel,
A third line of the display panel includes a seventh pixel having the green subpixel and the blue subpixel, an eighth pixel having the red subpixel and the green subpixel, and the blue subpixel and the red subpixel. A display device in which the pixels are arranged in the order of a ninth pixel. delete A display having a pixel array in which a plurality of data lines, a plurality of gate lines, and a plurality of red sub-pixels, a plurality of green sub-pixels, a plurality of blue sub-pixels, and thin film transistors disposed in each of the sub-pixels are disposed. panel; and
a display panel driving circuit for writing data of an input image to sub-pixels of the display panel;
The pixels of the display panel include two sub-pixels having different colors among the sub-pixels;
Red sub-pixels, green sub-pixels, and blue sub-pixels are disposed in each of a line direction and a column direction crossing each other in the pixel array;
Adjacent subpixels on each line of the display panel are offset from each other by a width smaller than the width of one line, and island pattern color filters are connected between the adjacent subpixels of the same color, so that the adjacent subpixels of the same color are connected to each other. A display device in which the color filter of the island pattern is shared among the display devices. delete According to claim 6,
Sub-pixels are arranged in the order of the red sub-pixel, the green sub-pixel, and the blue sub-pixel along the line direction;
Sub-pixels are arranged in the order of the red sub-pixel, the blue sub-pixel, and the green sub-pixel along the column direction;
A display device in which the adjacent sub-pixels of the same color are connected to each other in a diagonal direction. According to claim 8,
A display device in which openings of the subpixels are disposed along a straight line in each of the line direction and the column direction. According to claim 9,
A display device in which subpixels adjacent to each of the lines of the display panel are offset from each other by a width of 1/2 of one line. According to claim 10,
In odd-numbered subpixels, the opening is shifted upward from the center of the subpixel;
A display device in which the openings in even-th sub-pixels are shifted downward from the center of the sub-pixels. According to claim 6,
A first line of the display panel includes a first pixel having the red subpixel and the green subpixel, a second pixel having the blue subpixel and the red subpixel, and a green subpixel and the blue subpixel. The pixels are arranged in order of a third pixel,
The second line of the display panel includes a fourth pixel having the blue subpixel and the red subpixel, a fifth pixel having the green subpixel and the blue subpixel, and a red subpixel and the green subpixel. The pixels are arranged in order of a sixth pixel,
A third line of the display panel includes a seventh pixel having the green subpixel and the blue subpixel, an eighth pixel having the red subpixel and the green subpixel, and the blue subpixel and the red subpixel. A display device in which the pixels are arranged in the order of a ninth pixel. According to claim 1 or 6,
The display panel driving circuit
determining compensation data by summing results obtained by multiplying the same color data for each pixel in the unit pixel group by an area ratio occupied by three pixels defined in a unit pixel group area partitioned by virtual diagonal lines;
The virtual diagonal lines pass through 1/2 points between sub-pixels of the same color between adjacent pixels.

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