KR102360821B1 - Display device - Google Patents

Abstract

The display device of the present invention includes first and second sub-pixels disposed on an N-th line (N is a positive integer), third and fourth sub-pixels disposed on an N+1-th line below the N-th line, and and a non-opening area disposed between the Nth line and the N+1th line. The non-opening region includes an nth (n is a positive integer) gate line connected to the first and second thin film transistors, an n+1th gate line connected to the third and fourth thin film transistors, and the first thin film transistor A first contact hole for connecting the pixel electrode of the first sub-pixel, a second contact hole for connecting the second thin film transistor to the pixel electrode of the second sub-pixel, and the third thin film transistor for connecting the third sub-pixel a third contact hole connecting the pixel electrode, a fourth contact hole connecting the fourth thin film transistor to the pixel electrode of the fourth sub-pixel, and a spacer disposed between the first to fourth contact holes; .

Description

display device {DISPLAY DEVICE}

The present invention relates to a display device including a contact hole and a spacer for connecting a thin film transistor (hereinafter referred to as "TFT") and a pixel electrode.

Liquid Crystal Display Device (LCD), Organic Light Emitting Diode Display (OLED Display), Plasma Display Panel (PDP), Electrophoretic Display Device (EPD) Various flat panel display devices are being developed. A liquid crystal display displays an image by controlling an electric field applied to liquid crystal molecules according to a data voltage. In an active matrix driving type liquid crystal display device, a thin film transistor (hereinafter, referred to as “TFT”) is formed for each pixel.

The liquid crystal display includes a liquid crystal display panel, a backlight unit irradiating light to the liquid crystal display panel, a source drive integrated circuit (hereinafter referred to as “IC”) for supplying data voltages to data lines of the liquid crystal display panel, and liquid crystal display. A gate drive IC for supplying a gate pulse (or scan pulse) to the gate lines (or scan lines) of the display panel, a control circuit for controlling the ICs, a light source driving circuit for driving a light source of a backlight unit, etc. be prepared

Each of the pixels includes a red (Red:R) sub-pixel, a green (Green:G) sub-pixel, and a blue (Blue:B) sub-pixel for color implementation. The pixels may further include a white (W) sub-pixel. Hereinafter, a display device in which pixels are divided into RGBW sub-pixels is referred to as an “RGBW type display device”. The W sub-pixel may lower the luminance of the backlight unit by increasing the luminance of each pixel, thereby reducing power consumption of the liquid crystal display.

Since mobile devices are often used outdoors, a display device used for mobile devices must have excellent outdoor visibility. In order to improve outdoor visibility, there is a method of increasing the luminance of pixels. When the brightness of the backlight unit is increased to increase the luminance of the pixels, power consumption is high. Therefore, a method of increasing the luminance by improving the transmittance of the pixels is preferable. In order to increase the transmittance of the pixels, the aperture ratio of the pixels may be increased.

Pixels are difficult to increase the aperture ratio due to signal wiring, TFT, contact hole, spacer, and the like. Here, the signal wiring means data lines and gate lines connected to the pixels. In general, the pixel electrode and the TFT are separated with an insulating layer interposed therebetween. The pixel electrode is connected to the TFT through a contact hole passing through the insulating film. When the protective film covering the TFT is formed as an organic passivation layer, the size of the contact hole increases because the thickness is thick. As the contact hole increases, the aperture ratio of the pixels decreases. The spacer is disposed between the two substrates of the display panel to maintain a cell gap of the liquid crystal layer. When the contact hole becomes large, the spacer cannot be disposed over the contact hole. Spacers can be placed in the aperture area of the pixel avoiding the contact hole, but this results in a reduction in the aperture area of the pixel due to the spacer.

As a display device develops into a high resolution, a pixel per inch (PPI) of a pixel increases and a pixel size decreases. Although the pixel size is reduced, since it is difficult to reduce the size of the signal wiring, TFT, contact hole, spacer, etc., the aperture ratio of the pixel becomes smaller at high resolution.

The present invention provides a display device capable of improving transmittance of pixels.

The display device of the present invention includes first and second sub-pixels disposed on an N-th line (N is a positive integer), third and fourth sub-pixels disposed on an N+1-th line below the N-th line, and and a non-opening area disposed between the Nth line and the N+1th line.

The non-opening region includes an nth (n is a positive integer) gate line connected to the first and second thin film transistors, an n+1th gate line connected to the third and fourth thin film transistors, and the first thin film transistor A first contact hole for connecting the pixel electrode of the first sub-pixel, a second contact hole for connecting the second thin film transistor to the pixel electrode of the second sub-pixel, and the third thin film transistor for connecting the third sub-pixel a third contact hole connecting the pixel electrode, a fourth contact hole connecting the fourth thin film transistor to the pixel electrode of the fourth sub-pixel, and a spacer disposed between the first to fourth contact holes; .

In the display device of the present invention, the spacer arrangement space is secured in the non-opening area by summing the non-opening areas of the pixels adjacent up and down. As a result, in the present invention, the transmittance of pixels can be improved because the spacer can be disposed in the non-open area without the need to arrange the spacer at a position that encroaches on the open area of the pixel even if the pixel size is reduced and the contact hole is large at high resolution. have.

1 is a block diagram illustrating a display device according to an embodiment of the present invention.
2 is an equivalent circuit diagram illustrating a part of a pixel array according to an embodiment of the present invention.
3 is a diagram illustrating a planar structure of a pixel according to a first embodiment of the present invention.
4 is a diagram illustrating a planar structure of a pixel according to a second embodiment of the present invention.
FIG. 5 is a cross-sectional view showing a cross-sectional structure of a non-opening region taken along line "I-I'" in FIGS. 3 and 4;
6 is a view showing a color filter arrangement according to the first embodiment of the present invention.
7 is a view showing a color filter arrangement according to a second embodiment of the present invention.

Hereinafter, preferred embodiments according to the present invention will be described in detail with reference to the accompanying drawings. Like reference numerals refer to substantially identical elements throughout. In the following description, if it is determined that a detailed description of a known function or configuration related to the present invention may unnecessarily obscure the gist of the present invention, the detailed description thereof will be omitted.

1 and 2 , the display device of the present invention includes a display panel 100 having a pixel array formed thereon, and a display panel driving circuit for writing input image data to the display panel 100 . A backlight unit for uniformly irradiating light to the display panel 100 may be disposed under the display panel 100 .

The display panel 100 includes an upper substrate and a lower substrate facing each other with a liquid crystal layer LC interposed therebetween. The pixel array of the display panel 100 includes pixels arranged in a matrix form by a cross structure of data lines 11 and gate lines 12 . In FIG. 2 , S1 to S4 are data lines 11 , and G1 to G4 are gate lines 12 . Each of the pixels includes an R sub-pixel, a G sub-pixel, a B sub-pixel, and a W sub-pixel.

The lower substrate of the display panel 100 includes data lines 11 , gate lines 12 , a TFT, a pixel electrode 1 connected to the TFT, and a storage capacitor connected to the pixel electrode 1 . Cst) and the like. The TFT and the pixel electrode 1 are connected through a contact hole penetrating the insulating layer. In FIG. 1 , “Clc” denotes a capacitance formed in the liquid crystal layer between the pixel electrode 1 and the common electrode 2 . The TFT is a switch element that supplies a data voltage applied through the data line 11 to the pixel electrode 1 in response to a gate pulse from the gate line. Each of the sub-pixels uses liquid crystal molecules driven by a voltage difference between the pixel electrode 1 to which the data voltage for charging the data voltage is supplied through the TFT and the common electrode 2 to which the common voltage Vcom is applied. Controls the amount of light transmitted.

The TFTs formed on the lower substrate of the display panel 100 may be implemented with an amorphous silicon (a-Si) TFT, a low temperature poly silicon (LTPS) TFT, an oxide TFT, or the like. The TFTs are connected 1:1 to the pixel electrode of the sub-pixels.

A color filter array including a black matrix (BM) and a color filter (CF) is formed on the upper substrate of the display panel 100 . The common electrode 2 is formed on the upper substrate in the case of vertical electric field driving methods such as TN (Twisted Nematic) mode and VA (Vertical Alignment) mode, IPS (In-Plane Switching) mode and FFS (Fringe Field Switching) In the case of a horizontal electric field driving method such as mode, it may be formed on the lower substrate together with the pixel electrode.

A polarizing plate is attached to each of the upper and lower substrates of the display panel 100 , and an alignment layer for setting a pre-tilt angle of the liquid crystal is formed. The spacer is disposed between the upper substrate and the lower substrate to maintain a cell gap of the liquid crystal layer. The spacer may be implemented as a column spacer that can be patterned at a desired position.

The display device of the present invention may be implemented in any form, such as a transmissive liquid crystal display, a transflective liquid crystal display, or a reflective liquid crystal display. A backlight unit is required in a transmissive liquid crystal display device and a transflective liquid crystal display device. The backlight unit may be implemented as a direct type backlight unit or an edge type backlight unit.

The display panel driving circuit writes input image data into pixels. The display panel driving circuit includes a data driver 102 , a gate driver 104 , and a timing controller 106 .

The data driver 102 includes a plurality of source drive ICs. The data output channels of the source drive ICs are connected to the data lines 11 of the pixel array. The source drive ICs receive input image data from the timing controller 106 . Digital video data transmitted to the source drive ICs includes R data, G data, B data, and W data. The source drive ICs convert RGBW digital video data of an input image into positive/negative gamma compensation voltages under the control of the timing controller 106 to output positive/negative data voltages. Output voltages of the source drive ICs are supplied to the data lines S1 to Sm.

The gate driver 104 sequentially supplies gate pulses to the gate lines 12 under the control of the timing controller 106 . The gate pulse output from the gate driver 104 is synchronized with the data voltage. The gate driver 104 may be directly formed on the lower substrate of the display panel 100 together with the pixel array in order to reduce the cost of the IC.

The timing controller 106 converts RGB data of an input image received from the host system 110 into RGBW data using a white gain calculation algorithm and transmits the converted RGB data to the data driver 102 . The timing controller 106 receives timing signals synchronized with data of an input image. The timing signals include a vertical synchronization signal Vsync, a horizontal synchronization signal Hsync, a data enable signal DE, and a main clock CLK. The timing controller 106 controls operation timings of the data driver 102 and the gate driver 104 based on the timing signals Vsync, Hsync, DE, and DCLK. The white gain calculation algorithm may be applied to the white gain calculation algorithms proposed in Korean Patent Publication Nos. 10-2006-0117025, 10-2006-0133194, 10-2007-0011830, 10-2007-0080140, etc. previously filed by the applicant of the present application. .

The host system 110 may be any one of a television (Television) system, a set-top box, a navigation system, a DVD player, a Blu-ray player, a personal computer (PC), a home theater system, and a phone system.

According to the present invention, non-opening regions are combined at the boundary between the pixels by arranging the TFTs and the signal wirings 11 and 12 between the pixels adjacent to each other in a mirror-symmetrical manner as shown in FIGS. 2 to 4 . It should be noted that the size of the enlarged non-aperture area between the upper and lower neighboring pixels is not greater than the sum of the sizes of each of the upper and lower non-aperture areas. The present invention places a spacer in an enlarged non-aperture area between up-and-down neighboring pixels. According to the present invention, the spacer can be disposed in the non-opening area even if the contact holes are enlarged due to the application of the organic passivation layer. Accordingly, in the present invention, even if the pixel size is reduced and the contact hole is increased at high resolution, the transmittance of pixels can be increased because the spacer can be disposed in the non-opening area without the need to arrange the spacer at a position encroaching on the open area of the pixel.

In the display device of the present invention, the first and second sub-pixels (P3 and P4 in FIGS. 3 and 4), the N+th sub-pixels (P3 and P4 in FIGS. It includes third and fourth sub-pixels arranged on one line (L3 in FIGS. 3 and 4 ), and a non-opening region (B in FIGS. 3 and 4 ) arranged between an N-th line and an N+1-th line. The third sub-pixel is a sub-pixel of the N+1th line disposed below the first sub-pixel with a non-opening region interposed therebetween. The fourth sub-pixel is a sub-pixel of the N+1th line disposed below the second sub-pixel with the non-opening region interposed therebetween.

The non-opening region includes an n-th (n is a positive integer) gate line connected to the first and second TFTs, an n+1-th gate line connected to the third and fourth TFTs, and the first TFT connected to the first sub-pixel. A first contact hole (CH1 in FIGS. 3 and 4) connected to the pixel electrode, a second contact hole (CH2 in FIGS. 3 and 4) connecting the second TFT to the pixel electrode of the second sub-pixel, a third TFT A third contact hole (CH3 in FIGS. 3 and 4) for connecting to the pixel electrode of the third sub-pixel, and a fourth contact hole (FIGS. 3 and 4) for connecting the fourth TFT to the pixel electrode of the fourth sub-pixel in CH4). A spacer (CS in FIGS. 3 and 4 ) is disposed between the first to fourth contact holes.

3 is a diagram illustrating a planar structure of a pixel according to a first embodiment of the present invention. 4 is a diagram illustrating a planar structure of a pixel according to a second embodiment of the present invention.

Referring to FIGS. 3 and 4 , the display panel 100 includes a non-opening area B that is merged between vertically adjacent pixels.

When viewed in a plan view of the display panel 100 , the pixels of the two lines L1 and L2 positioned on the non-opening area B may secure a wide open area A without the non-opening area B . Also, the pixels disposed on the two lines L3 and L4 under the non-opening area B may secure a wide open area A without the non-opening area. The non-open area B is covered by the black matrix. The non-opening area further includes a vertical non-opening area along the data lines S1 to S3.

The first line L1 includes first and second sub-pixels P1 and P2. The second line L2 includes third and fourth sub-pixels P3 and P4. There is no non-opening area at the boundary between the first sub-pixel P1 and the third sub-pixel P3 disposed on the two vertically adjacent lines L1 and L2. Accordingly, the black matrix is not formed at the boundary between the first sub-pixel P1 and the third sub-pixel P3 disposed on the two vertically adjacent lines L1 and L2.

A non-opening area B is disposed between the pixels of the second and third lines L3 . The gate lines Gn and Gn+1, the TFT, and the spacer CS are disposed in the non-opening region B. As shown in FIG. The pixel electrode PXL is connected to the TFT formed on the gate lines Gn and Gn+1 through the contact holes CH1 to CH4 and CH. 3 and 4, the TFT is omitted. The n-th gate line Gn is connected to the sub-pixels of the second line L2 through the first TFT. The n+1th gate line Gn+1 is connected to the sub-pixels of the third line L3 through the second TFT.

There is no non-opening area at a boundary between the sub-pixels of the third line L3 and the sub-pixels of the fourth line L4. Accordingly, the black matrix is not formed at the boundary between the sub-pixels disposed on the two vertically adjacent lines L3 and L4.

There is a difference between the pixel structure of FIG. 3 and the pixel structure of FIG. 4 in the number of liquid crystal domains of sub-pixels adjacent to each other. Here, one liquid crystal domain is a liquid crystal region in which liquid crystal molecules are aligned at the same alignment angle.

In FIG. 3 , the liquid crystal initial alignment angle of the first sub-pixel P1 is different from the liquid crystal initial alignment angle of the third sub-pixel P3 . Accordingly, the first sub-pixel P1 and the third sub-pixel P3 are divided into two liquid crystal domains. The liquid crystal molecules of the first sub-pixel P1 form a first liquid crystal domain that is initially aligned in a first direction, and the liquid crystal molecules of the third sub-pixel P3 form a first liquid crystal domain that is initially aligned in a second direction different from the first direction. 2 to form a liquid crystal domain. The multi-domain can implement a wide viewing angle because the viewer does not feel a difference in refractive index of the liquid crystal even when looking at it from a wide viewing angle.

In FIG. 4 , the liquid crystal initial alignment angle of the first sub-pixel P1 is the same as the liquid crystal initial alignment angle of the third sub-pixel P3 . Accordingly, the first sub-pixel P1 and the third sub-pixel P3 are connected to one liquid crystal domain.

In FIG. 4 , the liquid crystal alignment angle of the pixels P1 to P4 of the first and second lines L1 and L4 and the third and fourth lines L3 and L4 to implement a multi-domain effect, that is, a wide viewing angle in FIG. 4 . ), the liquid crystal alignment angles of the pixels P1 to P4 are different. The pixels of the first and second lines L1 and L2 are driven in the first liquid crystal domain, while the pixels of the third and fourth lines L3 and L4 are driven in the first liquid crystal domain.

In FIG. 3 , the first and third sub-pixels P1 and P3 are divided into two liquid crystal domains having different initial alignment angles of liquid crystal molecules. A disclination region in which liquid crystal molecules are unstablely driven may exist between the two liquid crystal domains. The luminance of the disclination region may be lower than that of other opening regions. In contrast, the first and third sub-pixels P1 and P3 of FIG. 4 are connected to one liquid crystal domain in which the initial alignment angle of liquid crystal molecules is constant. The first and third sub-pixels P1 and P3 are connected without a black matrix. Accordingly, since the first and third sub-pixels P1 and P3 of FIG. 4 are connected to one liquid crystal domain without disclination, luminance can be further increased and the aperture ratio can be further increased compared to FIG. 3 . .

3 and 4 , the non-opening region B has the same cross-sectional structure. FIG. 5 shows the cross-sectional structure of the non-opening region B taken along the line "I-I'" in FIGS. 3 and 4 .

Referring to FIG. 5 , a lower plate of the display panel 100 includes a TFT array disposed on a lower substrate SUBS1 . The upper plate of the display panel 100 includes a color filter array disposed on an upper substrate SUBS2 . The column spacers CS may be formed on the color filter array.

The TFT array substrate includes signal wires 11 and 12 , a TFT, a pixel electrode PXL, a common electrode COM, and the like.

A light shield pattern LS is formed on the lower substrate SUBS1 , and a buffer insulating layer BUF is formed thereon. The light shielding pattern LS is disposed under the channel region in the semiconductor pattern ACT of the TFT to block external light incident through the substrate SUBS1, thereby generating a TFT generated when the semiconductor pattern ACT is exposed by external light. to prevent leakage current. The buffer insulating layer BUF is formed on the lower substrate SUBS1 to cover the light shielding pattern. The light shielding pattern LS may be formed of a metal, and the buffer insulating layer BUF may be formed of an inorganic insulating material such as SiOx or SiNx.

The semiconductor pattern ACT is covered by the gate insulating layer GI. The gate metal pattern is formed on the gate insulating layer GI. The gate metal pattern includes a gate GE of the TFT and gate lines Gn and Gn+1 connected to the gate GE. The gate insulating layer GI may be formed of an inorganic insulating material such as SiOx or SiNx.

The interlayer insulating layer INT covers the gate metal pattern. The interlayer insulating layer INT may be formed of an inorganic insulating material such as SiOx or SiNx. The source-drain metal pattern is formed on the interlayer insulating layer INT. The source-drain metal pattern includes a data line 11 and a source SE and a drain of the TFT. The source SE and the drain of the TFT are in contact with the semiconductor pattern ACT of the TFT through a contact hole penetrating the interlayer insulating layer INT and the gate insulating layer GI. The source SE of the TFT is connected to the pixel electrode PXL through the contact holes CH1 to CH4 and CH passing through the passivation layers PAS1 , PAS2 , and PAS3 . The drain of the TFT is connected to the data line.

The first passivation layer PAS1 covers the source-drain metal pattern. A second passivation layer PAS2 is formed on the first passivation layer PAS1 . The second passivation layer PAS2 is etched to expose the source SE of the TFT at the contact hole position. A common electrode COM is formed on the second passivation layer PAS2 . The third passivation layer PAS3 is formed on the second passivation layer PAS2 to cover the common electrode COM. The third passivation layer PAS3 is etched to form contact holes CH1 to CH4 and CH exposing the source SE of the TFT. A pixel electrode PXL is formed on the third passivation layer PAS3 . The common electrode COM and the pixel electrode PXL are formed of a transparent electrode material such as indium-tin oxide (ITO). The first and third passivation layers PAS1 and PAS3 may be formed of an inorganic insulating material such as SiOx or SiNx. The second passivation layer PAS2 may be formed of an organic insulating material such as photo-acryl.

A black matrix BM and a color filter CF are formed on the upper substrate SUBS2 , and a planarization layer OC and a spacer CS are formed thereon. The planarization layer OC and the spacer CS are formed of an organic insulating material. The spacer CS is disposed between the contact holes CH1 to CH4 and CH in the non-opening area B in order to avoid the contact holes CH1 to CH4 and CH without encroaching on the open area A. do. Accordingly, the spacer CS avoids the contact holes CH1 to CH4 and CH when viewed from the plane of the display panel 100 , and from the cross-sectional structure of the display panel 100 , the contact holes CH1 to CH4 , CH) does not overlap.

6 is a view showing a color filter arrangement according to the first embodiment of the present invention.

Referring to FIG. 6 , a red color filter is disposed in the R sub-pixel. A green color filter is disposed in the G sub-pixel, and a blue color filter is disposed in the G sub-pixel. Neighboring sub-pixels have different colors. For this reason, the color filter is divided into sub-pixel units. A black matrix BM is disposed between color filters having different colors to prevent optical crosstalk. The upper substrate SUBS2 of the W sub-pixel may be filled with the planarization layer OC without a color filter, or a separate transparent insulating pattern may be formed between the upper substrate SUBS2 and the planarization layer OC to compensate for a step difference.

7 is a view showing a color filter arrangement according to a second embodiment of the present invention.

Referring to FIG. 7 , a red color filter (CFR) is disposed in the R sub-pixel. A green color filter CFG is disposed in the G sub-pixel, and a blue color filter CFB is disposed in the B sub-pixel. The sub-pixels adjacent to the top and bottom are sub-pixels of the same color. Accordingly, the same color filter is shared by sub-pixels adjacent to each other. When neighboring sub-filters share a color filter, the aperture area is further expanded because there is no black matrix (BM) between the color filters.

When the pixel structure shown in FIG. 4 and the color filter arrangement shown in FIG. 7 are combined, the effect of expanding the aperture ratio of the pixel is further increased, thereby further increasing the transmittance of the pixel.

Those skilled in the art from the above description will be able to see that various changes and modifications are possible without departing from the technical spirit of the present invention. Accordingly, the technical scope of the present invention should not be limited to the contents described in the detailed description of the specification, but should be defined by the claims.

100: display panel 102: data driver
104: gate driver 106: timing controller
110: host system CH1~CH4, CH: contact hole
CS: spacer

Claims (8)

first and second sub-pixels disposed on an N-th line (N is a positive integer);
third and fourth sub-pixels disposed on an N+1-th line under the N-th line; and
a non-opening area disposed between the N-th line and the N+1-th line;
The non-opening area is
an nth (n is a positive integer) gate line connected to the first and second thin film transistors;
an n+1th gate line connected to the third and fourth thin film transistors;
a first contact hole connecting the first thin film transistor to the pixel electrode of the first sub-pixel;
a second contact hole connecting the second thin film transistor to the pixel electrode of the second sub-pixel;
a third contact hole connecting the third thin film transistor to the pixel electrode of the third sub-pixel;
a fourth contact hole connecting the fourth thin film transistor to the pixel electrode of the fourth sub-pixel; and
and a spacer disposed between the first to fourth contact holes. The method of claim 1,
fifth and sixth sub-pixels disposed on an N-1 th line above the N th line;
seventh and eighth sub-pixels disposed on an N+2th line under the N+1th line;
the first and fifth sub-pixels are vertically adjacent without a non-aperture region;
the second and sixth sub-pixels are vertically adjacent without a non-aperture region;
the third and seventh sub-pixels are vertically adjacent without a non-aperture region;
A display device in which the fourth and eighth sub-pixels are vertically adjacent to each other without a non-aperture region. The method of claim 1,
The first and fifth sub-pixels are divided into two liquid crystal domains having different initial alignment angles of liquid crystals;
The second and sixth sub-pixels are divided into two liquid crystal domains having different initial alignment angles of liquid crystals;
The third and seventh sub-pixels are divided into two liquid crystal domains having different initial alignment angles of liquid crystals;
The display device in which the fourth and eighth sub-pixels are divided into two liquid crystal domains having different initial alignment angles of liquid crystals. The method of claim 1,
The first and fifth sub-pixels are connected to one liquid crystal domain having the same initial alignment angle of the liquid crystal,
The second and sixth sub-pixels are connected to one liquid crystal domain having the same initial alignment angle of the liquid crystal,
The third and seventh sub-pixels are connected to one liquid crystal domain having the same initial alignment angle of the liquid crystal,
A display device in which the fourth and eighth sub-pixels are connected to one liquid crystal domain having the same initial alignment angle of liquid crystal. 5. The method according to claim 3 or 4,
the first sub-pixel is a sub-pixel of a first color;
the second sub-pixel is a sub-pixel of a second color;
the fifth sub-pixel is a sub-pixel of a third color;
and the sixth sub-pixel is a sub-pixel of a fourth color. 5. The method according to claim 3 or 4,
each of the first and seventh sub-pixels is a sub-pixel of a first color;
each of the second and eighth sub-pixels is a sub-pixel of a second color;
each of the third and fifth sub-pixels is a sub-pixel of a third color;
Each of the fourth and sixth sub-pixels is a sub-pixel of a fourth color. 5. The method according to claim 3 or 4,
each of the first and fifth sub-pixels is a sub-pixel of a first color connected without a black matrix;
and each of the second and sixth sub-pixels is a sub-pixel of a second color connected without the black matrix. 5. The method according to claim 3 or 4,
each of the first and fifth sub-pixels is a sub-pixel of a first color connected without a black matrix;
each of the second and sixth sub-pixels is a sub-pixel of a second color connected without the black matrix;
each of the third and seventh sub-pixels is a sub-pixel of a third color connected without the black matrix;
and each of the fourth and eighth sub-pixels is a sub-pixel of a fourth color connected without the black matrix.

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