KR102633330B1 - Display device - Google Patents

Abstract

The present invention includes a display panel, a data driver, and a gate driver. The display panel has data lines and gate lines intersecting at an acute angle and has a non-rectangular non-rectangular pixel array. The data driver is arranged along the outermost line of the heterogeneous pixel array and connected to the data lines. The gate driver includes a gate driver disposed along the outermost line of the heterogeneous pixel array and connected to the gate lines. Each pixel of the pixel array includes an opening area located inside a pair of data lines and a transistor area adjacent to the opening area in the vertical direction where a transistor is disposed, and the horizontal width of the transistor area is greater than the horizontal width of the opening area. It is set narrowly.

Description

Display device {DISPLAY DEVICE}

The present invention relates to a display device in which a gate driving circuit is built into a display panel of a heterogeneous display device in which the substrate structure of the display panel is not rectangular.

Liquid Crystal Display Device (LCD), Organic Light Emitting Diode Display (OLED Display), Plasma Display Panel (PDP), Electrophoretic Display Device (EPD) Various flat panel display devices are commercially available.

The display device includes a pixel array on which an image is displayed, and a display panel driving circuit that writes data of the input image to the pixels. The display panel driving circuit is a data driving circuit that supplies data signals to the data lines of the pixel array, and sequentially supplies gate pulses (or scan pulses) that are synchronized with the data signals to the gate lines (or scan lines) of the pixel array. It includes a gate driving circuit (or scan driving circuit), a data driving circuit, and a timing controller that controls the gate driving circuit.

Recently, technology has been applied to embed the gate driving circuit in the display panel along with the pixel array. Hereinafter, the gate driving circuit built into the display panel along with the pixel array is referred to as the “GIP (Gate In Panel) circuit.” The GIP circuit sequentially selects lines of the pixel array on which data will be written by shifting gate pulses supplied to the gate lines using a shift register.

Demand for heterogeneous display devices is increasing. Wearable devices, flexible devices, instrument panels, etc. require display devices of various shapes that deviate from the existing rectangular shape. Commercialization technology for such heterogeneous display devices is advancing.

In heterogeneous display devices, the parasitic capacitance of the display panel may increase because data lines and gate lines often intersect outside the pixel array due to the unique design of the pixel array or the unique substrate structure of the display panel. Additionally, when the display panel driving circuit is arranged along the heterogeneous pixel array to reduce the bezel size in a heterogeneous display device, the data driver and gate driver may overlap due to the overlapping portion of the data lines and gate lines. Therefore, in order to mount the display panel driving circuit on the display panel in a heterogeneous display device, a wide bezel is required. Considering the design of the variant display device and the size of the display area, the size of the bezel, which is the non-display area, should be reduced. However, it is difficult to reduce the bezel size due to the above problems.

Accordingly, the present invention provides a heterogeneous display device that can easily mount a display panel driving circuit and reduce the bezel size.

The present invention includes a display panel, a data driver, and a gate driver. The display panel has data lines and gate lines intersecting at an acute angle and has a non-rectangular non-rectangular pixel array. The data driver is arranged along the outermost line of the heterogeneous pixel array and connected to the data lines. The gate driver includes a gate driver disposed along the outermost line of the heterogeneous pixel array and connected to the gate lines. Each pixel of the pixel array includes an opening area located inside a pair of data lines and a transistor area adjacent to the opening area in the vertical direction where a transistor is disposed, and the horizontal width of the transistor area is greater than the horizontal width of the opening area. It is set narrowly.

The present invention intersects the data lines and gate lines of a heterogeneous pixel array at an acute angle and arranges the data driver and gate driver along the outermost line of the heterogeneous pixel array, thereby creating a display panel without increasing the parasitic capacity of the pixel array and without overlapping the drivers. The driving circuit can be mounted on the display panel board, and furthermore, the bezel size of the display device can be reduced.

Additionally, the present invention can reduce the width of the transistor area and expand the opening area.

1 is a block diagram schematically showing a display device according to an embodiment of the present invention.
FIG. 2 is a diagram showing the multiplexer circuit shown in FIG. 1.
3 to 7 are diagrams showing various heterogeneous pixel arrays and a display panel driving circuit according to an embodiment of the present invention.
Figure 8 is a diagram showing data lines and gate lines crossing at an acute angle.
Figure 9 is an equivalent circuit diagram showing a pixel array.
10 is a diagram showing a partial area of a pixel array according to the first embodiment.
FIG. 11 is a plan view showing only the stair pattern wiring in FIG. 10.
FIG. 12 is a top view showing one pixel in FIG. 10.
Figure 13 is a cross-sectional view showing the cross-sectional structure of a pixel taken along the line "Ⅰ-Ⅰ'".
FIG. 14 is a diagram showing an example of the arrangement of a display panel driving circuit and signal wires of the display panel according to an embodiment of the present invention.
Figure 15 is a diagram showing a comparative example in which data lines and gate lines are orthogonal in a heterogeneous display device.
FIG. 16 is a diagram showing an example in which the display panel driving circuits are arranged in an overlapping manner when the display panel driving circuits are arranged along the outermost line of the heterogeneous pixel array in a heterogeneous display device.
Figure 17 is a diagram showing a partial area of the pixel array according to the second embodiment.
FIG. 18 is a diagram showing the first pixel shown in FIG. 17.
Figure 19 is a diagram showing the layout of first to third data lines.
Figure 20 is a diagram showing a partial area of a pixel array according to a comparative example.
Figure 21 is a schematic diagram showing the opening area and transistor area of the first and second pixels according to the present invention.

Hereinafter, preferred embodiments according to the present invention will be described in detail with reference to the attached drawings. Like reference numerals refer to substantially the same elements throughout the specification. In the following description, if it is determined that a detailed description of a known function or configuration related to the present invention may unnecessarily obscure the gist of the present invention, the detailed description will be omitted.

The display device of the present invention is implemented as a flat panel display device such as a Liquid Crystal Display (LCD), a Field Emission Display (FED), an Organic Light Emitting Display (OLED), etc. It can be. In the following embodiments, the description will focus on the liquid crystal display device, but it should be noted that the embodiment is not limited thereto.

1 and 2, the display device of the present invention includes a display panel 100 with a pixel array (ARY) formed thereon, and a display panel driving circuit for writing data of an input image into the display panel 100. Provided with

The display panel 100 includes an upper substrate and a lower substrate that face each other with a liquid crystal layer therebetween. A pixel array (AA) on which an input image is displayed is formed in the active area of the display panel 100. The pixel array AA displays an input image including pixels arranged in a matrix form by an intersection structure of data lines DL1 to DLm and gate lines GL1 to GLn. Data lines (DL1 to DLm) and gate lines (GL1 to GLm) intersect at an acute angle greater than 0° and less than 90°. The pixel array (AA) is not rectangular, but has a heterogeneous design. As shown in FIGS. 3 to 7 , the pixel array AA has a shape other than a rectangle, such as a polygon larger than a pentagon, a trapezoid, a circle, or an oval. Touch sensors may be embedded in the heterogeneous pixel array (AA).

The lower substrate of the display panel 100 includes data lines (DL1 to DLm), gate lines (GL1 to GLn), thin film transistors (TFTs), a pixel electrode (1) connected to the TFT, and a pixel electrode (1). ), including a storage capacitor (Cst) connected to

Each pixel may be divided into red (R) pixel, green (G) pixel, and blue (B) pixel for color implementation. Additionally, each of the pixels may further include a white (W) pixel. Pixels adjust light transmittance using liquid crystal molecules driven by the voltage difference between the pixel electrode (PXL), which charges the data voltage through the TFT, and the common electrode (COM), to which the common voltage (Vcom) is applied.

TFTs formed on the lower substrate of the display panel 100 may be implemented as amorphous silicon (a-Si) TFT, low temperature poly silicon (LTPS) TFT, oxide TFT, etc. TFTs are formed at the intersection of data lines (DL1 to DLm) and gate lines (GL1 to GLn). The TFTs respond to the gate pulse and supply the data voltage from the data lines (DL1 to DLm) to the pixel electrode (PXL).

A color filter array including a black matrix (BM) and a color filter is formed on the upper substrate of the display panel 100. A common electrode (COM) is formed on the upper substrate in the case of vertical electric field driving methods such as TN (Twisted Nematic) mode and VA (Vertical Alignment) mode, and in IPS (In-Plane Switching) mode and FFS (Fringe Field Switching) mode. In the case of a horizontal electric field driving method such as mode, it can be formed on the lower substrate together with the pixel electrode. A polarizer is attached to each of the upper and lower substrates of the display panel 100, and an alignment film is formed to set the pre-tilt angle of the liquid crystal.

The display device of the present invention can be implemented in any form, such as a transmissive liquid crystal display device, a transflective liquid crystal display device, or a reflective liquid crystal display device. Transmissive and transflective liquid crystal displays require a backlight unit. The backlight unit may be implemented as a direct type backlight unit or an edge type backlight unit.

The display panel driving circuit writes data of the input image to the pixels. The display panel driving circuit includes a data driver 102, a gate driver 104, and a timing controller 106. The display panel driving circuit may further include a multiplexer (MUX).

The multiplexer (MUX) may be formed in the bezel area outside the pixel array (AA) on the substrate of the display panel 100. The multiplexer (MUX) is disposed between the data driver 102 and the data lines (DL1 to DLm).

The output channels of the data driver 102 are connected to the data lines DL1 to DLm through a multiplexer (MUX). The data driver 102 receives data of the input image from the timing controller 106. The data driver 102 converts digital video data of the input image into a gamma compensation voltage under the control of the timing controller 106 and outputs the data voltage. The data voltage is supplied to the data lines (DL1 to DLm) through a multiplexer (MUX).

The multiplexer (MUX) is disposed between the data driver 102 and the data lines (DL1 to DLm). The multiplexer (MUX) distributes the data voltage input from the data driver 102 to the data lines DL1 to DLm under the control of the timing controller 106. In the case of a 1:3 multiplexer as shown in FIG. 2, the multiplexer time-divides the data voltage input through one output channel of the data driver 102 and supplies it to three data lines. Therefore, by using a 1:3 multiplexer, the number of ICs of the data driver 102 required to drive the display panel 100 can be reduced by one-third.

Figure 2 is a diagram showing an embodiment of a multiplexer.

Referring to FIG. 2, in order to distribute the voltage output from the first and second output buffers (BUF1 and BUF2) to the first to sixth data lines (DL1 to DL6), the multiplexer (MUX) It may include 6 mux switches (M1 to M6).

The first mux switch M1 includes a gate receiving the first control signal C1, a drain connected to the first output buffer BUF1, and a source connected to the first data line DL1. The second mux switch M2 includes a gate receiving the second control signal C2, a drain connected to the first output buffer BUF1, and a source connected to the second data line DL2. The third mux switch M3 includes a gate receiving the third control signal C3, a drain connected to the first output buffer BUF1, and a source connected to the third data line DL3. The fourth mux switch M4 includes a gate receiving the first control signal C1, a drain connected to the second output buffer BUF2, and a source connected to the fourth data line DL4. The fifth mux switch M5 includes a gate receiving the second control signal C2, a drain connected to the second output buffer BUF2, and a source connected to the fifth data line DL5. The sixth mux switch M6 includes a gate receiving the third control signal C3, a drain connected to the second output buffer BUF2, and a source connected to the sixth data line DL6.

The gate driver 104 supplies gate pulses to the gate lines GL1 to GLn under the control of the timing controller 106. The gate driver 104 shifts the gate pulse using a shift register and sequentially supplies the gate pulse to the gate lines GL1 to GLn. The gate pulse is synchronized with the data voltage supplied to the data lines (DL1 to DLm). The gate driver 104 may be formed directly on the substrate of the display panel 100 using a GIP circuit.

3 to 7, data lines DL connected to the data driver 102 or the multiplexer MUX outside the heterogeneous pixel array AA and gate lines 104 connected to the gate driver 104. ) does not intersect. For this reason, even if the data driver 102 and the gate driver 104 are arranged roundly or at an obtuse angle along the outermost line of the heterogeneous pixel array (AA), the data driver 102 and the gate driver 104 overlap as shown in FIG. 16. I don't lose.

The timing controller 106 transmits digital video data of the input image received from the host system 110 to the data driver 102. The timing controller 106 receives timing signals synchronized with input image data from the host system 110. Timing signals include a vertical synchronization signal (Vsync), a horizontal synchronization signal (Hsync), a data enable signal (DE), and a main clock (DCLK). The timing controller 106 controls the operation timing of the data driver 102, the gate driver 104, and the multiplexer (MUX) based on timing signals (Vsync, Hsync, DE, and DCLK).

The touch sensor driver, not shown, supplies a driving signal to the touch sensors and determines a touch input based on the amount of change in charge of the touch sensors. In the case of a mobile device, the data driver 102, timing controller 106, touch sensor driver, etc. may be integrated into one integrated circuit (IC).

The host system 110 may be any one of a television (TV) system, a set-top box, a navigation system, a DVD player, a Blu-ray player, a personal computer (PC), a home theater system, and a phone system. The host system 110 transmits data of the input image to the timing controller 106, receives coordinate information of the touch input from the touch sensor driver, and executes an application program corresponding to the coordinate information.

3 to 7 are diagrams showing various heterogeneous pixel arrays and a display panel driving circuit according to an embodiment of the present invention. Figure 8 is a diagram showing data lines and gate lines crossing at an acute angle (θ).

3 to 8, the display panel of the present invention includes a heterogeneous pixel array and a display panel driving circuit disposed along the outermost line of the heterogeneous pixel array outside the heterogeneous pixel array. The display panel driving circuit includes a gate driver 201 and a data driver 101. 3 to 8, “DIC” is a data driver and “GIP” is a gate driver. Among the intersections of the data lines DL and the gate lines GL, the angle of at least some of the intersections is an acute angle θ.

In the case of a pixel array where data lines and gate lines intersect as in the prior art, when the display panel driving circuits are arranged to be bent at an obtuse angle along the outermost line of the heterogeneous pixel array, the data driver and the gate driver overlap and parasitic effects of the display panel occur. Capacity may be increased. In contrast, in the present invention, the gate lines GL and the data lines DL intersect at an acute angle, so that even if the display panel driving circuits are arranged to be bent at an obtuse angle along the outermost line of the heterogeneous pixel array, the display is displayed in a narrow bezel area. Design freedom can be improved by arranging the elements of the panel drive circuit and freely designing the layout of the circuit.

Figures 10 to 13 are diagrams showing a pixel array in which these TFTs are arranged.

Figure 10 is an enlarged plan view of a portion of the pixel array to show the plan layout of the pixel array. FIG. 11 is a diagram showing signal wiring of the pixel array formed along the diagonal direction in FIG. 10.

Referring to FIGS. 10 and 11 , in order to intersect the data lines DL and the gate lines GL at an acute angle θ, the data line DL or the gate line GL may be patterned in a step shape. there is. The data line DL may be patterned in a straight line, and the gate line GL may be patterned in a staircase shape. Conversely, the gate line DL may be patterned in a straight line, and the data line DL may be patterned in a staircase shape.

A straight data line (DL) or gate line (GL) is called a straight wiring, and a step-shaped gate line (GL) or data line (DL) is defined as a step pattern wiring. Staircase pattern wiring includes horizontal and vertical sections that are alternately connected in a manner that gradually rises (or falls) in one direction.

In order to obtain the effect of the straight wires and the step pattern wires intersecting at an acute angle as shown in FIGS. 3 to 8, the horizontal portions of the straight wires and the step pattern wires are orthogonal.

When the data lines DL are straight wires, the gate lines GL may be wired in a staircase pattern. When the gate lines GL are straight wires, the data lines DL may be wired in a staircase pattern. In staircase pattern wiring, an imaginary line connecting the center of the horizontal portion and the center of the vertical portion intersects the straight wiring at an acute angle.

FIG. 12 is a plan view showing one pixel in FIG. 10, and FIG. 13 is a cross-sectional view showing the cross-sectional structure of the pixel taken along “I-I'” in FIG. 12.

Referring to FIGS. 12 and 13 , pixels are defined by gate lines GL and data lines DL that intersect on the lower substrate GLS with the intermediate insulating layer INT in between. The pixel electrode PXL and the common electrode COM overlap with the third protective layer PA3 so that a fringe field can be applied between the pixel electrode PXL and the common electrode COM. The pixel electrode (PXL) may be separated into one or more pixel opening areas (OA). The pixel size of a high PPI (pixel per inch) display device is small. For this reason, the pixel electrode PXL may be divided into one or two pieces in the opening area OA, as shown in FIG. 12.

In each pixel, the data line (DL) and pixel electrode (PXL) are connected with a transistor. Basically, only one transistor can be implemented, but in order to reduce power consumption by reducing leakage current (or off-current) in the off state of the transistor, first and second transistors (T1) are installed in each pixel as shown in FIGS. 9 and 13. , T2) are preferably connected in series.

The first transistor T1 includes a source connected to the data line DL, a drain connected to the source of the second transistor T2, and a gate integrated with the gate line GL. The second transistor T2 includes a source connected to the data line DL, a source connected to the drain of the first transistor T1, and a gate integrated with the gate line GL. The drain of the first transistor (T1) and the source of the second transistor (T2) are connected through a semiconductor pattern (SEMI).

The gates of the first and second transistors T1 and T2 do not branch from the gate line GL but are used as part of the gate line to increase the opening area OA of the pixel. To this end, the semiconductor pattern (SEMI) within the pixel is formed as a pattern crossing the two transistor channel regions (A1 and A2) on the same gate line (GL). This semiconductor pattern (SEMI) contacts the data line (DL) through the first contact hole (CN1) and intersects the gate line (GL) at two points.

A light blocking layer (LS) is formed on the substrate (GLS). In the present invention, each of the transistors T1 and T2 may be implemented as an LTPS TFT. LTPS TFT can be formed with a top gate structure. In this case, current (photo current) may flow due to light (back light) flowing from the bottom to the top of the substrate (GLS). To prevent this problem, a light blocking layer LS may be disposed in a portion where the channel regions A1 and A2 of each of the transistors T1 and T2 are to be formed.

The buffer layer BUF is formed on the entire surface of the substrate GLS to cover the light blocking layer LS. A semiconductor pattern (SEMI) is formed on the buffer layer (BUF).

On the entire surface of the substrate GLS on which the semiconductor pattern SEMI is formed, a gate insulating material is deposited and patterned to form a gate insulating film GI covering the semiconductor pattern SEMI on the buffer layer BUF. A gate metal is deposited and patterned on the gate insulating layer GI to form a gate metal pattern on the gate insulating layer GI. The gate metal pattern includes a gate line (GL).

The semiconductor pattern (SEMI) is divided into an area that overlaps the gate line (GL) and an area that is not exposed. In order to lower the resistance of the exposed area of the semiconductor pattern (SEMI) without overlapping the gate line (GL), a portion of the semiconductor pattern (SEMI) may be made into a conductor by injecting impurities into the exposed area. The conductive portion of the semiconductor pattern (SEMI) includes a source contact area and a drain contact area. The semiconductor pattern (SEMI) overlapping the gate line (GL) is defined as the channel region (A1, A2) of the TFT (T1, T2).

An intermediate insulating film (INT) is deposited on the entire surface of the substrate (GLS) on which the gate line (GL) is formed. An intermediate insulating film (INT) is deposited on the entire surface of the substrate (GLS) on which the gate line (GL) is formed. First and second contact holes CN1 and CN2 are formed in the intermediate insulating layer INT and the gate insulating layer GI. The first contact hole CN1 exposes the source contact area of the semiconductor pattern SEMI. The second contact hole CN2 exposes the drain contact area of the semiconductor pattern SEMI.

A source-drain metal is deposited and patterned on the middle insulating layer INT to form first and second source-drain metal patterns SD1 and SD2 on the middle insulating layer INT. The first source-drain metal pattern SD1 includes a data line DL and the source of the first TFT T1 connected to the data line DL. The first source-drain metal pattern SD1 is in contact with the source contact area of the semiconductor pattern SEMI through the first contact hole CN1. The second source-drain metal pattern SD2 includes the drain of the second TFT (T2). The second source-drain metal pattern SD2 is in contact with the drain contact area of the semiconductor pattern SEMI through the second contact hole CN2. A first protective film (PAS1) is deposited on the intermediate insulating film (INT) to cover the first and second source-drain metal patterns (SD1). The first protective layer PAS1 may be formed of an organic insulating layer with a low dielectric constant, such as photo acrylic.

A first protective film hole PH1 is formed in the first protective film PAS1. The first protective film hole PH1 exposes the pixel electrode contact area on the second source-drain metal pattern SD2. A second protective film (PAS2) is formed on the first protective film (PAS1), and a common electrode (COM) is formed on the second protective film (PAS2). The third protective film (PAS3) is disposed on the second protective film (PAS2) to cover the common electrode (COM).

A second protective film hole PH2 is formed that penetrates the second and third protective films PAS2 and PAS2. The pixel electrode contact area of the second source-drain metal pattern SD2 is exposed through the second protective film hole PH2.

A pixel electrode (PXL) is formed on the third protective film (PA3). The pixel electrode (PXL) is in contact with the pixel electrode contact area of the second source-drain metal pattern (SD2) through the second protective film hole (PH2).

FIG. 14 is a diagram showing an example of the arrangement of a display panel driving circuit and signal wires of the display panel according to an embodiment of the present invention.

Referring to FIG. 14, the display panel driving circuit includes a first driver (DIC1) and a second driver (DIC2). In FIG. 14 , the first and second drivers DIC1 and DIC2 are adjacent data drivers and gate drivers, as shown in FIGS. 3 to 7 . The angle θ1 between the first and second driving units DIC1 and DIC2 along the outermost line of the heterogeneous pixel array may be an obtuse angle.

A data line (or gate line) connected to the first driver DIC1 and a gate line (or data line) connected to the second driver DIC2 intersect at an acute angle θ2.

15 and 16 show the data lines DL and the gate when the data driver DIC and the gate driver GIP are arranged roundly or at an obtuse angle along the outermost line of the heterogeneous pixel array AA in a heterogeneous display device. These are drawings showing problems that can occur when lines (GL) are orthogonal. It should be noted that Figures 15 and 16 are comparative examples illustrating to compare the effect of the present invention rather than the prior art widely known in the art.

Referring to FIG. 15, when the data lines DL and the gate lines GL are orthogonal, portions where the data lines DL and the gate lines GL intersect in the bezel area outside the heterogeneous pixel array AA It becomes more. Due to this portion (OVL), the capacity (capacitance) of the heterogeneous pixel array (AA) increases, which may cause signal delay. In contrast, in the present invention, when the display panel driving circuit is arranged along the outermost line of the heterogeneous pixel array (AA), the pixel array (AA) is formed by intersecting the data lines (DL) and the gate lines (GL) at an acute angle. Outside, there is almost no intersection between the data lines (DL) and gate lines (GL).

Referring to FIG. 16, when the display panel driving circuit is arranged along the outermost line of the heterogeneous pixel array (AA) where the data lines (DL) and the gate lines (GL) are orthogonal to each other, the first data driver (DIC1) and the gate driver (GIP) may overlap. In contrast, in the present invention, when the display panel driving circuit is arranged along the outermost line of the heterogeneous pixel array (AA), the pixel array (AA) is formed by intersecting the data lines (DL) and the gate lines (GL) at an acute angle. Outside, there is almost no intersection between the data lines (DL) and gate lines (GL). For this reason, when the data driver and the gate driver are arranged along the outermost line of the heterogeneous pixel array, the drivers do not overlap.

Figure 17 is a diagram showing a pixel array according to the second embodiment. FIG. 18 is a diagram showing the first pixel shown in FIG. 17, and FIG. 19 is a diagram showing data lines located at the boundary between the first pixel and the second pixel in FIG. 17. In the description of the second embodiment, the horizontal direction refers to the x-axis direction in FIG. 17 and the horizontal direction refers to the y-axis direction.

17 to 19, in the pixel array according to the second embodiment, the first and second pixels P1 and P2 located in adjacent column lines and connected to the same gate line are not disposed at the same position in the horizontal direction. No. The opening area OA1 of the first pixel P1 disposed on the first column line CL1 contacts the side of the transistor area TA1 of the second pixel P2 disposed on the second column line CL2. .

The width W1 of the first opening area OA1 and the width W2 of the first transistor area TA1 may be defined as the distance between the centers of the first and second data lines DL1 and DL2 in the horizontal direction. . Since the first and second data lines DL1 and DL2 disposed on both sides of the first pixel P1 are inclined inward from the bottom of the first pixel P1, the width W2 of the first transistor area TA1 ) is narrower than the width W1 of the first opening area OA1.

The transistor (T) has a source (S) corresponding to the horizontal part (HDL) of the data line (DL), a gate (G) that is part of the gate line, and a drain connected to the drain metal pattern (DP) through a contact hole (CN). Includes (D). The drain metal pattern (DP) extends from the drain (D) to the transistor area (TA1) to secure the aperture ratio, and is connected to the pixel electrode through the protection hole (PH) in the transistor area (TA1).

The first pixel P1 includes a first opening area OA1 and a first transistor area TA1. First and second data lines DL1 and DL2 are disposed at the boundary of the area of the first pixel P1.

The first data line DL1 consists of first and second vertical parts VDL1 and VDL2, first and second inclined parts SDL1 and SDL2, and horizontal parts HDL.

The first and second inclined portions SDL1 and SDL2 extend from the upper and lower portions of the first vertical portion VDL1, respectively. The second inclined portion SDL2 extends from the lower portion of the first vertical portion VDL1 in a slanted inward direction. The interior angle formed by the first vertical portion (VDL1) and the first inclined portion (SDL1) and the interior angle formed by the first vertical portion (VDL1) and the second inclined portion (SDL2) are obtuse angles. As a result, the horizontal width W2 of the first transistor area TA1 in the first pixel P1 is shorter than the horizontal width W1 of the first opening area OA1.

The first vertical portion VDL1 and the first and second inclined portions SDL1 and SDL2 are disposed on one side of the first opening area OA1.

Likewise, the first vertical portion VDL1 and the first and second inclined portions SDL1 and SDL2 of the second data line DL2 disposed on the other side of the first pixel P1 are of the first opening area OA1. placed on the other side.

The second vertical portion (VDL2) of the first and second data lines (DL1, DL2) is disposed in the vertical direction in the second inclined portion (SDL2). The horizontal portion HDL is disposed in the horizontal direction in the second vertical portion VDL2. The horizontal portion (HDL) corresponds to the source electrode (S) connected to the semiconductor layer (A).

The second vertical portion (VDL2) and the horizontal portion (HDL) of the first data line (DL1) are disposed in the transistor area (TA1) of the first pixel (P1).

The i (i is a natural number) gate line (GLi) overlaps with a partial area of the second inclined portion (SDL2) and the first vertical portion (VDL1) of the first data line (DL1) on a plane, and the first data line ( It has a horizontal portion parallel to the horizontal portion (HDL) of DL1). As a result, the ith gate line (GLi) has a step shape. A portion of the horizontal portion (HDL) of the ith gate line (GLi) becomes the gate electrode (G).

The side surface of the first transistor area TA1 contacts the second opening area OA2 of the second pixel P2. That is, since the second opening area OA2 is in contact with the first transistor area TA1, which has a width narrower than the width of the opening area, a larger area can be secured. Looking at this with reference to a comparative example, it is as follows.

Figure 20 is a diagram showing pixels according to a comparative example.

Referring to FIG. 20, the first and second pixels P1 and P2 according to the comparative example have a rectangular shape.

The first pixel P1 includes a first opening area OA1 and a first transistor area TA1, and the second pixel P2 includes a second opening area OA2 and a second transistor area TA2. do. The first and second opening areas (OA1, OA2) and the first and second transistor areas (TA1, TA2) have a rectangular shape.

The widths of the first and second opening areas OA1 and OA2 are determined by the spacing between adjacent data lines DL1 and DL2. Additionally, adjacent first and second opening areas OA1 and OA2 contact each other. Therefore, even if the dummy area DA is reduced in the first and second transistor areas TA1 and TA2, there is no room to expand the width of the opening areas OA1 and OA2.

In contrast, in the second embodiment of the present invention, the opening area and the transistor area of pixels arranged in adjacent column lines contact each other from the side. As a result, as shown in FIG. 21, the second opening area OA2 can be expanded to the dummy area DA, and thus the opening area OA2 can be expanded by the same amount as the width of the transistor area TA1 is reduced.

Through the above-described content, those skilled in the art will be able to see that various changes and modifications can be made without departing from the technical idea of the present invention. Therefore, the technical scope of the present invention should not be limited to what is described in the detailed description of the specification, but should be defined by the scope of the patent claims.

100: display panel 102: data driver
104: Gate driver 106: Timing controller
DL1~DLm: Data line GL1~GLn: Gate line

Claims (7)

A display panel in which data lines and gate lines intersect at acute angles and has a non-rectangular non-rectangular pixel array;
a data driver disposed along an outermost line of the heterogeneous pixel array and connected to the data lines; and
a gate driver disposed along an outermost line of the heterogeneous pixel array and connected to the gate lines;
Each of the pixels of the pixel array includes an opening area located inside the pair of data lines and a transistor area vertically adjacent to the opening area and in which a transistor is disposed,
In the pixel array, each of the first and second data lines located on both sides of the first pixel is
a first vertical portion disposed on a side of the opening area; and
At an end of the first vertical portion, there is an inclined portion inclined toward the center of the horizontal width of the transistor area,
The first data line is
a second vertical portion extending in a vertical direction from the inclined portion; and
Further comprising a horizontal portion in a horizontal direction from the second vertical portion,
The horizontal portion is connected to the semiconductor layer to form a source electrode,
A display device in which the horizontal width of the transistor area is narrower than the horizontal width of the opening area. delete delete According to claim 1,
A display device wherein the inclined portion of the first data line overlaps the gate line. According to claim 4,
The gate line is
A display device having a staircase shape, including a region that partially overlaps the first vertical portion and the inclined portion of the first data line and is parallel to the horizontal portion of the first data line. According to claim 1,
The first pixel is disposed in a first column line,
In the second column line, the display device further includes a second pixel having an opening area whose side contacts the transistor area of the first pixel. delete

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