KR102365917B1 - Display device - Google Patents

Abstract

The present invention relates to a display device, comprising: a display panel including a curved section having a center of a circle; a gate driving circuit formed outside the pixel array on the display panel to supply a gate pulse to the gate lines; a plurality of auto probe pads disposed on one bezel area of the display panel; a plurality of switch elements disposed on the other bezel area of the display panel with the pixel array interposed therebetween; and a plurality of wires disposed in the pixel array to connect the auto probe pads and the switch elements. The gate driving circuit includes a shift register to which stages are sequentially connected, and at least one of the stages is arranged along a curved line of the display panel and out of an extension line of the gate line.

Description

display device {DISPLAY DEVICE}

The present invention relates to a display device in which a gate driving circuit is incorporated in a display panel of a non-rectangular display device having a non-rectangular substrate structure.

Wearable devices, flexible devices, instrument panels, etc. require various types of heterogeneous display devices instead of the conventional rectangular shape. For example, in a circular watch, the display panel is processed into a disk shape.

The driving circuit of the display device includes a pixel array for displaying an image, a data driving circuit for supplying data signals to data lines of the pixel array, and a gate pulse ( or a gate driving circuit (or scan driving circuit) for sequentially supplying scan pulses), a timing controller for controlling the data driving circuit and the gate driving circuit, and the like. Recently, a technology for embedding a gate driving circuit in a display panel together with a pixel array has been applied. The gate driving circuit built into the display panel is known as a “Gate In Panel (GIP) circuit”. The GIP circuit includes a shift register. A shift register includes a number of cascadingly connected stages. The stages generate an output in response to a start pulse and shift the output according to a shift clock. Accordingly, a start pulse, a shift clock, a driving voltage, and the like are supplied to the shift register.

In the display device, a gate driving circuit is connected to a separate gate driving IC (Integrated Circuit) (GIC) to the display panel as shown in FIG. 1 . This method not only increases the cost of the display device due to the cost of the IC, but also increases the number of routing lines RL, thereby increasing the bezel widths BZx and BZy. The routing wires RL connect output terminals of the gate drive IC to the gate lines. Accordingly, the routing lines RL are required as many as the number of gate lines of the pixel array. A bezel is a non-display area outside the pixel array.

If the GIP circuit is embedded in the heterogeneous display panel, the number of routing wires (RL) can be reduced, but it is difficult to reduce the bezel width (BZx). In order to secure a space occupied by wirings that supply start pulses, shift clocks, and driving voltages to the stages of the GIP circuit, it is difficult to reduce the bezel width because the GIP circuit is lengthened in the x-axis direction. Accordingly, there is no example in which a GIP circuit is applied to a display device.

In order to perform an electrical inspection of the display panel in the manufacturing process of the display panel, pads or switch elements for electrical inspection may be formed on a substrate of the display panel. The switch elements may be implemented as TFTs formed on a substrate of a display panel at the same time as a thin film transistor (hereinafter, referred to as “TFT”) of a pixel array.

A liquid crystal display (LCD) displays an image by controlling an electric field applied to liquid crystal molecules according to a data voltage. In an active matrix driving type liquid crystal display device, a TFT is formed for each pixel.

Liquid crystal display manufacturing process includes substrate cleaning of liquid crystal display panel, substrate patterning process, alignment film formation/rubbing process, substrate bonding and liquid crystal dropping process, driving circuit mounting process, inspection process, repair process, liquid crystal module assembly process, etc. do.

In the substrate cleaning process, foreign substances contaminated on the surfaces of the upper and lower glass substrates of the liquid crystal display panel are removed with a cleaning solution. The substrate patterning process forms various thin film patterns such as signal wiring, TFT, and pixel electrodes including data lines and gate lines on the lower glass substrate, and various types of black matrix, color filters, and common electrodes, etc., on the upper glass substrate. forming and patterning the thin film material. In the alignment film formation/rubbing process, an alignment film is applied on glass substrates and the alignment film is rubbed with a rubbing cloth or subjected to photo-alignment treatment. Through this series of processes, the lower glass substrate of the liquid crystal display panel has data lines supplied with a video data voltage, gate lines crossing the data lines and sequentially supplied with scan signals, i.e., gate pulses, and data lines. A TFT array including a TFT formed at the intersection of the gate lines, a pixel electrode connected to the TFTs, a storage capacitor, and the like is formed. A color filter array including a black matrix, a color filter, and a common electrode is formed on the upper glass substrate of the liquid crystal display panel. The common electrode is formed on the upper glass substrate in a vertical electric field driving method such as TN (Twisted Nematic) mode and VA (Vertical Alignment) mode, and horizontal electric field such as IPS (In Plane Switching) mode and FFS (Fringe Field Switching) mode It is formed on the lower glass substrate together with the pixel electrode in the driving method. A polarizing plate, a polarizing plate, a protective film, etc. are attached to each of the upper glass substrate and the lower glass substrate.

In the substrate bonding and liquid crystal dropping process, a sealant is drawn on one of the upper and lower glass substrates of the liquid crystal display panel and liquid crystal is dropped on the other substrate.

In the driving circuit mounting process, the integrated circuit (IC) of the data driving circuit is mounted on the lower glass substrate of the liquid crystal display panel using a chip on glass (COG) process or a tape automated bonding (TAB) process. The gate driving circuit may be directly formed on the lower glass substrate of the liquid crystal display panel together with the TFT array in the GIP (Gate In Panel) process, or may be attached on the lower glass substrate by the TAB process in the driving circuit mounting process. The driving circuit mounting process connects driving circuit ICs and a printed circuit board (PCB) with a flexible printed circuit board (FPC) or a flexible flat cable (FFC).

The inspection process includes inspection of the driving circuit, wiring inspection of data lines and gate lines formed on the TFT array substrate, inspection performed after pixel electrodes are formed, electrical inspection conducted after substrate bonding and liquid crystal dropping process, lighting inspection, etc. do. The repair process repairs defects found by the inspection process.

When the liquid crystal display panel is completed through the above-described series of processes, the assembly process of the liquid crystal module is performed. The liquid crystal module assembly process aligns the backlight unit under the liquid crystal display panel, and assembles the liquid crystal display panel and the backlight unit into a liquid crystal module using mechanisms such as guide/case members.

In the auto-probe inspection, electrical inspection is performed on the substrate of the liquid crystal display panel prior to the driving circuit mounting process to inspect signal wiring defects or thin film pattern defects on the substrate.

In order to enable the auto probe test, the lower glass substrate includes an auto probe test pad (hereinafter referred to as "AP pad") that is in contact with the needle of the auto probe test device, and a signal wire (hereinafter referred to as "AP pad") connected to the AP pad. , "AP wiring"), and switch elements (hereinafter, referred to as "AP switch") connected between the AP wirings and the signal wirings of the pixel array are formed. The AP pad and the AP wirings are formed in the bezel area BZ together with the GIP circuit. Therefore, it is difficult to secure a space for arranging the AP pad and the AP wires in the bezel area of the display device having a narrow bezel or a different shape.

The present invention provides a display device capable of embedding a gate driving circuit in a heterogeneous display panel without increasing a bezel width.

The display device of the present invention includes data lines, gate lines orthogonal to the data lines, and a pixel array in which pixels are arranged in a matrix form defined by the data lines and the gate lines, and includes a center of a circle. A display panel including a curved section having a; a gate driving circuit formed outside the pixel array on the display panel to supply a gate pulse to the gate lines; a plurality of auto probe pads disposed on one bezel area of the display panel; a plurality of switch elements disposed on the other bezel area of the display panel with the pixel array interposed therebetween; and a plurality of wires disposed in the pixel array to connect the auto probe pads and the switch elements.
The gate driving circuit includes a shift register to which stages are sequentially connected, and at least one of the stages is arranged along a curved line of the display panel and out of an extension line of the gate line.

delete

According to the present invention, the shift register of the gate driving circuit is arranged along the curved line of the display panel and at least one of the stages of the shift register is arranged at a position out of the extension line of the gate line, thereby providing a gate to the heterogeneous display panel without increasing the bezel width of the display panel. A driving circuit can be built-in. Furthermore, according to the present invention, by arranging the stage of the shift register above or below the extension line of the gate line, a space for arranging elements for electrical inspection can be secured on the bezel of the heterogeneous display panel.

1 is a diagram showing a gate driving circuit applied to a conventional display device.
2 is a block diagram illustrating a driving circuit of a display device according to an exemplary embodiment of the present invention.
3 is a diagram showing a shift register configuration of a GIP circuit.
4 and 5 are diagrams illustrating various connection forms of the GIP circuit and the gate lines when the GIP circuit is disposed on both sides of the heterogeneous display panel.
6 and 7 are views illustrating various examples of a heterogeneous display panel.
8 is a diagram illustrating an example in which a bezel increases when a GIP circuit is built in a heterogeneous display panel.
9 and 10 are diagrams illustrating a GIP circuit arrangement of a display device according to an exemplary embodiment of the present invention.
FIG. 11 is an enlarged view illustrating stages adjacent to each other in FIGS. 9 and 10 .
12 is a view showing a right-angled triangle having the same height as the radius of the circle of FIG. 12 .
13 is a diagram illustrating an example of a gate driving circuit applied to a variant display panel of a 5.5″ QHD (Quarter High Definition) product.
14 is a diagram illustrating various methods of connecting a stage and gate lines of a shift register in a bezel area of a display device according to an exemplary embodiment of the present invention.
15 is a diagram illustrating a pad and wiring for an auto probe inspection in a display device according to an exemplary embodiment of the present invention.
16 is a circuit diagram showing details of an AP pad, an AP wiring, and an AP switch for an auto probe test.
17 and 18 are diagrams schematically showing a mobile terminal to which a display device is applied according to an embodiment of the present invention.
19 is a plan view illustrating the display module illustrated in FIG. 18 in detail.

The display device of the present invention is a liquid crystal display (LCD), a field emission display (FED), a plasma display panel (PDP), an organic light emitting diode display (Organic Light Emitting Display) , OLED), and can be implemented based on flat panel display devices such as electrophoresis (EPD).

Hereinafter, preferred embodiments according to the present invention will be described in detail with reference to the accompanying drawings. Like reference numerals refer to substantially identical elements throughout. In the following description, if it is determined that a detailed description of a known function or configuration related to the present invention may unnecessarily obscure the gist of the present invention, the detailed description thereof will be omitted.

2 and 3 , a display device according to an exemplary embodiment of the present invention includes a heterogeneous display panel PNL and a driving circuit for writing input image data to a pixel array of the display panel PNL. includes

The heterogeneous display panel PNL includes data lines, gate lines orthogonal to the data lines, and a pixel array in which pixels are arranged in a matrix form defined by the data lines and the gate lines. In addition, the heterogeneous display panel PNL includes a curved section having a center of a circle as shown in FIGS. 6 to 9 . The input image is displayed in a pixel array.

Touch sensors may be disposed on the deformable display panel PNL. Touch sensors may be embedded in the pixel array. In this case, the display device of the present invention may further include a touch sensor driving circuit for driving the touch sensors.

The display driving circuit includes a data driving circuit (SIC) for supplying a data signal to the data lines 12 and a GIP circuit for sequentially supplying a gate pulse synchronized with the data signal to the gate lines 14 . A timing controller (not shown) T-con transmits digital data of an input image to the data driving circuit SIC, and controls operation timings of the data driving circuit GIC and the GIP circuit. The GIP circuit may be formed on one edge or both edges of the heterogeneous display panel outside the V pixel array.

The GIP circuit includes a shift register. The shift register includes subordinately connected stages S(N-2) to S(N+2) as shown in FIG. 3 . The stages S(N-2) to S(N+2) start to output a gate pulse in response to the start pulse Vst, and shift the output according to the shift clocks GCLK1 to GCLK4. Link wires are connected to the stages S(N-2) to S(N+2). Output signals of the stages S(N-2) to S(N+2) are supplied to the gate lines G1 to Gn as gate pulses. An output of each of the stages may be input as a start pulse of the next stage, and the output may also be input to a previous stage as a reset signal. The stages may output a carry signal separate from the gate pulse and supply it to the next stage as a start pulse.

Link wires connected between the stages S(N-2) to S(N+2) transmit a start pulse Vst, a shift clock GCLK1 to GCLK4, a driving voltage, and the like to the stages S(N-2). to S(N+2)), and transmits a carry signal and a reset signal between stages S(N-2) to S(N+2). The driving voltage includes a high voltage and a low voltage of the gate pulse. The carry signal is input as a start pulse of the next stage, and the reset signal discharges the output of the previous stage.

4 and 5 are diagrams illustrating various connection forms of the GIP circuit and gate lines when the GIP circuit is disposed on both sides of the heterogeneous display panel PNL.

Referring to FIG. 4 , the GIP circuit includes a first GIP (GIP(L)) circuit disposed on one edge of the variant display panel PNL, and a second GIP (GIP(L)) circuit disposed on the other edge of the variant display panel PNL. (R)).

Each of the first and second GIP circuits GIP(L) and GIP(R) may be connected to all gate lines G1 to Gn. Each of the first and second GIP circuits GIP(L) and GIP(R)) simultaneously receives a start pulse Vst and simultaneously outputs a gate pulse. Accordingly, the gate pulses output from the first and second GIP circuits GIP(L) and GIP(R) are simultaneously applied to both ends of the same gate line.

Referring to FIG. 5 , the first GIP circuit GIP(L) is connected to the gate lines of the first group to sequentially supply gate pulses to the gate lines of the first group. The second GIP circuit GIP(R) is connected to the gate lines of the second group to sequentially supply gate pulses to the gate lines of the second group.

The gate lines of the first group may be odd-numbered gate lines G1, G3, ... Gn-1 as shown in FIG. 5 . The gate lines of the second group may be even-th gate lines G2, G4, ... Gn as shown in FIG. 5 . A start pulse Vst may be applied to the first and second GIPs GIP(L) and GIP(R) with a predetermined time difference. Accordingly, there may be a predetermined time difference between the gate pulse output timing and the carry signal output timing of the first and second GIP circuits GIP(R). For example, after the first gate pulse from the first GIP circuit GIP(L) is applied to the first gate line G1, approximately one horizontal period after the second gate pulse from the second GIP circuit GIP(R) A gate pulse may be supplied to the second gate line G2 .

6 and 7 are diagrams illustrating various examples of a heterogeneous display panel according to an embodiment of the present invention.

6 and 7 , at least a portion of the deformable display panel may be processed into a curve having a predetermined curvature. Stages of the GIP circuit are arranged along the curved line of the heterogeneous display panel PNL. The stages S(N-2) to S(N+2) are arranged along an extension line E that connects the ends of each of the gate lines GL from the center C of the circle in the curve. The major axis L of the stage is parallel to the extension line E connecting the ends of the gate lines GL from the center C of the circle, and the center of the minor axis length S of the stage meets the extension line E.

8 is a diagram illustrating an example in which a bezel increases when a GIP circuit is built in a heterogeneous display panel.

Referring to FIG. 8 , each of the stages of the GIP circuit may be connected to the gate lines GL in parallel and disposed along a curved line of the heterogeneous display panel. However, in this method, it is necessary to reduce the minor axis length (or vertical width, S) of the stages S(N-2) to S(N+2) in the curved section, and the stages S(N) in the straight section (not shown) -2) to S(N+2)), the short-axis length (S) should be reduced. When the circuit configuration of the stages is the same, if the minor axis length of the stage is reduced, the major axis length (or the horizontal width) becomes longer, thereby increasing the bezel width. In FIG. 8, reference numeral 20 denotes a stage, and reference numeral 22 denotes link wires connecting the stages.

9 to 11 , according to the present invention, the stages of the GIP circuit are arranged along the curved line of the heterogeneous display panel PNL, and as shown in FIGS. 6 and 7 , the long axis direction of the stage is the center of the circle (C). to be inclined at a predetermined angle so as to be parallel to the extension line E connecting the ends of the gate lines GL. In addition, the stage arranged along the curved line deviates from the extension line 36 of the gate line GL as shown in FIG. 14A . As a result, the present invention provides the stages S(N-2) to S(N+2) in a narrow exclusion area of the heterogeneous display panel PLN without increasing the stage long axis length (or horizontal width) of the GIP circuit. It can be placed along a curved line.

In the GIP circuit of the present invention, stages include adjacent stages whose spacing increases toward the end of the heterogeneous display panel. Adjacent stages are arranged along a curved line with the same center (C) of the circle. When each of the neighboring stages has one end close to the center (C) and the other end far from the center (C), the distance g1 between one end of the neighboring stages is the distance between the other ends ( g2) is smaller than

9 is an example in which stages of the GIP circuit are connected 1:1 with gate lines. In FIG. 10, GIP circuits are formed on each of both sides of the heterogeneous display panel as in FIG. 5, and the GIP circuits are connected to odd-numbered gate lines ( G1, G3, G5...Gn-1) and even-th gate lines G2, G4, G6...Gn are dividedly driven. In the example of FIG. 10 , the short-axis length (or vertical width) of each of the stages of the GIP circuit can be increased up to twice (2P) the vertical width P of 1 pixel, so the bezel width ( BZ) can be further reduced. In other words, the vertical width of each of the stages is less than or equal to twice the vertical width of 1 pixel.

9 and 10 , reference numeral 34 denotes a link wire connecting the gate line GL and the stage.

According to the present invention, the angle θ of the stages of the GIP circuit can be calculated along the curved line in the heterogeneous display panel based on the trigonometric function calculation of a right triangle having a hypotenuse of the same length as the radius R of the circle as shown in FIG. 12 . . Hereinafter, as shown in FIGS. 5 and 10 , in an example in which GIP circuits are separately disposed on both sides of the heterogeneous display panel PNL, odd-numbered gate lines are connected to the first GIP circuit, and even-th gate lines are connected to the second GIP circuit, the stage A method of calculating the angles θ will be described with reference to FIGS. 12 and 13 .

12 and 13 , the radius R of the circle is determined by the curved line and the bezel size of the heterogeneous display panel. It is assumed that the vertical width of each of the stages of the first and second GIP circuits GIP(L) and GIP(R) is a constant determined to be twice the vertical width P of one pixel. The height H of the right triangle is calculated as an arithmetic sequence having a tolerance d by setting the number of the uppermost gate line to which the first gate pulse is output in each of the first and second GIP circuits as '1'. The height of the first gate line (height Hodd1 of G1) of the first GIP circuit GIP(L) and the height of the first gate line (height of G2 Heven1) of the second GIP circuit GIP(R) are 1 pixel vertical The difference is as much as the width (P). The height sequence of the odd-th gate lines (G1, G3, G5... Gn-1) HoddN (N is a positive integer) and the height sequence HevenN of the even-th gate lines (G2, G4, G6... Gn) Is as follows.

HoddN = Hodd1 + (n-1)d

HevenN = Heven1 + (n-1)d

Given the radius (R) and height (H) of the circle, the angle (θ) is calculated as follows, so the stage of the first GIP circuit connected to the odd-th gate lines (G1, G3, G5... Gn-1) The angle AoddN and the stage angle AevenN of the first GIP circuit connected to the even-th gate lines G2, G4, G6... Gn are calculated as follows.

Based on this, as a result of applying the 5.5″ QHD (Quarter High Definition) product standard, the stages of the GIP circuit connected to each of the gate lines could be arranged within 0.95 mm of the bezel as shown in FIG. 13 . The vertical width (one PXL size) of 5.5″ QHD is 47.25 μm, the vertical width of the stage (GIP vertical width (d)) is 94.50 μm, and the radius (R) of the circle is 3050 μm.

14 is a diagram illustrating various methods of connecting a stage and gate lines of a GIP circuit in a bezel area of a display device according to an exemplary embodiment of the present invention.

Referring to FIG. 14 , in order to narrow the bezel area or secure additional space for other circuits to be arranged within the bezel area, the stage 30 of the shift register is arranged to extend beyond the extension line 36 of the gate line GL. . Each of the stages 30 is dependently connected to each other, and is connected to the gate line GL through the link wiring 34 .

One or more of the stages 30 may be disposed on the extension line 36 of the gate line GL as shown in FIG. 14A . One or more of the stages 30 may be disposed under the extension line 36 of the gate line GL as shown in FIG. 14B . The angle θ between the extension line 36 of the gate line GL and the stage, the interval between the extension line 36 of the gate line GL and the stage 30, etc. are the width of the bezel area or the curvature of the curve in the unusual part. may vary depending on the radius of

15 is a diagram illustrating a pad and wiring for an auto probe test in a display device according to an exemplary embodiment of the present invention. 15 is an example in which a release part is formed on an upper end of a pixel array in a mobile device. 16 is a circuit diagram showing details of an AP pad, an AP wiring, and an AP switch for an auto probe test.

15 and 16 , the shift register of the GIP circuit is disposed in the left and right bezel areas outside the pixel array. The top of the pixel array has an anomaly designed as a curve. If the upper bezel area is designed as a deformed part, the bezel area becomes narrow, making it difficult to arrange devices for auto-probe inspection.

In order to enable automatic probe inspection, an AP pad APPAD, an AP wiring 21 to 24 , an AP switch APTR, etc. are formed on the substrate of the display panel. In the present invention, in order to arrange the AP switch APTR in the upper bezel area of the display panel, at least some of the stages of the shift register disposed in the bezel area are disposed below the extension line of the gate line GL. Each of the stages is connected to the gate line GL through the link wiring 34 .

Since the stages of the shift register are arranged below the extension line of the gate line, a space without stages is secured in the bezel area. AP switches APTR may be disposed in the space secured in this way.

The AP wirings include an enable line 21 , a first test data line 22 , a second test data line 23 , and a third test data line 23 . The AP pads APPAD and the AP switches APTR may be separated from the display panel PNL with a pixel array interposed therebetween.

The AP wirings 21 to 24 may be formed in the pixel array. The AP wirings 21 to 24 overlap the data lines DL connected to the pixels and may be disposed in the pixel array without reducing the aperture ratio of the pixel. The AP pads APPAD may be disposed on the lower bezel together with the drive IC DIC. The AP pads APPAD are connected to the AP wires 21 to 24 .

The AP switch APTR may be disposed in the upper bezel additionally secured by the stages 30 being disposed below the extension line of the gate line. The AP switch APTR is disposed in a space secured above the stages 30 including the first TFT T1 , the second TFT T2 , and the third TFT T3 . The first TFT T1 supplies a first test data signal to the first data line DL connected to the red sub-pixel in response to the enable signal EN. The gate of the first TFT T1 is connected to the enable line 21 . The drain of the first TFT T1 is connected to the first test data line 22 , and the source of the first TFT T1 is connected to the first data line 12 . The first test data signal is supplied to the first test data wiring 22 through the needle in the inspection process. The second TFT T2 supplies a second test data signal to the second data line DL connected to the green sub-pixel in response to the enable signal EN. The gate of the second TFT T2 is connected to the enable line 21 . The drain of the second TFT T2 is connected to the second test data line 23 , and the source of the second TFT T2 is connected to the second data line DL. The second test data signal is supplied to the second test data wiring 23 through the needle in the inspection process. The third TFT T3 supplies a third test data signal to the third data line DL connected to the blue sub-pixel in response to the enable signal EN. The gate of the third TFT T3 is connected to the enable line 21 . The drain of the third TFT T3 is connected to the third test data line 24 , and the source of the third TFT T3 is connected to the third data line DL. The third test data signal is supplied to the third test data line 24 through the needle in the inspection process.

In the inspection process, the auto probe inspection apparatus supplies the enable signal and the RGB test data signal through the AP pads, and supplies the gate test signals to the GIP lines through the GIP pads (not shown). The GIP pads are connected to the GIP wires and contact the needle of the auto probe inspection device in the inspection process. The gate test signals include signals such as a start pulse and a shift clock for driving the shift register of the gate driving circuit GIP. When the gate lines and the data lines are driven in this way, the presence or absence of defects in pixels and signal lines can be checked without mounting the drive IC (DIC) on the display panel (PNL).

The drive IC (DIC) includes a data drive circuit. The data driving circuit supplies data voltages to data lines connected to the pixels to write data to the pixels. A multiplexer (MUX) may be disposed between the data driving circuit and the pixel array as shown in FIG. 19 . The multiplexer MUX may reduce the number of output channels of the data driving circuit by dividing the data voltage from the data driving circuit. The drive IC (DIC) may further include a timing controller and a touch sensor driving circuit.

The timing controller transmits the input image data received from the host system to the data driving circuit. In addition, the timing controller controls operation timings of the data driving circuit, the gate driving circuit, and the touch sensor driving circuit. The host system (FIG. 19, HOST) is, in this embodiment, any one of a phone system, a TV (Television) system, a set-top box, a navigation system, a DVD player, a Blu-ray player, a personal computer (PC), and a home theater system. can be one

17 and 18 are diagrams schematically showing a mobile terminal to which a display device is applied according to an embodiment of the present invention. 19 is a plan view illustrating the display module illustrated in FIG. 18 in detail.

17 to 19 , the mobile terminal of the present invention includes a display module, a front cover 101, a back cover 103, a mid frame, a main board 104, and a battery. (105) and the like. Here, the “cover” may be expressed as a case or a housing.

The display device of the present invention may be implemented as a flat panel display device, such as a liquid crystal display (LCD) or an organic light emitting diode display (OLED display). It should be noted that although the embodiment is mainly described with respect to the liquid crystal display device (LCD), the present invention is not limited thereto.

The display module includes the display panel 100 of the flat panel display and a display panel driving circuit. Touch sensors may be disposed on the entire screen of the display panel 100 . The display panel driving circuit includes a drive IC (DIC) and a flexible circuit board 106 connecting the drive IC (DIC) to the main board 104 . The drive IC (DIC) writes image data input through the main board 104 into pixels of the display panel 100 . The flexible circuit board may be any one of a flexible printed circuit board (FPC) and a flexible flat cable (FFC).

The front cover 101 may include tempered glass covering the display panel 100 . The front cover 101 covers the front of the mobile terminal. A front camera and various sensors may be disposed on the front of the mobile terminal. A rear camera and various sensors may be disposed on the rear surface of the mobile terminal. The sensors are sensors applicable to a mobile terminal, for example, a proximity sensor, a gyro sensor, a geomagnetic sensor, a motion sensor, an illuminance sensor, an RGB sensor, a Hall sensor, a temperature/humidity sensor, a heart rate sensor, and a fingerprint recognition sensor. and various other sensors.

A display module, a mid frame 102 , a main board 104 , a battery 105 , and the like are disposed in a space between the front cover 101 and the back cover 103 . The mid frame 102 supports the display panel 100 and spatially separates the display panel 100 from the main board 104 . The flexible circuit board 106 of the display module is connected to the main board 104 through a slot of the mid frame 102 . An audio/video (A/V) input unit, a user input unit, a speaker, a microphone, and the like are installed on the front cover 101 and the back cover 103 . The A/U input, user input, speaker, and microphone are connected to the main board 104 . The user input unit may include a touch key pad, a dome switch, a touch pad, a jog wheel, a jog switch, and the like.

Circuits of the host system (HOST) are mounted on the main board 104 . The host system (HOST) includes a display module, a wireless communication module, a short-range communication module, a mobile communication module, a broadcast reception module, an A/U input unit, a Global Position System (GPS) module, a power circuit, and the like. A user input unit, a speaker, a microphone, a battery 105, and the like are connected to the host system HOST. The power circuit removes noise from the voltage of the battery 105 and supplies it to the host system (HOST) and the module power supply of the display panel driving circuit.

In the display panel 100 , one or more corner portions CNR among corner portions where both sides meet are concave in a chamfered shape to have an inner angle θ of 180° or more and 300° or less. A front camera and/or one or more sensors may be disposed in a space secured by the corner portion CNR.

The screen of the display panel 100 includes a pixel array that displays an input image. The screen includes a main display unit 100A and an auxiliary display unit 100B. The main display part 100A is disposed below the corner part CNR.

The auxiliary display part 100B is disposed between two adjacent corner parts including the corner part CNR at the upper end of the display panel 100 . The above-described AP switch APTR may be disposed on the auxiliary display unit 100B. In the embodiment, an example in which the auxiliary display unit 100B is disposed on the main display unit 100A is shown, but the present invention is not limited thereto.

The auxiliary display unit 100B displays data in a full display mode and an always on mode. The data displayed on the auxiliary display unit 100B is data that is frequently viewed by the user, for example, data showing a communication state, a battery power state, a social network service (SNS) message, a clock, and the like. Data displayed on the auxiliary display unit 100B may be selected by a user.

Meanwhile, in the prior art, a pixel array is formed only on the main display unit 100A. For this reason, in the case of the prior art, the image is displayed only on the main display unit 100A. In a display panel of the prior art, an image cannot be displayed because pixels are not formed between corners on both sides where a camera or a sensor is disposed. In contrast, in the present invention, by arranging pixels in an area corresponding to the upper bezel in the prior art, extending them to the auxiliary display unit 100B, and optimizing a driving circuit for driving the pixel arrays formed in the auxiliary display unit 100B, the image image The display unit is enlarged to the auxiliary display unit 100B.

The main display unit 100A displays input image data in a full display mode, and is not driven to reduce power consumption in an always on mode. Accordingly, the main display unit 100A does not operate in an always on mode.

The display panel 100 includes an upper substrate and a lower substrate facing each other with a liquid crystal layer LC interposed therebetween. The pixel array of the display panel 100 includes pixels arranged in a matrix form by a cross structure of data lines DL and gate lines GL. The pixel array is divided into a main display unit 100A and an auxiliary display unit 100B. The data lines DL cross the main display unit 100A and the auxiliary display unit 100B and are connected to the pixels of the main display unit 100A and the pixels of the auxiliary display unit 100B. The gate lines GL are divided into gate lines GL connected to pixels of the main display unit 100A and gate lines GL connected to pixels of the auxiliary display unit 100B.

A TFT array may be formed on a lower substrate of the display panel 100 . The TFT array includes data lines DL, gate lines GL, a TFT formed at intersections of data lines DL and gate lines GL, a pixel electrode 11 connected to the TFT, and a pixel electrode. and a storage capacitor (Cst) connected to (11) and the like. The TFTs may be implemented as an amorphous silicon (a-Si) TFT, a LTPS (Low Temperature Poly Silicon) TFT, an oxide TFT (Oxide TFT), or the like. The TFTs are connected to the pixel electrodes of the sub-pixels. In FIG. 4 , “Clc” indicates the capacitance of the liquid crystal layer between the pixel electrode PXL and the common electrode COM.

The TFT is a switch element that supplies a data voltage applied through the data line DL to the pixel electrode PXL in response to a gate pulse from the gate line GL. Each of the pixels uses liquid crystal molecules driven by a voltage difference between the pixel electrode PXL to which the data voltage for charging the data voltage is supplied through the TFT and the common electrode COM to which the common voltage Vcom is applied. The input image is displayed by adjusting the amount of transmission.

In FIG. 19, “Ct” denotes an in-cell touch sensor embedded in a pixel array. The in-cell touch sensor Ct may be implemented with capacitance type touch sensors. Capacitive type touch sensors may be divided into self capacitance or mutual capacitance. In the in-cell touch technology, since the touch sensors Ct are coupled to the signal lines DL and GL of the pixels and the pixel electrode PXL, a signal applied to the pixels may act as noise to the touch sensors. there is. In order to reduce the mutual influence between the pixels and the touch sensors, one frame period of the display panel is divided into one or more display periods for writing input image data to the pixels, and one or more touch sensing periods for driving the touch sensors. divide the time The common electrode COM is divided into electrodes of the in-cell touch sensors. The divided common electrode COM supplies a common voltage Vcom that is a reference voltage of pixels during a display period and supplies electric charges to the in-cell touch sensors Ct during a touch sensing period.

A color filter array may be formed on the upper substrate of the display panel 100 . The color filter array includes a black matrix (BM) and a color filter (CF). The common electrode (COM) is formed on the upper substrate in the case of vertical electric field driving methods such as TN (Twisted Nematic) mode and VA (Vertical Alignment) mode, IPS (In-Plane Switching) mode and FFS (Fringe Field Switching) In the case of a horizontal electric field driving method such as a mode, it may be formed on the lower substrate together with the pixel electrode PXL.

A polarizing plate is attached to each of the upper and lower substrates of the display panel 100 , and an alignment layer for setting a pre-tilt angle of the liquid crystal is formed. The spacer is disposed between the upper substrate and the lower substrate to maintain a cell gap of the liquid crystal layer.

The present invention may further include a backlight unit for uniformly irradiating light to the display panel 100 . The display device of the present invention may be implemented in any form, such as a transmissive liquid crystal display, a transflective liquid crystal display, or a reflective liquid crystal display. A backlight unit is required in a transmissive liquid crystal display device and a transflective liquid crystal display device. The backlight unit may be implemented as a direct type backlight unit or an edge type backlight unit.

The display panel driving circuit includes a data driving circuit and a gate driving circuit to write input image data to pixels. The gate driving circuit may be implemented as a GIP circuit mounted on the display panel 100 . The GIP circuit includes a shift register composed of the stages described in the above-described embodiments. The GIP circuit includes a first GIP circuit GIP1 that supplies a gate pulse to the gate lines GL of the main display unit 100A, and a second GIP circuit that supplies a gate pulse to the gate lines GL of the auxiliary display unit 100B. It is divided into a GIP circuit (GIP2). The first GIP circuit GIP1 and the second GIP circuit GIP2 may be individually controlled under the control of the timing controller. In the always on mode, the first GIP circuit GIP1 does not operate and the second GIP circuit GIP2 operates, so that the gate pulses are supplied to the gate lines GL of the auxiliary display unit 100B. In the full display mode, the first GIP circuit GIP1 and the second GIP circuit GIP2 operate so that a gate pulse is applied to the gate lines GL of the main display unit 100A and the auxiliary display unit 100B. is supplied

The display panel driving circuit includes a timing controller and a module power supply. The module power supply unit generates power required for driving the display panel driving circuit and the display panel.

The display panel driving circuit may further include a backlight driving unit. The backlight driver adjusts the backlight brightness by varying the duty ratio of the dimming signal according to the input image. The dimming signal is generated as a PWM (Pulse Width Module) signal.

The backlight unit includes a plurality of light sources. The light sources may be implemented as Light Emitting Diodes (LEDs). The light sources include a first light source 50 for irradiating light to the main display unit 100A and a second light source 52 for irradiating light to the auxiliary display unit 100B. The backlight driver may individually control the light sources 50 and 52 in response to the mode signal. The second light source 52 may be disposed in a concave space secured by the corner portion CNR. In the normal driving mode, the backlight driver turns off the first light source 50 and turns on the second light source 52 to irradiate light to the auxiliary display unit 100B. The backlight driver illuminates the light sources 50 and 52 in the front driving mode to irradiate light to the main display unit 100A and the auxiliary display unit 100B.

Those skilled in the art from the above description will be able to see that various changes and modifications are possible without departing from the technical spirit of the present invention. Accordingly, the technical scope of the present invention should not be limited to the contents described in the detailed description of the specification, but should be defined by the claims.

PNL, 100: display panel SIC: data driving circuit
GIP : Gate drive circuit (GIP circuit) DIC : Drive IC

Claims (13)

data lines, gate lines orthogonal to the data lines, and a pixel array in which pixels are arranged in a matrix form defined by the data lines and the gate lines, and including a curved section having a center of a circle a display panel to;
a gate driving circuit formed outside the pixel array on the display panel to supply a gate pulse to the gate lines;
a plurality of auto probe pads disposed on one bezel area of the display panel;
a plurality of switch elements disposed on the other bezel area of the display panel with the pixel array interposed therebetween; and
a plurality of wires disposed in the pixel array to connect the auto probe pads and the switch elements;
The gate driving circuit includes a shift register to which stages are cascaded,
At least one of the stages is disposed along a curved line of the display panel and is out of an extension line of the gate line. The method of claim 1,
The long axis of the stage arranged along the curved line is parallel to an extension line connecting the ends of the gate line from the center of the circle. The method of claim 1,
The center of the minor axis length of the stage meets the extension line. The method of claim 1,
The gate driving circuit is
a first gate driving circuit disposed on one edge of the display panel; and
a second gate driving circuit disposed on the other edge of the display panel;
and the first gate driving circuit is connected to odd-numbered gate lines, and the second gate driving circuit is connected to even-numbered gate lines. 5. The method of claim 4,
The stages include adjacent stages whose distances from each other increase toward the end of the display panel,
When the circle has one end close to the center and the other end far from the center, a distance between one end of the adjacent stages is smaller than a distance between the other ends. 6. The method of claim 5,
A vertical width of each of the stages is less than or equal to twice a vertical width of one pixel. The method of claim 1,
and the stages are disposed above an extension of the gate line or below an extension of the gate line. The method of claim 1,
The stage is disposed to be inclined to have a predetermined angle with an extension line of the gate line. The method of claim 1,
the stages include a stage disposed below an extension line of the gate line;
The display device is disposed on a stage in which the switch elements are disposed below an extension line of the gate line. 10. The method of claim 9,
each of the switch elements includes a gate to which an enable signal is applied through the auto probe pad, a drain connected to the wiring, and a source connected to a data line of the pixel array. 10. The method of claim 9,
and the wirings are disposed between the data lines of the pixel array and the gate driving circuit. 10. The method of claim 9,
The display panel is divided into a main display unit and an auxiliary display unit,
The auxiliary display unit is driven in each of the front driving mode and the regular driving mode to display data,
The main display unit is driven in the front driving mode to display the data, and the display device is not driven in the normal driving mode. 13. The method of claim 12,
The gate driving circuit is
a first gate driving circuit for supplying the gate pulses to the gate lines of the main display unit; and
a second gate driving circuit for supplying the gate pulses to the gate lines of the auxiliary display;
In the always driving mode, the first gate driving circuit is not driven, and the second gate driving circuit is operated to supply the gate pulses to the gate lines of the auxiliary display unit;
In the front driving mode, the first gate driving circuit and the second gate driving circuit are driven to supply the gate pulses to the gate lines of the main display unit and the gate lines of the auxiliary display unit.

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