KR20160021060A - Display device - Google Patents

Abstract

The present invention relates to a display device which can have a gate driving circuit embedded in a heterogeneous display panel without increasing the bezel width. The display device comprises: a display panel including a curve section having the center of a circle; and a gate driving circuit formed outside a pixel array on a heterogeneous display panel, and supplying a gate pulse to gate lines. The gate driving circuit includes a shift resistor dependently coupled to stages. The stages are arranged along a curve line of the heterogeneous display panel. The major axis of the stages is parallel with an extension line connecting each end unit of the gate lines from the center of the circle.

Description

Display device {DISPLAY DEVICE}

The present invention relates to a display device in which a gate drive circuit is embedded in a display panel of a deformed display device in which the substrate structure of the display panel is not rectangular.

Wearable devices, flexible devices, instrument panels, and the like require various types of deformed display devices other than the conventional rectangular shape. For example, in a circular watch, a display panel is processed into a disc shape.

The driving circuit of the display device includes a pixel array in which an image is displayed, a data driving circuit for supplying a data signal to the data lines of the pixel array, a gate pulse (" Or a scan pulse), a timing controller for controlling the data driving circuit and the gate driving circuit, and the like. Recently, a technique of embedding a gate drive circuit in a display panel together with a pixel array has been applied. The gate drive circuit built in the display panel is known as a "GIP (Gate In Panel) circuit ". The GIP circuit includes a shift register. The shift register includes a plurality of stages connected in a dependent manner. The stages generate an output in response to the start pulse and shift the output according to the shift clock. Therefore, a start pulse, a shift clock, a drive voltage, and the like are supplied to the shift register.

In the display device, a gate drive circuit is connected to a display panel, as shown in FIG. 1, with a separate gate drive IC (Integrated Circuit) (GIC). This method not only increases the cost of the display device due to the IC cost, but also increases the number of routing lines RL, thereby increasing the bezel widths BZx and BZy. The routing wirings RL connect the output terminals of the gate drive IC to the gate lines. Therefore, the routing wirings RL are required by the number of gate lines of the pixel array. The bezel is a non-display area outside the pixel array.

When the GIP circuit is incorporated in the mold release display panel, the number of routing wirings RL can be reduced, but it is difficult to reduce the bezel width BZx. It is difficult to reduce the width of the bezel because the GIP circuit is elongated in the x-axis direction in order to secure the occupation space of the wirings supplying the start pulse, the shift clock and the driving voltage to the stages of the GIP circuit. Therefore, there is no example in which the GIP circuit is applied to the display device.

In order to perform the electrical inspection of the display panel in the manufacturing process of the display panel, pads or switch elements for electrical inspection may be formed on the substrate of the display panel. The switching elements may be implemented as TFTs formed on a substrate of a display panel simultaneously with a thin film transistor (hereinafter referred to as "TFT") of a pixel array.

BACKGROUND ART A liquid crystal display (LCD) displays an image by controlling an electric field applied to liquid crystal molecules in accordance with a data voltage. In a liquid crystal display device of an active matrix driving type, a TFT is formed for each pixel.

The manufacturing process of a liquid crystal display device includes the steps of cleaning a substrate of a liquid crystal display panel, patterning a substrate, forming / rubbing an alignment film, joining a substrate and adhering a liquid crystal, mounting a driver circuit, inspecting, repairing, do.

The substrate cleaning process removes contaminants from the upper glass substrate and the lower glass substrate of the liquid crystal display panel with a cleaning liquid. The substrate patterning process includes forming various thin film patterns such as signal lines including a data line and a gate line, a TFT, and a pixel electrode on a lower glass substrate, and forming a thin film pattern on the upper glass substrate using various types of black matrix, color filter, And forming and patterning the thin film material. In the alignment film forming / rubbing process, an alignment film is applied on glass substrates and the alignment film is rubbed with a rubbing film or optically aligned. Through the series of processes, the lower glass substrate of the liquid crystal display panel is provided with data lines to which video data voltages are supplied, gate lines that intersect the data lines and are supplied with scan signals, that is, gate pulses sequentially, TFTs formed at intersections of gate lines, pixel electrodes connected to TFTs, and storage capacitors are formed. A color filter array including a black matrix, a color filter, and a common electrode is formed on the upper glass substrate of the liquid crystal display panel. The common electrode is formed on the upper glass substrate in a vertical electric field driving method such as a TN (Twisted Nematic) mode and a VA (Vertical Alignment) mode, and a horizontal electric field such as IPS (In Plane Switching) mode and FFS (Fringe Field Switching) Is formed on the lower glass substrate together with the pixel electrode in the driving method. A polarizing plate and a polarizing plate and a protective film are attached to the upper glass substrate and the lower glass substrate, respectively.

The substrate coalescence and liquid crystal dropping process draws a sealant on one of the upper and lower glass substrates of the liquid crystal display panel and drops the liquid crystal on another substrate.

In the driving circuit mounting process, an integrated circuit (IC) of a data driving circuit is mounted on a lower glass substrate of a liquid crystal display panel using a COG (Chip On Glass) process or a TAB (Tape Automated Bonding) process. The gate driving circuit may be formed directly on the lower glass substrate of the liquid crystal display panel together with the TFT array by a GIP (Gate In Panel) process, or may be attached on the lower glass substrate by the TAB process in the driving circuit mounting process. The driving circuit mounting process connects the driving circuit ICs and the printed circuit board (PCB) with a flexible printed circuit board (FPC) or a flexible flat cable (FFC).

The inspecting process includes an inspection for a driver circuit, a wire inspecting of a data line and a gate line formed on a TFT array substrate, an inspecting after a pixel electrode is formed, an electrical inspecting after a liquid crystal dropping process, do. The repair process repairs defects found by the inspection process.

When the liquid crystal display panel completed through the above-described series of steps is completed, the assembly process of the liquid crystal module is performed. In the assembling process of the liquid crystal module, the backlight unit is aligned below the liquid crystal display panel, and the liquid crystal display panel and the backlight unit are assembled into the liquid crystal module using a mechanism such as a guide / case member.

In the auto-probe inspection, electrical inspection is performed on the substrate of the liquid crystal display panel prior to the driver circuit mounting process to inspect the signal wiring defect and the thin film pattern defect on the substrate.

(Hereinafter referred to as " AP pad ") in which a needle of an auto-probe inspection apparatus is contacted, and a signal wiring (hereinafter referred to as " AP probe " , "AP wiring"), and switch elements (hereinafter referred to as " AP switch ") connected between the AP wires and the signal wires of the pixel array. AP pads and AP wirings are formed in the bezel region BZ together with the GIP circuit. Therefore, it is difficult to secure a space for arranging the AP pads and the AP wirings in the bezel area of the deformed part or the bezel of the display device is narrow.

The present invention provides a display device capable of embedding a gate driving circuit in a mold release display panel without increasing the bezel width.

A display device of the present invention includes a pixel array in which pixels are arranged in a matrix form defined by data lines, gate lines orthogonal to the data lines, and the data lines and the gate lines, And a gate driving circuit formed outside the pixel array on the display panel to supply gate pulses to the gate lines.

Wherein the gate drive circuit includes a shift register to which stages are connected in a dependent manner, and at least one of the stages is disposed along a curved line of the display panel and out of an extension of the gate line.

According to the present invention, since the shift register of the gate drive circuit is arranged along the curved line of the display panel and at least one of the stages of the shift register is disposed at a position deviated from the extended line of the gate line, A driving circuit can be incorporated. Furthermore, the present invention can secure a space in the bezel of the mold release display panel by arranging the elements for electrical inspection by arranging the stage of the shift register above or below the extension of the gate line.

1 is a view showing a gate driving circuit applied to a conventional display device.
2 is a block diagram showing a driving circuit of a display device according to an embodiment of the present invention.
3 is a diagram showing a shift register configuration of the GIP circuit.
Figs. 4 and 5 are views showing various connection forms of the GIP circuit and gate lines when the GIP circuit is disposed on both sides of the mold release display panel.
Figs. 6 and 7 are views showing various examples of the variant display panel.
8 is a view showing an example in which the bezel is enlarged when the GIP circuit is incorporated in the mold release display panel.
9 and 10 are views showing a GIP circuit arrangement of a display apparatus according to an embodiment of the present invention.
FIG. 11 is an enlarged view of neighboring stages in FIGS. 9 and 10. FIG.
FIG. 12 is a diagram showing a right triangle having a height equal to the radius of a circle. FIG.
13 is a view showing an example of a gate drive circuit applied to a mold release display panel of a 5.5 "QHD (Quarter High Definition) product.
14 is a view illustrating various connection methods of stages and gate lines of a shift register in a bezel region of a display device according to an embodiment of the present invention.
15 is a view showing pads and wires for an automatic probe inspection in a display device according to an embodiment of the present invention.
16 is a detailed circuit diagram of AP pads, AP wiring, and AP switches for auto-probe inspection.
17 and 18 are views schematically showing a mobile terminal in which a display device according to an embodiment of the present invention is operated.
FIG. 19 is a plan view showing the display module shown in FIG. 18 in detail.

The display device of the present invention can be applied to a liquid crystal display (LCD), a field emission display (FED), a plasma display panel (PDP), an organic light emitting display , OLED), electrophoresis (EPD), and the like.

 DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Reference will now be made in detail to the preferred embodiments of the present invention, examples of which are illustrated in the accompanying drawings. Like reference numerals throughout the specification denote substantially identical components. In the following description, a detailed description of known functions and configurations incorporated herein will be omitted when it may make the subject matter of the present invention rather unclear.

2 and 3, a display device according to an exemplary embodiment of the present invention includes a mold release display panel PNL, a driving circuit for writing data of an input image to a pixel array of the display panel PNL, .

The mold release display panel (PNL) includes data lines, gate lines orthogonal to the data lines, and a pixel array in which pixels are arranged in a matrix form defined by the data lines and the gate lines. The mold release display panel PNL includes a curved section having the center of the circle as shown in FIGS. The input image is displayed on the pixel array.

Touch sensors can be placed on the mold release display panel (PNL). The touch sensors may be embedded in the pixel array. In this case, the display device of the present invention may further include a touch sensor driving circuit for driving the touch sensors.

The display driving circuit includes a data driving circuit SIC for supplying a data signal to the data lines 12 and a GIP circuit for sequentially supplying gate pulses synchronized with the data signals to the gate lines 14. [ A timing controller (T-con), not shown, transmits the digital data of the input image to the data driving circuit (SIC) and controls the operation timing of the data driving circuit (GIC) and the GIP circuit. The GIP circuit may be formed on one side edge of the mold release display panel or on both side edges outside the V pixel array.

The GIP circuit includes a shift register. The shift register includes stages S (N-2) to S (N + 2) that are connected in a dependent manner as shown in FIG. The stages S (N-2) to S (N + 2) start outputting the gate pulse in response to the start pulse Vst and shift the output in accordance with the shift clocks GCLK1 to GCLK4. Link wirings are connected to the stages S (N-2) to S (N + 2). The output signals of the stages S (N-2) to S (N + 2) are supplied to the gate lines G1 to Gn as gate pulses. Each of the stages has its output input as a start pulse of the next stage, and its output can also be input to the previous stage as a reset signal. The stages may output a carry signal separate from the gate pulse and supply the next stage as a start pulse.

The link wirings connected between the stages S (N-2) to S (N + 2) are connected to the stages S (N-2) through a start pulse Vst, shift clocks GCLK1 to GCLK4, To S (N + 2), and transmits a carry signal and a reset signal between the stages S (N-2) to S (N + 2). The driving voltage includes a high voltage and a low voltage of the gate pulse. The carry signal is input as the start pulse of the next stage, and the reset signal discharges the output of the previous stage.

Figs. 4 and 5 are views showing various connection forms of the GIP circuit and the gate lines when the GIP circuit is disposed on both sides of the mold release display panel (PNL).

4, the GIP circuit includes a first GIP (GIP (L)) circuit disposed at one edge of the mold release display panel PNL and a second GIP (R).

Each of the first and second GIP circuits GIP (L), GIP (R)) may be connected to all of the gate lines G1 to Gn. Each of the first and second GIP circuits GIP (L) and GIP (R)) receives the start pulse Vst at the same time and outputs a gate pulse at the same time. Therefore, the gate pulses output from the first and second GIP circuits (GIP (L), GIP (R)) are simultaneously applied to both ends of the same gate line.

Referring to FIG. 5, the first GIP circuit (GIP (L)) is connected to the first group of gate lines to sequentially supply gate pulses to the first group of gate lines. The second GIP circuit (GIP (R)) is connected to the gate lines of the second group to sequentially supply gate pulses to the gate lines of the second group.

The gate lines of the first group may be the odd-numbered gate lines (G1, G3, ..., Gn-1) as shown in FIG. The gate lines of the second group may be the even gate lines G2, G4, ... Gn as shown in FIG. The start pulse Vst may be applied to the first and second GIPs GIP (L) and GIP (R) with a predetermined time difference. Therefore, there may be a predetermined time difference between the gate pulse output timing of the first and second GIP circuits (GIP (R)) and the carry signal output timing. For example, after a first gate pulse is applied to the first gate line G1 from the first GIP circuit GIP (L), a second gate pulse is applied from the second GIP circuit GIP (R) A gate pulse may be supplied to the second gate line G2.

6 and 7 are views showing various examples of a mold release display panel according to an embodiment of the present invention.

Referring to Figs. 6 and 7, the mold release display panel can be processed into a curve having a predetermined curvature at least in part. Stages of the GIP circuit are arranged along the curved line of the mold release display panel (PNL). The stages S (N-2) to S (N + 2) are arranged along an extension line E connecting the ends of each of the gate lines GL from the center C of the circle in the curve. The long axis L of the stage is parallel to the extension line E connecting the ends of each of the gate lines GL from the center C of the circle and the center of the short axis length S of the stage meets the extension line E.

8 is a view showing an example in which the bezel is enlarged when the GIP circuit is incorporated in the mold release display panel.

Referring to FIG. 8, each of the stages of the GIP circuit may be connected to the gate lines GL in parallel, and arranged along the curved line of the mold release display panel. However, this method must reduce the short axis length (or the vertical width, S) of the stages S (N-2) to S (N + 2) in the curved section, -2) to S (N + 2)). When the circuit configuration of the stages is the same, when the short axis length of the stage is reduced, the length of the major axis (or width) becomes longer and the width of the bezel is increased. In Fig. 8, reference numeral 20 denotes a stage, and 22 denotes link wirings connecting the stages.

9 to 11, the present invention is characterized in that the stages of the GIP circuit are arranged along the curved lines of the mold release display panel (PNL), wherein the long axis direction of the stage, as shown in Figs. 6 and 7, So as to be parallel to the extension line E connecting the end of the gate line GL. Further, the stage arranged along the curved line deviates from the extension line 36 of the gate line GL as shown in Fig. 14 (A). As a result, the present invention allows the stages (S (N-2) to S (N + 2)) to be formed in a narrow exclusion region Can be placed along the curved line in FIG.

In the GIP circuit of the present invention, the stages include neighboring stages in which a distance between the adjacent stages increases toward the end of the display panel. Neighboring stages are arranged along the same curved line with the center of the circle (C). The gap g1 between one ends of the neighboring stages when the neighboring stages have one end closer to the center C and the other end farther from the center C than the distance between the other ends g2).

FIG. 9 shows an example in which the stages of the GIP circuit are connected in a 1: 1 relationship with the gate lines, FIG. 10 shows a case in which a GIP circuit is formed on each side of the display panel as shown in FIG. 5, G1, G3, G5, ..., Gn-1) and the even-numbered gate lines (G2, G4, G6 ... Gn). 10, the short axis length (or the vertical width) of each of the stages of the GIP circuit can be increased up to twice the vertical width P of the maximum one pixel (2P), so the bezel width BZ) can be further reduced. In other words, the vertical width of each of the stages is less than twice the vertical width of one pixel.

9 and 10, reference numeral 34 denotes a link wiring in which the gate line GL connects the stage.

The present invention can calculate the angle [theta] of the stages of the GIP circuit along the curved line in the mold release display panel based on the trigonometric function calculation of the right triangle having the hypotenuse having the same length as the radius (R) of the circle . Hereinafter, as shown in FIGS. 5 and 10, in the example in which the GIP circuits are disposed on both sides of the mold release display panel PNL, the odd-numbered gate lines are connected to the first GIP circuit, 12 will be described with reference to Figs. 12 and 13. Fig.

12 and 13, the radius R of the circle is determined by the curved line and the bezel size of the mold release display panel. It is assumed that the vertical width of each of the stages of the first and second GIP circuits GIP (L) and GIP (R) is a constant determined twice as much as the vertical width P of one pixel. The height H of the right triangle is calculated as an isomorphic sequence having a tolerance d with the number of the top gate line at which the first gate pulse is outputted in each of the first and second GIP circuits as '1'. The first gate line height (G1 height Hodd1) of the first GIP circuit (GIP (L)) and the first gate line height (G2 height Heven1) of the second GIP circuit GIP (R) (P). (N is a positive integer) of the odd-numbered gate lines G1, G3, G5 ... Gn-1 and the height sequence HevenN of the odd-numbered gate lines G2, G4, G6 ... Gn Is as follows.

HoddN = Hodd1 + (n-1) d

HevenN = Heven1 + (n-1) d

Given the radius R and height H of the circle, the angle? Is calculated as follows, so that the stage of the first GIP circuit connected to the odd-numbered gate lines G1, G3, G5 ... Gn- The stage angle AevenN of the first GIP circuit connected to the angle AoddN and the even gate lines G2, G4, G6 ... Gn is calculated as follows.

Based on this, as a result of applying to the 5.5 "QHD (Quarter High Definition) product standard, the stages of the GIP circuit connected to each of the gate lines could be arranged within 0.95 mm of the bezel as shown in FIG. One PXL size of 5.5 "QHD is 47.25 μm, the vertical width of the stage (GIP vertical width (d)) is 94.50 μm, and the radius of the circle (R) is 3050 μm.

14 is a view showing various connection methods of stages and gate lines of a GIP circuit in a bezel region of a display device according to an embodiment of the present invention.

14, in order to narrow the bezel region or to secure additional space for other circuits to be placed in the bezel region, the stage 30 of the shift register is disposed to extend beyond the extension line 36 of the gate line GL . Each of the stages 30 is connected in a dependent manner and is connected to the gate line GL through the link wiring 34. [

One or more of the stages 30 may be disposed on an extension line 36 of the gate line GL as shown in Fig. 14 (A). One or more of the stages 30 may be disposed under the extension line 36 of the gate line GL as shown in FIG. 14 (B). The angle between the extended line 36 of the gate line GL and the stage and the distance between the extended line 36 of the gate line GL and the stage 30 are determined by the width of the bezel region or the curvature of the curved line, And the like.

15 is a view showing pads and wires for an automatic probe inspection in a display device according to an embodiment of the present invention. 15 is an example in which a deformed portion is formed on the top of a pixel array in a mobile device. 16 is a detailed circuit diagram of AP pads, AP wiring, and AP switches for auto-probe inspection.

Referring to Figs. 15 and 16, the shift register of the GIP circuit is disposed in the left and right bezel regions outside the pixel array. The top of the pixel array has a mold release portion designed as a curved line. If the top bezel area is designed as a release, the bezel area becomes narrow and it is difficult to place devices for autoprobe inspection.

AP pads (APPAD), AP wirings (21 to 24), AP switches (APTR), and the like are formed on the substrate of the display panel to enable automatic probe inspection. The present invention places at least a part of the stages of the shift register disposed in the bezel region below the extension of the gate line GL in order to arrange the AP switch APTR in the upper bezel area of the display panel. Each of the stages is connected to the gate line GL via the link wiring 34. [

The stages of the shift register are arranged below the extended line of the gate line, thereby securing a space free of stages in the bezel region. The AP switches (APTR) can be arranged in the thus secured space.

The AP wirings include an enable wiring 21, a first test data wiring 22, a second test data wiring 23, and a third test data wiring 23. AP pads APPAD and AP switches APTR can be separated from each other across the pixel array in the display panel PNL.

The AP wirings 21 to 24 may be formed in the pixel array. The AP wirings 21 to 24 can be disposed in the pixel array without overlapping the data lines DL connected to the pixels and without lowering the aperture ratio of the pixels. The AP pads (APPAD) may be placed in the lower bezel with the drive IC (DIC). The AP pads APPAD are connected to the AP wirings 21 to 24.

The AP switch (APTR) may be disposed within the further secured upper bezel by arranging the stages 30 below the extension of the gate line. The AP switch APTR is disposed in the space reserved on the stages 30 including the first TFT T1, the second TFT T2 and the third TFT T3. The first TFT (T1) supplies the first test data signal to the first data line (DL) connected to the red subpixel in response to the enable signal (EN). The gate of the first TFT (T1) is connected to the enable wiring (21). The drain of the first TFT (T1) is connected to the first test data line (22), and the source of the first TFT (T1) is connected to the first data line (12). The first test data signal is supplied to the first test data wiring 22 through the needles in the inspection process. The second TFT (T2) supplies a second test data signal to the second data line (DL) connected to the green subpixel in response to the enable signal (EN). The gate of the second TFT (T2) is connected to the enable wiring (21). The drain of the second TFT T2 is connected to the second test data line 23 and the source of the second TFT T2 is connected to the second data line DL. The second test data signal is supplied to the second test data wiring 23 through the needles in the inspection process. The third TFT T3 supplies a third test data signal to the third data line DL connected to the blue subpixel in response to the enable signal EN. The gate of the third TFT (T3) is connected to the enable wiring (21). The drain of the third TFT T3 is connected to the third test data line 24 and the source of the third TFT T3 is connected to the third data line DL. The third test data signal is supplied to the third test data wiring 24 through the needles in the inspection process.

In the inspection process, the auto-probe inspection apparatus supplies an enable signal, an RGB test data signal through AP pads, and supplies gate test signals to GIP wirings via GIP pads (not shown). The GIP pads are connected to GIP wirings and contact the needles of the autoclave inspection device in the inspection process. The gate test signals include signals such as a start pulse, a shift clock, and the like for driving the shift register of the gate drive circuit (GIP). When the gate lines and the data lines are driven in this way, the driver IC (DIC) is not mounted on the display panel (PNL), and the presence of defects in the pixels and signal lines can be known.

The drive IC (DIC) includes a data driving circuit. The data driving circuit supplies a data voltage to the data lines connected to the pixels to write data to the pixels. A multiplexer (MUX) may be disposed between the data driving circuit and the pixel array as shown in FIG. The multiplexer (MUX) can reduce the number of output channels of the data driving circuit by dividing the data voltage from the data driving circuit. The drive IC (DIC) may further include a timing controller and a touch sensor driving circuit.

The timing controller transmits the data of the input image received from the host system to the data driving circuit. The timing controller controls the operation timing of the data driving circuit, the gate driving circuit, and the touch sensor driving circuit. The host system (FIG. 19, HOST) can be used in this embodiment as a phone system, a TV system, a set-top box, a navigation system, a DVD player, a Blu-ray player, It can be one.

17 and 18 are views schematically showing a mobile terminal in which a display device according to an embodiment of the present invention is operated. FIG. 19 is a plan view showing the display module shown in FIG. 18 in detail.

17 to 19, the mobile terminal of the present invention includes a display module, a front cover 101, a back cover 103, a mid frame, a main board 104, (105) and the like. Here, the "cover" may be represented by a case and a housing.

The display device of the present invention may be implemented as a flat panel display device such as a liquid crystal display (LCD), an organic light emitting diode (OLED) display, or the like. Note that the liquid crystal display (LCD) is mainly described in the embodiment, but the present invention is not limited thereto.

The display module includes the display panel 100 of the flat panel display device and the display panel drive circuit. In the display panel 100, touch sensors may be disposed on the entire screen. The display panel drive circuit includes a drive IC (DIC) and a flexible circuit board 106 connecting the drive IC (DIC) to the main board 104. The drive IC (DIC) writes the image data input through the main board 104 to the pixels of the display panel 100. The flexible circuit board may be any one of an FPC (Flexible Printed Circuit board) and an FFC (Flexible Flat Cable).

The front cover 101 may include a tempered glass covering the display panel 100. The front cover 101 covers the front surface of the mobile terminal. A front camera and various sensors may be disposed on the front of the mobile terminal. A back camera and various sensors may be disposed on the back of the mobile terminal. The sensors may be sensors that are applicable to mobile terminals, such as proximity sensors, gyro sensors, geomagnetism sensors, motion sensors, illuminance sensors, RGB sensors, Hall sensors, temperature / humidity sensors, And the like.

A display module, a mid frame 102, a main board 104, a battery 105, and the like are disposed in a space between the front cover 101 and the back cover 103. [ The mid frame 102 supports the display panel 100 and spatially separates the display panel 100 from the main board 104. [ The flexible circuit board 106 of the display module is connected to the main board 104 through a slot of the midframe 102. The front cover 101 and the back cover 103 are provided with an A / V (Audio / Video) input unit, a user input unit, a speaker, and a microphone. The A / U input unit, the user input unit, the speaker, and the microphone are connected to the main board 104. The user input unit may include a touch key pad, a dome switch, a touch pad, a jog wheel, a jog switch, and the like.

On the main board 104, the circuits of the host system HOST are mounted. The host system (HOST) includes a display module, a wireless communication module, a short distance communication module, a mobile communication module, a broadcast reception module, an A / U input portion, a GPS (Global Position System) module, A user input unit, a speaker, a microphone, a battery 105, and the like are connected to the host system HOST. The power supply circuit removes noise from the voltage of the battery 105 and supplies it to the host power supply unit of the host system HOST and the display panel driving circuit.

One or more corner portions (CNR) of corners where both sides meet at the sides of the display panel 100 are machined concavely in a chamfered shape to have an internal angle (?) Of 180 占 to 300 占. A front camera and / or one or more sensors may be disposed in the space secured by the corner portion (CNR).

The screen of the display panel 100 includes a pixel array for displaying an input image. The screen includes a main display portion 100A and an auxiliary display portion 100B. The main display portion 100A is disposed below the corner portion CNR.

The auxiliary display portion 100B is disposed between two adjacent corner portions including the corner portion CNR at the upper end of the display panel 100. [ The above-described AP switch (APTR) may be disposed on the auxiliary display section 100B. In the embodiment, the auxiliary display unit 100B is disposed on the main display unit 100A, but the present invention is not limited thereto.

The auxiliary display unit 100B displays data in a full display mode and an always on mode. The data displayed on the auxiliary display unit 100B is data showing data frequently seen by the user, such as a communication state, a battery power state, a social network service (SNS) message, a clock, and the like. The data displayed on the auxiliary display unit 100B can be selected by the user.

On the other hand, in the related art, a pixel array is formed only in the main display portion 100A. Therefore, in the case of the prior art, the image is displayed only on the main display section 100A. In the display panel of the related art, no pixels are formed between the corner portions on which the camera or the sensor is disposed, so that the image can not be displayed. In contrast, according to the present invention, pixels are arranged in an area corresponding to an upper bezel to extend the auxiliary display part 100B and optimize a driving circuit for driving the pixel arrays formed in the auxiliary display part 100B, The display section is enlarged to the auxiliary display section 100B.

The main display unit 100A displays the input image data in the full display mode and is not driven to reduce the power consumption in the always on mode. Therefore, the main display unit 100A does not operate in the always-on mode.

The display panel 100 includes an upper substrate and a lower substrate opposed to each other with the liquid crystal layer LC therebetween. The pixel array of the display panel 100 includes pixels arranged in a matrix form by an intersection structure of the data lines DL and the gate lines GL. The pixel array is divided into a main display portion 100A and an auxiliary display portion 100B. The data lines DL are connected to the pixels of the main display portion 100A and the pixels of the auxiliary display portion 100B across the main display portion 100A and the auxiliary display portion 100B. The gate lines GL are divided into gate lines GL connected to the pixels of the main display portion 100A and gate lines GL connected to the pixels of the sub display portion 100B.

On the lower substrate of the display panel 100, a TFT array may be formed. The TFT array includes a TFT formed at an intersection of data lines DL, gate lines GL, data lines DL and gate lines GL, a pixel electrode 11 connected to the TFT, (Storage Capacitor, Cst) connected to the storage capacitor 11, and the like. The TFTs may be implemented as an amorphous silicon (a-Si) TFT, a low temperature polysilicon (LTPS) TFT, or an oxide TFT (oxide TFT). The TFTs are connected to the pixel electrodes of the subpixels. 4, "Clc" represents the capacitance of the liquid crystal layer between the pixel electrode PXL and the common electrode COM.

The TFT is a switch element for supplying a data voltage applied to the pixel electrode PXL via the data line DL in response to a gate pulse from the gate line GL. Each of the pixels is driven by liquid crystal molecules driven by a voltage difference between a pixel electrode PXL to which a data voltage for charging a data voltage is supplied through a TFT and a common electrode COM to which a common voltage Vcom is applied, The input image is displayed.

In Fig. 19, "Ct" is an inshell touch sensor embedded in a pixel array. The in-line touch sensor Ct may be implemented as a capacitive-type touch sensor. Capacitive type touch sensors can be divided into self capacitance or mutual capacitance. Since the touch sensor Ct is coupled to the signal lines DL and GL of the pixels and the pixel electrode PXL, the signal applied to the pixels can act as noise to the touch sensors have. In order to reduce the mutual influence of the pixels and the touch sensors, one frame period of the display panel is divided into at least one display period for writing data of the input image to the pixels and at least one touch sensing period for driving the touch sensors Time-sharing. The common electrode COM is divided into electrodes of the in-cell touch sensors. The divided common electrode COM supplies a common voltage Vcom which is a reference voltage of pixels during a display period and supplies charges to the intellect touch sensors Ct during a touch sensing period.

A color filter array may be formed on the upper substrate of the display panel 100. The color filter array includes a black matrix (BM) and a color filter (CF). The common electrode COM is formed on the upper substrate in the case of a vertical field driving method such as a TN (Twisted Nematic) mode and a VA (Vertical Alignment) mode. In the IPS (In-Plane Switching) mode and the FFS (Fringe Field Switching) Mode may be formed on the lower substrate together with the pixel electrode PXL in the case of the horizontal electric field driving method.

A polarizing plate is attached to each of the upper substrate and the lower substrate of the display panel 100, and an alignment film for setting a pre-tilt angle of the liquid crystal is formed. The spacers are disposed between the upper substrate and the lower substrate to maintain a cell gap of the liquid crystal layer.

The present invention may further include a backlight unit for uniformly illuminating the display panel 100 with light. The display device of the present invention can be implemented in any form such as a transmissive liquid crystal display device, a transflective liquid crystal display device, and a reflective liquid crystal display device. In a transmissive liquid crystal display device and a transflective liquid crystal display device, a backlight unit is required. The backlight unit may be implemented as a direct type backlight unit or an edge type backlight unit.

The display panel driving circuit includes a data driving circuit and a gate driving circuit, and writes data of the input image to the pixels. The gate driving circuit may be implemented by a GIP circuit mounted on the display panel 100. [ The GIP circuit includes a shift register composed of the stages described in the above embodiments. The GIP circuit includes a first GIP circuit GIP1 for supplying a gate pulse to the gate lines GL of the main display section 100A and a second GIP circuit GIP1 for supplying a gate pulse to the gate lines GL of the sub display section 100B. And a GIP circuit (GIP2). The first GIP circuit GIP1 and the second GIP circuit GIP2 can be individually controlled under the control of the timing controller. In the always-on mode, the first GIP circuit GIP1 does not operate and the second GIP circuit GIP2 operates to supply gate pulses to the gate lines GL of the sub display unit 100B. The first GIP circuit GIP1 and the second GIP circuit GIP2 operate in the full display mode and gate pulses are applied to the gate lines GL of the main display unit 100A and the auxiliary display unit 100B .

The display panel drive circuit includes a timing controller and a module power supply unit. The module power supply generates power for driving the display panel drive circuit and the display panel.

The display panel driving circuit may further include a backlight driving unit. The duty ratio of the dimming signal is varied according to the input image of the backlight driving unit to adjust the backlight luminance. The dimming signal is generated as a PWM (Pulse Width Module) signal.

The backlight unit includes a plurality of light sources. The light sources may be implemented with LED (Light Emitting Diode). The light sources include a first light source 50 that emits light to the main display unit 100A and a second light source 52 that emits light to the auxiliary display unit 100B. The backlight driver can individually control the light sources 50 and 52 in response to the mode signal. And the second light source 52 can be disposed in the concave space secured by the corner portion CNR. The backlight driving unit turns off the first light source 50 and lights the second light source 52 in the normal driving mode to irradiate the auxiliary display unit 100B with light. The backlight driving unit illuminates the main display unit 100A and the auxiliary display unit 100B by turning on the light sources 50 and 52 in the front drive mode.

It will be apparent to those skilled in the art that various modifications and variations can be made in the present invention without departing from the spirit or scope of the invention. Therefore, the technical scope of the present invention should not be limited to the contents described in the detailed description of the specification, but should be defined by the claims.

PNL, 100: display panel SIC: data driving circuit
GIP: Gate drive circuit (GIP circuit) DIC: Drive IC

Claims (10)

Data lines, gate lines orthogonal to the data lines, and a pixel array in which pixels are arranged in a matrix form defined by the data lines and the gate lines, and includes a curved section with the center of the circle ; And
And a gate driving circuit formed outside the pixel array on the display panel to supply gate pulses to the gate lines,
Wherein the gate drive circuit includes a shift register to which stages are connected,
Wherein at least one of the stages is disposed along a curved line of the display panel and out of an extension of the gate line. The method according to claim 1,
Wherein a long axis of the stage arranged along the curved line is parallel to an extension line connecting the end of the gate line to the center of the circle. The method according to claim 1,
And the minor axis length center of the stage meets the extension line. The method according to claim 1,
The gate drive circuit
A first gate driving circuit disposed at one side edge of the display panel; And
And a second gate driving circuit disposed on the other edge of the display panel,
Wherein the first gate driving circuit is connected to the odd-numbered gate lines, and the second gate driving circuit is connected to the even-numbered gate lines. 5. The method of claim 4,
Wherein the stages include neighboring stages in which a distance between the adjacent stages becomes larger toward an end of the display panel,
Wherein a distance between one end of the neighboring stages is smaller than a distance between the other ends when one end near the center of the circle and the other end far from the center are located. 6. The method of claim 5,
Wherein the vertical width of each of the stages is not more than twice the vertical width of one pixel. The method according to claim 1,
Wherein the stages include a stage disposed over an extension of the gate line or below an extension of the gate line. The method according to claim 1,
And the stage is disposed obliquely so as to have an angle with an extension of the gate line. The method according to claim 1,
The stages including a stage disposed below an extension of the gate line,
Wherein the switch elements for electrical inspection of the display panel are arranged on a stage arranged below an extension of the gate line. 10. The method of claim 9,
Wherein the switch element comprises a gate to which an enable signal is applied via a pad, a drain coupled to the test data line, and a source coupled to the data line of the pixel array.

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