KR20170015672A - Display device - Google Patents

Abstract

The present invention relates to a display device having an array substrate of a thin film transistor. According to the present invention, a display device includes a display panel that receives data voltages through first to fourth data lines, a data driver that outputs data voltages to the first to fourth source channels, and a pad portion that connects the display panel with the data driver. First to fourth source pads are connected with the first to fourth source channels, respectively. The first to fourth data pads are connected with the first to fourth data lines, respectively. A first link pattern connects the first source pad with the first data pad. A second link pattern overlaps some areas of the second source pad and the second data pad. A third link pattern overlaps some areas of the third source pad and the third data pad. A fourth link pattern connects the fourth source pad with the fourth data pad. A fifth link pattern overlaps some areas of the second source pad and the third data pad. A sixth link pattern overlaps some areas of the third source pad and the second data pad.

Description

Display device {DISPLAY DEVICE}

The present invention relates to a display device having a thin film transistor array substrate.

An organic light emitting diode (OLED) display, a plasma display panel (PDP), an electrophoretic display device (EPD), a liquid crystal display (LCD) Various flat panel display devices have been developed. A liquid crystal display device displays an image by controlling an electric field applied to liquid crystal molecules in accordance with a data voltage. In a liquid crystal display device of an active matrix driving method, a thin film transistor (hereinafter referred to as "TFT") is formed at each intersection of a data line and a gate line for each pixel.

The liquid crystal display device includes a display panel in which pixels are arranged in a matrix form, a backlight unit for applying light to the display panel, a source drive integrated circuit (IC) for supplying a data voltage to the data lines of the display panel A gate driver IC for supplying gate pulses (or scan pulses) to the gate lines (or scan lines) of the display panel, and a control circuit for controlling the ICs, a light source driving circuit for driving the light sources of the backlight unit And the like. The input image is displayed on the pixel array of the display panel.

The pixels include R (Red) subpixel, G (Green) subpixel, and B (Blue) subpixel for color implementation. The pixels may further include W (White) subpixels in addition to RGB subpixels. The W subpixel can lower the brightness of the backlight unit by lowering the brightness of each of the pixels, thereby lowering the power consumption of the liquid crystal display device. Hereinafter, an RGB type display device refers to a display device in which pixels are divided into RGB subpixels, and an RGBW type display device refers to a display device in which pixels are divided into RGBW subpixels.

Since the RGBW type display device and the RGB type display device have different arrangements of the color pixels, the polarity pattern of the data voltages inputted to the RGBW type display device and the RGB type display device are different in consideration of image quality and power consumption. Therefore, since the RGBW type display device and the RGB type display device must use independent source drive ICs, there is a difficulty in manufacturing various display devices of common models.

The present invention provides a TFT array substrate and a source driver IC that can be applied to both RGB type display devices and RGBW type display devices.

The display device of the present invention includes a display panel that receives a data voltage through first to fourth data lines, a data driver that outputs a data voltage to the first to fourth source channels, and a pad portion that connects the display panel and the data driver do. The first to fourth source pads are respectively connected to the first to fourth source channels. The first to fourth data pads are connected to the first to fourth data lines, respectively. The first link pattern connects the first source pad and the first data pad. The second link pattern overlaps with a portion of the second source pad and the second data pad. The third link pattern overlaps with a portion of the third source pad and the third data pad. The fourth link pattern connects the fourth source pad and the fourth data pad. The fifth link pattern overlaps with some areas of the second source pad and the third data pad. The sixth link pattern overlaps with some areas of the third source pad and the second data pad.

The display device of the present invention provides a TFT array substrate that can be applied to two types of display devices through a connection method of a contact hole in a pad portion common to RGBW type display devices and RGB type display devices. The display device of the present invention provides a thin film transistor substrate which can be applied to both RGBW type display devices and RGB type display devices. In addition, since the connection structure of the link pattern of the pad portion can be changed so that the polarity input of the data voltage can be different according to the RGBW type display device and the RGB type display device, one source drive IC can be connected to the RGBW type display device and the RGB type It can be applied to all display devices. Particularly, the pad portion of the present invention has the same link pattern as that of each electrode pad applied to the RGBW type display device and the RGB type display device, and only the mask is changed in the course of etching the passivation layer, It is possible to realize a link structure of the pad portion which can be applied to all of the display devices.

1 is a block diagram showing a display device according to an embodiment of the present invention.
2 is an equivalent circuit diagram showing a part of the TFT array substrate of the display panel shown in Fig.
3 is a view showing a color arrangement in an RGBW type display device.
4 is a view showing a color arrangement in an RGB type display device.
5 is a view showing a source driver IC according to the first embodiment.
6 is a waveform diagram showing a polarity control signal of the RGBW type display device.
7 is a diagram illustrating the polarity of pixels determined according to the polarity control signal shown in FIG.
8 is a diagram showing the output of the data voltage in the RGBW type display device.
9 is a schematic diagram showing a connection structure of a pad portion in an RGB type display device.
10 is a diagram showing the output of the data voltage in the RGB type display device.
11 is a view showing a source driver IC according to the second embodiment.
12 is a plan view showing a pad portion according to the first embodiment.
13 is a cross-sectional view showing a pad portion cut along the line A-A 'in FIG.
14 is a plan view showing a pad portion according to the second embodiment.
15 is a cross-sectional view showing a pad portion cut along the line A-A 'in Fig.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Reference will now be made in detail to the preferred embodiments of the present invention, examples of which are illustrated in the accompanying drawings. Like reference numerals throughout the specification denote substantially identical components. In the following description, a detailed description of known functions and configurations incorporated herein will be omitted when it may make the subject matter of the present invention rather unclear.

1, the display apparatus of the present invention includes a display panel 100 and a display panel drive circuit for writing data of an input image on the display panel 100. [ A backlight unit for uniformly irradiating light to the display panel 100 may be disposed under the display panel 100.

In order to reduce the number of source driver ICs, this display device implements a double rate driving (DRD) display device in which two adjacent subpixels in a horizontal direction (x axis or row line direction) share one data line. The DRD display device can reduce the number of source drive ICs to 1/2 because the number of data lines is reduced. In the DRD display device, the operating frequency of the source drive IC is doubled.

The display panel 100 includes a TFT array substrate and a color filter array substrate facing each other with a liquid crystal layer interposed therebetween. The display panel 100 includes pixels arranged in a matrix form by an intersection structure of the data lines S1 to Sm and the gate lines G1 to Gn. Each of the pixels is divided into RGB subpixels or RGBW subpixels.

The TFT array substrate of the display panel 100 is provided with data lines S1 to Sm, gate lines G1 to Gn, a TFT disposed at the intersection of the data line and the gate line, a pixel electrode 11 connected to the TFT, And a storage capacitor (Cst) connected to the pixel electrode 11, and the like. Each of the pixels adjusts the amount of light transmitted by using liquid crystal molecules driven by the voltage difference between the pixel electrode 11 charging the data voltage through the TFT and the common electrode 12 applied with the common voltage Vcom And displays an image of the video data.

The color filter substrate of the display panel 100 is provided with a color filter array including a black matrix and a color filter. The common electrode 12 is formed on the upper substrate in the case of a vertical electric field driving method such as a TN (Twisted Nematic) mode and a VA (Vertical Alignment) mode. The common electrode 12 is divided into an IPS (In-Plane Switching) mode and an FFS (Fringe Field Switching) The pixel electrode 11 may be formed on the TFT array substrate in the case of the horizontal electric field driving method such as the mode. On the TFT array substrate and the color filter array substrate of the display panel 100, an alignment film for attaching a polarizing plate and setting a pre-tilt angle of liquid crystal is formed.

The display device of the present invention can be implemented in any form such as a transmissive liquid crystal display device, a transflective liquid crystal display device, and a reflective liquid crystal display device. In a transmissive liquid crystal display device and a transflective liquid crystal display device, a backlight unit is required. The backlight unit may be implemented as a direct type backlight unit or an edge type backlight unit.

The display panel drive circuit writes the data of the input image to the pixels. The display panel drive circuit includes a data driver 102, a gate driver 104, a timing controller 20, and a gamma correction unit 22. In an RGB type display device, data written to pixels includes R data, G data, and B data. In an RGBW type display device, data written to pixels includes R data, G data, B data, and W data.

The data driver 102 includes a plurality of source drive ICs. The data source channels of the source drive ICs are connected to the data lines S1 to Sm. The source drive ICs receive the digital video data of the input image from the timing controller 20. [ In the RGB type display device, the digital video data transmitted to the source drive ICs includes R data, G data, and B data. In the RGBW type display device, the digital video data transmitted to the source drive ICs includes R data, G data, B data, and W data. The source driver ICs convert the digital video data of the input image into the positive / negative gamma compensation voltages under the control of the timing controller 20, and output the positive / negative data voltages. The output voltage of the data driver 102 is supplied to the data lines S1 to Sm.

Two horizontally adjacent subpixels share one data line and are supplied with time-divided data voltages through the data line as shown in FIG. Due to the shared structure of the data lines, the number of data lines and the number of source driver ICs can be reduced compared to a general pixel array structure at the same resolution.

Each of the source driver ICs can reverse the polarity of the data voltage to be supplied to the pixels under the control of the timing controller 20 to an inversion period of 2 horizontal periods or longer and N / 2 (N is the vertical resolution of the display panel) horizontal period or less . The embodiment of the present invention exemplifies the example in which the polarity of the data voltage is inverted every two horizontal periods (2H), but is not limited thereto. The four-color data voltages sequentially output from the source driver IC for two horizontal periods are charged to four subpixels sharing the same data line.

The source drive ICs maintain the same polarity of the four-color data voltages to be charged in four sub-pixels during two horizontal periods (2H) in response to the polarity control signal POL received from the timing controller 20, The polarity of the data voltage is inverted every period 2H. Thus, the source drive ICs continuously output eight data voltages during four horizontal periods (4H), reversing the polarity of the data voltages in two horizontal periods. In the present invention, the polarity inversion period of the data voltage is long, so that the number of transitions of the data voltage is small. As a result, the power consumption and heat generation of the source drive ICs of the present invention can be reduced. The source driver ICs can further reduce the number of transitions of the data voltage by inverting the polarity of the data voltage to be supplied to the pixels to four horizontal period periods under the control of the timing controller 20. [

The gate driver 104 sequentially supplies gate pulses to the gate lines G1 to Gn under the control of the timing controller 20. [ The gate pulse output from the gate driver 104 is synchronized with the positive / negative polarity video data voltages to be charged to the pixels. The gate driver 104 may be formed directly on the TFT array substrate of the display panel 100 in the same manufacturing process to reduce the IC cost. The gate driver 104 formed directly on the lower substrate of the display panel 100 is known as a "gate in panel " (GIP) circuit.

The timing controller 20 transmits the data of the input image received from the host system 30 to the data driver 102. An interface for data transmission between the timing controller 20 and the source driver ICs of the data driver 102 may be a mini-LVDS (low voltage differential signaling) interface or an EPI (Embedded Panel Interface) interface.

The timing controller 20 receives timing signals synchronized with the input image data from the host system 24. The timing signals include a vertical synchronization signal Vsync, a horizontal synchronization signal Hsync, a data enable signal DE, a dot clock DCLK, and the like. The timing controller 20 controls the operation timings of the data driver 102 and the gate driver 104 based on the timing signals Vsync, Hsync, DE, and DCLK received together with the pixel data of the input image. The timing controller 20 may transmit a polarity control signal POL to each of the source drive ICs of the data driver 102 to control the polarity of the pixels. The Mini LVDS interface transmits the polarity control signal via separate control wiring. The EPI interface encodes the polarity control information in the control data packet transmitted between the clock training pattern for CDR (Clok and Data Recovery) and the RGB / RGBW data packet and transmits it to each of the source drive ICs to be.

The timing controller 20 can convert RGB data of the input image into RGBW data using a known white gain calculation algorithm. The white gain calculation algorithm can be any known one.

The host system 24 may be any one of a TV system, a set-top box, a navigation system, a DVD player, a Blu-ray player, a personal computer (PC), a home theater system, and a phone system.

The timing controller 20 refers to a set value stored in an EEPROM (Electrically Erasable Programmable Read-Only Memory) 21 and generates a data / gate timing control signal for controlling the operation timing of the data driver 102 and the gate driver 104 . Rising edge timing, pulse duration, falling edge timing, and the like for the data / gate timing control signal are preset in the EEPROM 21.

The present invention shares the TFT array substrate and the data driver 102 in the RGB type display device and the RGBW type display device.

2 is an equivalent circuit diagram showing a part of a TFT array substrate which can be commonly used in an RGB type display device and an RGBW type display device. In FIG. 2, the common electrode 12 and the storage capacitor Cst are omitted.

Referring to FIG. 2, a connection relationship of subpixels sharing the same data line S 1 and sequentially charging the same polarity data voltage will be described below.

When the subpixels arranged on the odd-numbered line of the display panel 100 are referred to as P1 to P4 and the subpixels arranged on the odd-numbered line of the display panel 100 are referred to as P5 to P8, The relationship is as follows.

The first subpixel P1 supplies a first data voltage supplied to the first pixel electrode PIX1 through the first data line S1 in response to a gate pulse supplied from the first gate line G1. 1 TFT (T1). The first TFT T1 includes a gate connected to the first gate line G1, a drain connected to the first data line S1, and a source connected to the first pixel electrode PIX1.

The second subpixel P2 supplies a second data voltage supplied to the second pixel electrode PIX2 through the first data line S1 in response to a gate pulse supplied from the second gate line G2. 2 TFT (T2). The second TFT T2 includes a gate connected to the second gate line G2, a drain connected to the first data line S1, and a source connected to the second pixel electrode PIX2.

The third subpixel P6 supplies the third data voltage supplied to the third pixel electrode PIX3 through the first data line S1 in response to the gate pulse supplied from the third gate line G3. 3 TFT (T3). The third TFT T3 includes a gate connected to the third gate line G3, a drain connected to the first data line S1, and a source connected to the third pixel electrode PIX3.

The fourth subpixel P5 applies a fourth data voltage supplied through the (J + 1) th data line S1 to the fourth pixel electrode PIX4 in response to the fourth gate pulse from the fourth gate line G4 And a fourth TFT T4 for supplying the fourth TFT T4. The fourth TFT T4 includes a gate connected to the fourth gate line G4, a drain connected to the first data line S1, and a source connected to the fourth pixel electrode PIX4.

The connection relationship of the subpixels P3, P4, P7 and P8 sharing the second data line S2 is the same as that of the subpixels P1, P2, P5 and P6 except for the data lines.

3 shows a color arrangement in an RGBW type display device. In Fig. 3, the odd-numbered lines of the color filter substrate are arranged in the RGBW order, and the even-numbered lines are arranged in the BWRG order. 4 shows a color arrangement in an RGB type display device. In Fig. 4, color filters are arranged in RGB order on the odd-numbered line and the even-th line of the color filter substrate, respectively.

5 is a circuit diagram showing a source drive IC according to the first embodiment of the present invention. 6 is a waveform diagram showing a polarity control signal of the RGBW type display device. 6 shows the polarity control signals POL (S1) to POL (S4) supplied to the first to fourth data lines S1 to S4. Lt; / RTI > shows the polarity of the pixels.

5 to 7, the source drive IC includes a plurality of buffers P1, P2, N3, and N4, a plurality of switches, and a plurality of source channels OUT1 to OUT4.

The buffers P1, P2, N3 and N4 include P buffers P1 and P2 for supplying positive polarity data voltages (+ Vdata) input from the PDAC to the source channels, and negative polarity data voltages -Vdata) to the source channels. The first P buffer P1 includes first data Data1 to be supplied to the first data line S1 through the first source channel OUT1 and third data Data1 to be supplied to the third data line S3 (+ Vdata) of the third data (Data3) to be supplied to the first data (Data3). The second P buffer P2 supplies the second data Data2 to be supplied to the second data line S2 through the second source channel OUT2 and the fourth data line S4 (+ Vdata) of the fourth data (Data4) to be supplied to the first data line (Data1). The first N buffer N3 includes first data Data1 to be supplied to the first data line S3 through the first source channel OUT1 and third data line Data2 to be supplied to the third data line S3 (-Vdata) of the third data (Data3) to be supplied to the third data (Data3). The second N buffer N4 supplies the second data Data2 to be supplied to the second data line S2 through the second source channel OUT2 and the fourth data line S4 through the fourth source channel OUT4. (-Vdata) of the fourth data (Data4) to be supplied to the second data line (Data1).

The switches include a multiplexer (MUX) for data distribution, switches SW1 to SW4 for supplying data voltages, switches SW5 and SW6 for charge share, and the like.

The multiplexer includes mux switches SA1, SB1, SA3, SB3, SC2, SD2, SC4, and SD4 that distribute the data voltages output through one buffer to a plurality of source channels. The multiplexer selects the polarities of the data voltages (+ Vdata, -Vdata) in response to the polarity control signals POL (S1), POL (S2), POL (S3) and POL (S4) shown in FIG.

The first MUX switch SA1 connected to the first P buffer P1 is connected to the output terminal of the first P buffer P1 in response to the first logic value of the first polarity control signal POL The second MUX switch SB1 connected to the first P buffer P1 is connected to the first P buffer P1 in response to the first logical value of the first polarity control signal POL (S1) Output terminal to the third source channel OUT3. The first and second MUX switches SA1 and SB1 are turned on when the first polarity control signal POL (S1) is the second logical value, )do.

The third MUX switch SC2 connected to the second P buffer P2 is connected to the output terminal of the second P buffer P2 in response to the first logic value of the second polarity control signal POL The second MUX switch SD2 connected to the second P buffer P2 is connected to the second P buffer P2 in response to the first logical value of the second polarity control signal POL (S2) And the output terminal is connected to the fourth source channel OUT4. The third and fourth MUX switches SC2 and SD2 are turned off when the second polarity control signal POL (S2) is the second logic value.

The fifth MUX switch SB3 connected to the first N-buffer N3 is connected to the output terminal of the first N-buffer N3 in response to the second logic value of the third polarity control signal POL (S3) The sixth MUX switch SA3 connected to the first N-buffer N3 is connected to the first N-buffer N3 in response to the second logic value of the third polarity control signal POL (S3) And the output terminal is connected to the third source channel OUT3. The fifth and sixth MUX switches SB3 and SA3 are turned off when the third polarity control signal POL (S3) is the first logic value.

The seventh MUX switch SD4 connected to the second N buffer N4 is connected to the output terminal of the second N buffer N2 in response to the second logic value of the fourth polarity control signal POL4, The fourth multiplexer switch SC4 connected to the second N buffer N4 is connected to the second N buffer N2 in response to the second logic value of the fourth polarity control signal POL4 And the output terminal is connected to the fourth source channel OUT4. The seventh and eighth MUX switches SD4 and SC4 are turned off when the fourth polarity control signal POL (S4) is the first logic value.

The data voltage supply switches SW1 to SW4 are disposed between the multiplexer and the source channel to supply the positive polarity data voltage (+ Vdata) and the negative polarity data voltage (-Vdata) from the multiplexer to the source channels OUT1 to OUT4 Supply. Each of the data voltage supply switches SW1 to SW4 includes an input terminal connected to two MUX switches and an output terminal connected to one source channel.

Switches for charge share (SW5, SW6, hereinafter referred to as "CS switch") connect source channels in which the polarity of the data voltage changes simultaneously when the polarity of the data voltage changes.

The first CS switch SW5 is connected to the first and third source channels OUT1 and OUT3 connected to the data lines of the first data line group. The first CS switch SW5 is turned on at the first charge share timing to charge-share the data lines S1 and S3 of the first data line group. The first charge share timing is controlled by the first source output enable signal SOE1. The first CS switch SW5 connects the first and third source channels OUT1 and OUT3 in response to the first logic value of the first source output enable signal SOE1 to generate a charge share .

The second CS switch SW6 is connected to the first and third source channels OUT1 and OUT3 connected to the data lines S2 and S4 of the second data line group. The second CS switch SW6 is turned on at the first charge share timing to charge-share the data lines S2 and S4 of the second data line group. The second charge share timing is controlled by the second source output enable signal SOE2. The second CS switch SW6 connects the second and fourth source channels OUT2 and OUT4 in response to the first logic value of the second source output enable signal SOE2 to generate a charge share .

The source driver IC inverts the polarity of the data voltage in response to the first to fourth polarity control signals POL (S1) to POL (S4). The polarity of the pixels is controlled by the polarity control signals POL (S1) 7 by the POL (S4). The pixel array includes pixels whose polarities of the data voltages are inverted in units of one dot between neighboring subpixels and pixels whose polarities of the data voltages are inverted in units of two dots The polarity control signals POL (S1) to POL (S4) as shown in FIG. 6 can be seen when the same polarity is concentrated in lines or blocks in the RGBW display device The polarity control signals POL (S1) to POL (S4) as shown in FIG. 6 can prevent the polarity of the pixels arranged along the vertical and horizontal directions in the RGBW display device It is possible to prevent the common voltage Vcom from being shifted When the common voltage Vcom is shifted, the data voltage charging rate between the positive polarity pixel and the negative polarity pixel at the same gray level changes, resulting in a luminance difference between the positive pixel and the negative polarity pixel. (POL (S1) to POL (S4) can realize the optimum image quality in the RGBW display device.

The inventors of the present invention have repeatedly conducted various image quality tests and found that the image quality is deteriorated when the polarity control signals POL (S1) to POL (S4) as shown in FIG. 6 are applied to RGB display devices. An optimum polarity control method that does not deteriorate the picture quality when the TFT array substrate of the RGBW display device is applied to the RGB display device is derived by repeatedly experimenting with many picture quality tests while changing the polarity of the pixel array with the polar pattern of various candidates. This polarity control method will be described with reference to Figs. 8 and 9. Fig.

8 shows the polarities of the data voltages supplied to the first to fourth data lines S1 to S4 of the RGB type display device, and Fig. 9 shows the polarity of the pixels determined by the data voltages shown in Fig. to be.

As shown in FIG. 9, the pixel array includes pixels whose polarities of the data voltages are inverted in units of one dot between neighboring subpixels, and pixels whose polarities of the data voltages are inverted in units of two dots. A pixel array represented by the polarity as shown in Fig. 9 can prevent a luminance difference and flicker which may be seen when the same polarity concentrates in line or block form in an RGB display device. Also, the polarities of the pixels arranged along the vertical and horizontal directions in FIG. 9 and the RGB display device are not shifted to one side, and the shift of the common voltage Vcom can be prevented.

The polarity of the data voltage shown in Fig. 8 is such that the polarities of the first and second data voltages are symmetrical to each other, and the polarities of the third and fourth data voltages are symmetrical to each other. As described above, in order to change the timing at which the provided polarities of the data lines are inverted, each of the source drive ICs must be used. However, when the polarity of the data voltage shown in FIG. 8 is compared with the polarity of the data voltage shown in FIG. 6, the polarities of the second and third data voltages are reversed. Therefore, the display device of the present invention can be applied to the RGB type display panel as shown in FIG. 4 by changing the pad structure of the data line connected to the source channel as shown in FIG.

11 is a circuit diagram showing a source drive IC according to a second embodiment of the present invention. In Fig. 11, the shift register, latch, DAC, etc. of the source drive IC are omitted.

Referring to FIG. 11, the source drive IC includes a plurality of buffers P1, P2, N3, N4, a plurality of switches, and a plurality of source channels OUT1 to OUT4.

The buffers P1, P2, N3 and N4 include P buffers P1 and P3 for supplying a positive data voltage (+ Vdata) input from the PDAC to the source channels, and a negative data voltage -Vdata) to the source channels. The P buffers P1 and P3 and the N buffers N2 and N4 may be alternately arranged as shown in FIG. The first P buffer P1 includes first data Data1 to be supplied to the first data line S1 through the first source channel OUT1 and second data Data1 to be supplied to the second data line S2 (+ Vdata) of the second data (Data2) to be supplied to the second data (Data2). The first N buffer N2 includes first data Data1 to be supplied to the first data line S3 through the first source channel OUT1 and second data Data1 to be supplied to the second data line S2 (-Vdata) of the second data (Data2) to be supplied to the second data line (Data2). The second P buffer P3 is connected to the third data Data3 to be supplied to the third data line S3 through the third source channel OUT3 and the third data Data3 to be supplied to the fourth data line S4 (+ Vdata) of the fourth data (Data4) to be supplied to the first data line (Data1). The second N buffer N4 supplies the third data Data3 to be supplied to the third data line S3 through the third source channel OUT3 and the third data Data3 to be supplied to the fourth data line S4 (-Vdata) of the fourth data (Data4) to be supplied to the second data line (Data1).

The switches include a multiplexer (MUX) for data distribution, switches S1 to S4 for supplying data voltages, switches S5 and S6 for charge share, and the like.

The multiplexer MUX includes MUX switches SA1, SB1, SA3, SB3, SC2, SD2, SC4, and SD4 that distribute the data voltages output through one buffer to a plurality of source channels. The multiplexer MUX selects the polarity of the data voltages (+ Vdata, -Vdata) in response to the polarity control signals POL (S1), POL (S2), POL (S3) and POL (S4).

The data voltage supply switches SW1 to SW4 are disposed between the multiplexer and the source channel to supply the positive polarity data voltage (+ Vdata) and the negative polarity data voltage (-Vdata) from the multiplexer to the source channels OUT1 to OUT4 Supply. Each of the data voltage supply switches S1 to S4 includes an input terminal connected to two MUX switches and an output terminal connected to one source channel. The first and second data voltage supply switches SW1 and SW2 supply the positive and negative polarity data voltages to the first and second source channels SW1 and SW2 in response to the second logic value of the first source output enable signal SOE1, (OUT1, OUT2). The third and fourth data voltage supply switches SW3 and SW4 are turned on in response to the second logic value of the second source output enable signal SOE2 to supply the positive and negative polarity data voltages to the third and fourth source channels (OUT3, OUT4).

The CS switches SW5 and SW6 connect the source channels whose polarity of the data voltage changes simultaneously when the polarity of the data voltage changes. The first CS switch SW5 is connected to the first and second source channels OUT1 and OUT2 and is responsive to the first logic value of the first source output enable signal SOE1 to generate the first and second source channels OUT1 and OUT2, (OUT1, OUT2) are connected to perform charge sharing. The second CS switch SW6 is connected to the third and fourth source channels OUT3 and OUT4 and is responsive to the first logic value of the second source output enable signal SOE2 to generate the third and fourth source channels & (OUT3, OUT4) are connected to perform charge sharing.

The source drive IC according to the second embodiment shown in Fig. 11 outputs the data voltage of the polarity as shown in Fig. That is, the source drive IC of the second embodiment is advantageous to be applied to the RGB type display panel.

However, as in the first embodiment, the source drive IC shown in FIG. 11 can exhibit the same effect as the drive using the polarity control signal shown in FIG. 6 by changing the pad portion of the display panel as shown in FIG.

In order to apply the source drive ICs shown in FIGS. 5 and 11 to the RGBW type display panel and the RGB type display panel, respectively, the connection structure of the pad portion must be designed differently. The present invention proposes a pad unit as follows to share the pad unit of the display panel.

FIG. 12 is a plan view of the pad portion according to the first embodiment, and FIG. 13 is a view showing a section cut along the line A-A 'shown in FIG. FIG. 14 is a plan view of the pad portion according to the second embodiment, and FIG. 15 is a sectional view taken along the line A-A 'shown in FIG. The pad portion according to the first embodiment shows details of the pad portion shown in Figs. 5 and 11, and the pad portion according to the second embodiment shows the structure of the pad portion shown in Fig. The pad portion according to the present invention has the same process of forming the metal array layer and the pads, and can be divided into the first and second embodiments according to the formation positions of the contact holes.

12 and 13, the pad unit 110 according to the first embodiment includes first to fourth source pads SP 1, SP 2, SP 3 and SP 4, first to fourth data pads DP 1 and DP 2, DP3 and DP4, and first to sixth link patterns LINK1, LINK2, LINK3, LINK4, LINK5 and LINK6. The first to fourth source pads SP 1 to SP 4 are connected to the first to fourth source channels OUT 1 to OUT 4 and the first to fourth data pads DP 1 to DP 4, DP3 and DP4 are connected to the first to fourth data lines S1, S2, S3 and S4, respectively.

A process of forming the pad portion 110 will be briefly described below. The first to fourth source pads SP 1, SP 2, SP 3 and SP 4 are formed using a first metal layer on the substrate GLS. The first to fourth data pads DP1, DP2, DP3 and DP4 are formed on the insulating film GI so as to cover the first to fourth source pads SP1, SP2, SP3 and SP4. do. The passivation layer PAS is formed to cover the first to fourth data pads DP1, DP2, DP3 and DP4. The first through fourth contact holes CONT1, CONT2, CONT3 and CONT4 are formed by selectively etching the passivation layer PAS using a mask.

The first source pad SP1 is connected to the first link pattern LINK1 through the first contact hole CONT1 and the first data pad SP1 is connected to the first link pattern CONT2 through the second contact hole CONT2. LINK1). Therefore, the data voltage output from the first source channel OUT1 is connected to the first data line S1.

The second source pad SP2 is connected to the second link pattern LINK2 through the third contact hole CONT3 and the second data pad SP2 is connected to the second link pattern L4 through the fourth contact hole CONT4. LINK2). Therefore, the data voltage output from the second source channel OUT2 is connected to the second data line S2.

The third source pad SP3 is connected to the third link pattern LINK3 through the fifth contact hole CONT5 and the third data pad DP3 is connected to the third link pattern CONT3 through the sixth contact hole CONT6. LINK3). Accordingly, the data voltage output from the third source channel OUT3 is connected to the third data line S3.

The fourth source pad SP4 is connected to the fourth link pattern LINK4 via the seventh contact hole CONT7 and the fourth data pad DP4 is connected to the fourth link pattern CONT4 through the eighth contact hole CONT8. LINK4). Therefore, the data voltage output from the fourth source channel OUT4 is connected to the fourth data line S4.

14 and 15, the pad portion 111 according to the second embodiment includes first to fourth source pads SP 1, SP 2, SP 3 and SP 4, first to fourth data pads DP 1, DP 2, DP3 and DP4 and first to sixth link patterns LINK1, LINK2, LINK3, LINK4, LINK5 and LINK6. The first to fourth source pads SP 1 to SP 4 are connected to the first to fourth source channels OUT 1 to OUT 4 and the first to fourth data pads DP 1 to DP 4, DP3 and DP4 are connected to the first to fourth data lines S1, S2, S3 and S4, respectively.

The first source pad SP1 is connected to the first link pattern LINK1 through the first contact hole CONT1 and the first data pad DP1 is connected to the first link pattern CONT2 through the second contact hole CONT2. LINK1). Therefore, the data voltage output from the first source channel OUT1 is connected to the first data line S1.

The second source pad SP2 is connected to the fifth link pattern LINK5 through the third contact hole CONT3 and the third data pad DP3 is connected to the fifth link pattern L4 through the fourth contact hole CONT4. LINK5). Therefore, the data voltage output from the second source channel OUT2 is connected to the third data line S3.

The third source pad SP3 is connected to the sixth link pattern LINK6 through the fifth contact hole CONT5 and the second data pad DP2 is connected to the sixth link pattern L6 through the sixth contact hole CONT6. LINK6). Therefore, the data voltage output from the third source channel OUT3 is connected to the second data line S2.

The fourth source pad 4 is connected to the fourth link pattern LINK4 through the seventh contact hole CONT7 and the fourth data pad 4 is connected to the fourth link 4 via the eighth contact hole CONT8. Pattern (LINK4). Therefore, the data voltage output from the fourth source channel OUT4 is connected to the fourth data line S4.

The pad portions according to the first and second embodiments are formed in the same process until the passivation layer (PAS) is formed. The pad portions 110 and 111 of the first and second embodiments are formed by a method of changing only the process of aligning the mask in order to selectively etch the passivation layer PAS. That is, since the pad portions 110 and 111 of the first and second embodiments have the same process of forming the first to sixth link patterns LINK1, LINK2, LINK3, LINK4, LINK5, and LINK6, It is advantageous to apply it to all of RGB display panels.

It will be apparent to those skilled in the art that various modifications and variations can be made in the present invention without departing from the spirit or scope of the invention. Therefore, the technical scope of the present invention should not be limited to the contents described in the detailed description of the specification, but should be defined by the claims.

100: display panel 102: data driver
104: Gate driver 20: Timing controller
21: EEPROM POL (S1) to POL (S4): Polarity control signal

Claims (9)

A display panel that receives a data voltage through the first to fourth data lines;
A data driver for outputting the data voltage to the first to fourth source channels; And
And a pad portion connecting the display panel and the data driver,
The pad portion
First to fourth source pads connected to the first to fourth source channels, respectively;
First to fourth data pads connected to the first to fourth data lines, respectively;
A first link pattern connecting the first source pad and the first data pad;
A second link pattern overlapping a part of the second source pad and the second data pad;
A third link pattern overlapping with the third source terminal and a part of the third data pad;
A fourth link pattern connecting the fourth source pad and the fourth data pad;
A fifth link pattern overlapping a part of the second source pad and the third data pad; And
And a sixth link pattern overlapping a part of the third source pad and the second data pad.
The method according to claim 1,
The display panel
First and second subpixels connected to the first data line in the odd-numbered line;
Third and fourth subpixels connected to the second data line in the odd-numbered line;
A second gate line coupled to the first sub-pixel;
A first gate line coupled to the second sub-pixel;
A fourth gate line coupled to the third sub-pixel; And
And a third gate line connected to the fourth sub-pixel.
The method according to claim 1,
The first to fourth source pads are located on a substrate,
The first to fourth data pads are located on the insulating film covering the first to fourth source pads,
And a passivation layer covering the first to fourth data pads.
The method of claim 3,
The second source pad and the second data pad are connected to the second link pattern through a contact hole,
And the third source pad and the third data pad are connected to the third link pattern through a contact hole.
5. The method of claim 4,
Wherein the display panel comprises RGBW type subpixels,
The data driver
First and second P buffers for outputting a positive polarity data voltage; And
And a first and a second N buffer outputting a negative polarity data voltage,
The first P buffer outputs first data provided to the first data line through the first source channel and third data supplied to the third data line through the third source channel, and,
The second P buffer outputs a positive voltage of the second data supplied to the second data line through the second source channel and the fourth data supplied to the fourth data line through the fourth source channel,
The first N buffer outputs a negative data voltage of the first data and the third data,
And the second N buffer outputs a negative data voltage of the second data and the fourth data.
5. The method of claim 4,
Wherein the display panel includes subpixels of the RGB system,
The data driver
First and second P buffers for outputting a positive polarity data voltage; And
And a first and a second N buffer outputting a negative polarity data voltage,
The first P buffer outputs first data to be supplied to the first data line through the first source channel and second data to be supplied to the second data line through the second source channel and,
The first N buffer outputs a negative data voltage of the first data and the second data,
The second P buffer outputs a third voltage supplied to the third data line through the third source channel and a positive voltage of the fourth data supplied to the fourth data line through the fourth source channel,
And the second N buffer outputs a negative data voltage of the third data and the fourth data.
The method of claim 3,
The second source pad and the third data pad are connected to the fifth link pattern through a contact hole,
And the third source pad and the second data pad are connected to the sixth link pattern through a contact hole.
8. The method of claim 7,
Wherein the display panel comprises RGB type subpixels,
The data driver
First and second P buffers for outputting a positive polarity data voltage; And
And a first and a second N buffer outputting a negative polarity data voltage,
The first P buffer outputs first data provided to the first data line through the first source channel and third data supplied to the third data line through the third source channel, and,
The second P buffer outputs a positive voltage of the second data supplied to the second data line through the second source channel and the fourth data supplied to the fourth data line through the fourth source channel,
The first N buffer outputs a negative data voltage of the first data and the third data,
And the second N buffer outputs a negative data voltage of the second data and the fourth data.
8. The method of claim 7,
Wherein the display panel includes sub-pixels of the RGBW scheme,
The data driver
First and second P buffers for outputting a positive polarity data voltage; And
And a first and a second N buffer outputting a negative polarity data voltage,
The first P buffer outputs first data to be supplied to the first data line through the first source channel and second data to be supplied to the second data line through the second source channel and,
The first N buffer outputs a negative data voltage of the first data and the second data,
The second P buffer outputs a third voltage supplied to the third data line through the third source channel and a positive voltage of the fourth data supplied to the fourth data line through the fourth source channel,
And the second N buffer outputs a negative data voltage of the third data and the fourth data.

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