KR20170076949A - Gate Driving Circuit for Display Device and Display Device having the same - Google Patents

Abstract

The present invention includes a mode selection pin capable of selecting an odd driving mode in which only the odd gate line is controlled by the gate driving circuit (G-IC) and an excellent driving mode in which only the even gate line is controlled, It is possible to reduce the number of control signals and the wiring therefor and to use them as they are without needing to change the timing controller or to implement additional functions and to prevent the gate block dim phenomenon which is a phenomenon of luminance unevenness due to the asymmetric structure .

Description

TECHNICAL FIELD [0001] The present invention relates to a gate driving circuit for a display device and a display device including the same,

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a gate driving circuit and a display device including the same, and more particularly, to a gate driving circuit and a display device including the same, And a display device including a driving circuit.

2. Description of the Related Art [0002] As an information-oriented society develops, there have been various demands for a display device for displaying images. Recently, a liquid crystal display (LCD), a plasma display panel (PDP) Various display devices such as an OLED (Organic Light Emitting Diode Display Device) are being utilized.

Among them, a liquid crystal display (LCD) displays an image by adjusting the light transmittance of liquid crystal using an electric field. To this end, a liquid crystal display device includes a liquid crystal display panel in which liquid crystal cells are arranged in a matrix form, and a driving circuit for driving the liquid crystal display panel.

The pixel array of the liquid crystal display panel includes a plurality of gate lines GL and data lines DL intersecting each other and a thin film transistor for driving the liquid crystal cells Clc at intersections of the gate lines GL and the data lines GL. (Hereinafter referred to as "TFT") is formed. A storage capacitor Cst for holding the voltage of the liquid crystal cell Clc is formed in the liquid crystal display panel. The liquid crystal cell Clc includes a pixel electrode, a common electrode, and a liquid crystal layer. An electric field is applied to the liquid crystal layer of the liquid crystal cells Clc by the data voltage applied to the pixel electrode and the common voltage Vcom applied to the common electrode. And the amount of light passing through the liquid crystal layer is controlled by this electric field, thereby realizing an image.

The driving circuit includes a gate driving circuit (G-IC) for sequentially supplying a gate output signal to gate lines, a data driving circuit (D-IC) for supplying a video signal (i.e., a data voltage) . The data driving circuit drives the data lines to supply the data voltages to the liquid crystal cells Clc. The gate driving circuit sequentially drives the gate lines to select the liquid crystal cells Clc of the display panel to which the data voltage is to be supplied, one horizontal line at a time.

The gate driving circuit sequentially generates a gate output signal Vout_i for providing to each gate line and supplies the gate output signal Vout_i to each gate line. The gate signal of the first level is sequentially generated one frame at a time, Line.

In general, the gate drive circuit (G-IC) is formed only on one side of the display panel so as to drive the entire N gate lines. However, since gate line wiring for connecting the gate drive circuit and each gate line, The bezel of the display panel of the display panel is increased.

In order to overcome such a problem, a two-gate driving circuit system is used in which two gate driving circuits are arranged on both sides of the display panel, and each gate driving circuit controls a part (half) of the gate lines N .

However, in the conventional two-gate driving circuit schemes, the number of gate control signal lines connecting the respective gate driving circuits from the timing controller (T-con) of the display panel increases, There is a problem that the number of control signals increases.

In view of the above, it is an object of the present invention to provide a gate driving circuit and a display device including the same, which can simplify the gate control signal wiring structure and the number of gate control signals using two gate driving circuits.

Another object of the present invention is to provide a gate drive circuit G (hereinafter, referred to as " G ") drive circuit including a mode select pin capable of selecting an odd drive mode for controlling only an odd gate line and an excellent gate drive mode for controlling only an even gate line -IC) chip, it is possible to easily operate a two-gate driving circuit system without changing the structure of the timing controller, and a display device including the same.

It is still another object of the present invention to provide a display device, in which a gate drive circuit (G-IC) including a mode selection pin is disposed on each side of a display panel to form odd gate line groups and even gate line groups The display panel can be operated only by the four gate control signals and the four gate control signal lines, thereby providing a display device of a simple structure.

 According to an aspect of the present invention, there is provided a display device including a display panel including a plurality of data lines, a total of N gate lines and a plurality of pixels, (Odd) gate line of the N gate lines, wherein the odd gate drive circuit includes an odd / even mode select pin and a odd / even mode select pin, Gate driver circuit and one or two gate-start pulses GSP1 and GSP2, one horizontal period (1H) gate driver circuit and an odd gate driver circuit connected to the even (odd) gate lines among the N gate lines, Common gate shift clocks (common GSC) and common gate output enable (common GOE) signals having the odd gate drive circuit and the even gate It provides a display device including a timing controller provided in the same circuit.

According to another embodiment of the present invention, there is provided a gate drive circuit which is mounted on a display panel for a display device in which N gate lines are arranged and operates in accordance with a control signal from a timing controller, When the mode selection signal applied to the odd / even mode select pin is an odd select signal, only the odd gate output signal of the gate output signal generated by the gate control signal received from the timing controller is transferred to the odd gate line When the mode selection signal applied to the odd / even mode select pin is an even select signal, only the outgoing gate output signal of the gate output signal generated by the gate control signal received from the timing controller is output to the outgoing gate line A gate drive circuit for a display device is provided.

According to the embodiment of the present invention to be described below, the structure of the display panel can be simplified by minimizing the gate control signal wiring structure and the number of the gate control signals using the two gate driving circuits.

In addition, a mode selection pin capable of selecting the odd driving mode in which only the odd gate line is controlled and the excellent driving mode in which only the even gate line is controlled is provided in the gate driver circuit (G-IC) disposed on both sides of the display panel It is possible to operate the display panel with only three or four gate control signals and signal wiring for the three or four gate control signals without changing the structure of the timing controller.

1 is a functional block diagram of a liquid crystal display device of the entire driving type to which the present invention can be applied.
2 shows a display panel structure of a first scheme using a two-gate drive circuit, compared with the present invention, and Fig. 3 shows a timing diagram of a control signal structure and a gate control signal in the first scheme.
Fig. 4 shows a display panel structure of a second scheme using a two-gate drive circuit, compared with the present invention, and Fig. 5 shows a timing diagram of a control signal configuration and a gate control signal in the second scheme.
6 shows a structure of a display device according to an embodiment of the present invention.
FIG. 7 shows a chip structure of a gate drive circuit which can be used in an embodiment of the present invention, and shows a structure including a mode select pin.
8 shows a gate control signal configuration and a signal flow of a display panel according to an embodiment of the present invention.
9 is a timing chart of a gate control signal supplied to the odd gate driving circuit (G-IC_odd) and the excellent gate driving circuit (G-IC_even) according to the embodiment of the present invention and a gate output signal outputted from each gate driving circuit to be.

Hereinafter, some embodiments of the present invention will be described in detail with reference to exemplary drawings. In the drawings, like reference numerals are used to denote like elements throughout the drawings, even if they are shown on different drawings. In the following description of the present invention, a detailed description of known functions and configurations incorporated herein will be omitted when it may make the subject matter of the present invention rather unclear.

In describing the components of the present invention, terms such as first, second, A, B, (a), and (b) may be used. These terms are intended to distinguish the components from other components, and the terms do not limit the nature, order, order, or number of the components. When a component is described as being "connected", "coupled", or "connected" to another component, the component may be directly connected or connected to the other component, Quot; intervening "or that each component may be" connected, "" coupled, "or " connected" through other components.

1 is a functional block diagram of a liquid crystal display device of the entire driving type to which the present invention can be applied.

1, a typical liquid crystal display device includes a display panel 10 including a display area 16 (Active Area; AA) in which a plurality of pixels P are formed, And a system board 20 that is a printed circuit board (PCB) including a driving circuit for driving the display device.

The display panel 10 typically includes an array substrate as a lower substrate on which a plurality of gate lines, a date line, and a plurality of thin film transistors are formed, a color filter substrate as a top substrate on which a color filter and a black matrix (BM) And the like.

The display panel 10 is formed with a number of pixels defined as intersecting regions of the gate line GL and the data line DL. That is, the data lines D1 to Dm and the gate lines G1 to Gn are intersected with each other on the lower array substrate, and m × n (m, n is a positive integer) liquid crystal cells Clc ) Are formed in a matrix form.

Each of the liquid crystal cells Clc includes a TFT, a pixel electrode 1 connected to the TFT, and a storage capacitor Cst. The liquid crystal cell Clc is driven by the voltage difference between the pixel electrode 1 for charging the data voltage through the TFT and the common electrode 2 to which the common voltage Vcom is applied and adjusts the amount of light incident thereon, (DATA_RGB).

On the other hand, on the upper glass substrate of the display panel 10, a black matrix, a color filter, and a common electrode are formed. The common electrode 2 is formed on the upper glass substrate in the vertical field driving mode such as the TN mode and the VA mode and is formed on the lower glass substrate together with the pixel electrode 1 in the horizontal electric field driving method such as the IPS mode and the FFS mode .

Meanwhile, the gate drive circuit 13 for providing the gate output signal Vout to the gate line is connected to the display panel through a TFT array process according to a gate-in-panel (GIP) May be formed directly on the lower substrate, may be formed as a separate chip, and may be connected to the display panel by a bonding method or the like.

That is, the gate drive circuit 13 is formed in the non-display area NAA outside the display area 16 (AA) of the display panel 10 and has a structure symmetrically formed on both sides of the panel But is not limited thereto.

A plurality of GIP blocks or GIP circuit blocks may be included in the gate driving circuit 13. Each GIP block may be connected to each gate line to generate and provide a gate output signal Vouti to the corresponding gate line .

In FIG. 1, a gate drive circuit 13 is formed on only one side (left side) of the display panel to provide a gate output signal to N gate lines. In FIGS. 2 and 3, Is formed.

The system board 20 may be connected to the display panel 10 through a flexible PCB (FPCB) 17 or a tape carrier package (TCP) 11, a data driving circuit 12, and the like.

The timing controller 11 may be referred to as T-Con. The timing controller 11 generates a data control signal for controlling the operation timing of the data driving circuit 12 using external timing signals Vsync, Hsync, DE, and DCLK And a gate control signal GDC for controlling the operation timings of the gate drive circuit 13 and providing them to the respective drive circuits.

The data control signal SDC supplied from the timing controller 11 to the data driving circuit 12 includes a source start signal (Source, Start Pulse, SSP), a source sampling clock (SSC) (SOE), a polarity control signal (POL), and the like.

The gate control signal GDC supplied from the timing controller 11 to the gate drive circuit 13 is supplied to the gate driver circuit 13 through a gate start pulse GSP, a gate shift clock GSC, A gate output enable (GOE), a polarity control signal (POL), and the like.

That is, when the timing controller 11 provides the GSP for starting the scanning of the gate line to the gate driving circuit 13, the scanning of the gate line starts, and the GSC and the GOE having one horizontal period (H) The gate output signal Vout_i corresponding to each gate line is generated and provided as a corresponding gate line in each horizontal period.

To this end, a total of N gate link wirings are formed in the non-display area on the left side of the display panel of Fig. 1, and each data link wiring functions to connect each gate line to the gate drive circuit 13 .

Here, the horizontal period or the horizontal period period represented by " H " can be defined as a reciprocal of a value obtained by multiplying the frame frequency by the number of gate lines. For example, if the display panel has a resolution of 1920 * 1080, the horizontal interval (H) period becomes 1 / (60Hz * 1080) 15.4 mu s.

The data driving circuit 12 can be expressed as a D-IC and includes a plurality of source drive ICs. Each of the source drive ICs samples and latches the digital video data (DATA_RGB) input from the timing controller 11 in response to a data control signal SDC from the timing controller 11 and converts the data into data of a parallel data system, And generates and supplies a data output signal to the data lines D1 to Dm.

1, in a system in which one gate driving circuit is disposed only on one side of the display panel to drive a total of N gate lines, gate line wiring for connecting the gate driving circuit and each gate line is not displayed on one side of the display panel Area, there is a problem that the bezel of the display panel of the display panel is increased.

In order to overcome such a problem, a two-gate driving circuit system is used in which two gate driving circuits are arranged on both sides of the display panel, and each gate driving circuit controls a part (half) of the gate lines N .

Figs. 2 to 5 show an example of a display panel including such a two-gate driving circuit. For convenience, Figs. 2 and 3 are shown in the first scheme and Figs. 4 and 5 are schematically shown.

Fig. 2 shows a display panel structure of a first scheme using a two-gate driving circuit, compared with the present invention, and Fig. 3 shows a timing diagram of a control signal configuration and a gate control signal.

2 and 3, a first gate driving circuit (G-IC # 1) 230 is disposed at the lower left end of the display panel and a total of N / 2 gates (Odd number) gate lines (GL # 1, 3, 5 ... (N-1)) are connected through a link wiring.

Further, the second gate driving circuit (G-IC # 2; 230 ') is arranged at the lower right end of the display panel and the even (even numbered) gate wiring is connected to the second gate driving circuit 230' Gate lines (GL # 2, 3, 6, ..., N) are connected.

As shown in FIG. 3 (a), in the first scheme, the timing controller 240 provides GSP1, GSC1, GOE1, etc. as gate control signals for controlling the first gate driving circuit 230.

The first gate driving circuit 230 receiving this gate control signal generates odd (odd) gate lines GL # 1, ..., (N-1) ), And outputs the gate output signals Vout1, Vout3, ..., Vout (N-1) sequentially to the GST carry signal Vout (N-1) To GSP2 to the timing controller 240. [

Then, the timing controller 240 generates GSP3, GSC2, and GOE2 as gate control signals for starting the operation of the second gate driving circuit 230 'after receiving the GSP carry signal GSP2, To the driving circuit 230 '.

The second gate driving circuit 230 'outputs the outgassing gate output signals Vout2, Vout4, ..., VoutN in the same manner as described above. After outputting the last outgoing gate output signal VoutN, the GSP carry signal To the timing controller 240, thereby completing one frame scanning.

3B, in the first scheme, among the gate control signals supplied to the first gate driving circuit and the second gate driving circuit, GSC1 / 2 and GOE1 / 2 are two horizontal periods ( 2H).

In this way, in the first scheme, the timing controller generates separate gate control signal waveforms GSC and GOE for the first gate driving circuit and the second gate driving circuit instead of the basic signal waveform generated in units of one horizontal period (1H) .

Therefore, if the display panel does not have a timing controller, or if it is not possible to add a function for generating the gate control signal to the timing controller by changing the gate control signal, it is difficult to apply the first method.

Also, in the display panel itself, there is a timing controller for a set device in a set device (TV, monitor, etc.) which is an electronic device in which the display panel is mounted even if there is no timing controller. In this case, It is difficult to apply the first scheme because the set timing controller is designed to implement only the basic functions for the common use.

In addition to the drawbacks in the design of the timing controller, in the first method, eight gate control signal lines for transferring gate control signals between the timing controller and the 1/2 gate driving circuit must be formed in total, There is a drawback that the size increases.

Thus, in the two-gate driving circuit structure of the first scheme as shown in Figs. 2 and 3, the number of gate control signals is eight and the structure of the timing controller needs to be changed accordingly. There is a drawback that it is difficult.

As an alternative to overcome the disadvantage of the first scheme, a 2-gate driver circuit structure of the second scheme as shown in Figs. 4 and 5 can be proposed.

Fig. 4 shows a display panel structure of a second scheme using a two-gate drive circuit, compared with the present invention, and Fig. 5 shows a timing diagram of a control signal configuration and a gate control signal in the second scheme.

4 and 5, a first gate driving circuit (G-IC # 1) 430 is disposed at the lower left end of the display panel and a total of N / 2 gates N / 2 gate lines (GL # 1, 2, 3, ..., N / 2) are connected from the first one through the link wiring.

The second gate driving circuit (G-IC # 2; 430 ') is disposed at the lower right end of the display panel and the N / 2 gate link wiring is connected to the second gate driving circuit 430' Two gate lines GL # (N / 2 + 1), (N / 2 + 2), ..., N are connected.

5 (a), the timing controller 440 in this second scheme has GSP1 and one horizontal period 1H as a gate control signal for controlling the first gate driving circuit 430 GSC, and GOE.

The first gate driving circuit 430 receiving this gate control signal generates N / 2 gate lines GL # 1, 2, 3, ..., N (N) in the first half, using the signal timing shown in FIG. Vout (N / 2)) and outputs the last gate output signal (Vout (N / 2)) of the first half to the GSP carry signal (Vout1, And transmits the generated signal GSP2 to the second gate driving circuit 430 '.

Since the second gate driving circuit 430 'receives the same GSC and GOE as those received by the first gate driving circuit 430 from the timing controller 440, the second gate driving circuit 430' receives GSP2 from the first gate driving circuit 430 The gate output signal Vout (N / 2) is sequentially supplied to the N / 2 gate lines GL # (N / 2 + 1), And outputs a GSP2 carry signal to the timing controller 430 after outputting the last gate output signal VoutN of the second half , And one frame scanning is completed.

In this second scheme, as shown in FIG. 5 (b), among the gate control signals supplied to the first gate driving circuit and the second gate driving circuit, the GSC / GOE has a basic control signal waveform And the same gate control signal is used for the 1/2 gate driving circuit.

Therefore, in the second scheme, four signal signals of GSP1, GSp2, GSC, and GOE are sufficient for the gate control signal, and the basic control signal waveform can be used as it is, so that the disadvantage of the first scheme can be solved to some extent.

However, in the second method, the gate link wiring to the last gate line GL # (N / 2) served by the first gate driving circuit 430 and the gate line wiring to the first gate line (N / 2) and GL (N / 2) due to the fact that gate line wiring to GL # (N / 2 + 1) does not achieve a complete symmetry in line design or process, # (N / 2 + 1) may cause a luminance non-uniformity phenomenon such as a band line.

This display failure can be expressed by a gate block dim phenomenon (Gate Block Dim).

In the second method, the gate output signal Vout (N / 2) applied to the last gate line GL # (N / 2) served by the first gate driving circuit 430 goes from left to right, The output signal waveform of the left starting point can be changed while reaching the right end point due to the transfer characteristic.

Conversely, the gate output signal Vout (N / 2 + 1) applied to the first gate line GL # (N / 2 + 1) served by the second gate driving circuit 430 'progresses from right to left, A signal waveform change similar to the above occurs during transmission.

As a result, in the case of adjacent pixels formed with the same data line between GL # (N / 2) and GL # (N / 2 + 1), the applied gate output signal waveforms are different, .

As described above, in the second system, there is a disadvantage that display failure occurs due to uneven brightness between the control region of the first gate drive circuit 430 and the control region of the second gate drive circuit 430 '.

SUMMARY OF THE INVENTION The present invention has been made to solve the drawbacks of the first mode and the second mode, and it is an object of the present invention to provide two gate drive circuits including a mode select pin operable in one of an odd driving mode and an even driving mode And the odd / even mode selection signal is applied to the mode selection pin. In the timing controller, one or two gate start pulses (GSP1, GSP2) and a common gate shift clock having one horizontal period The gate control signal GSC and the common gate output enable (GOE) signal are transmitted to the both gate driving circuits to operate. Thus, the gate control signal can be reduced to simplify the gate control signal wiring, Gate driver circuit structure which does not cause defects is proposed.

6 shows an overall structure of a display device according to an embodiment of the present invention.

The display device according to an embodiment of the present invention mainly includes a display panel 610, gate drive circuits 630 and 630 'including an odd / even mode select pin, a timing controller 640 for generating and outputting a gate control signal ).

The display panel 610 includes a plurality of data lines DL and a total of N gate lines GL and a display region including a plurality of pixels defined as intersecting regions of the data lines and the gate lines A / A), and a non-display area (N / A) formed around the display area but not displaying an image.

Gate driver circuits 630 and 630 'are disposed on both sides of one side (lower side) of the non-display area N / A of the display panel 610, and one or more data driving circuits D- IC 620 are disposed.

One of the two gate driving circuits disposed on both sides includes a radix gate driving circuit (not shown) including a radix / odd mode selection pin and operating in a radial mode according to an odd mode selection signal applied to the radix / G-IC_odd), and the other is an excellent gate driving circuit (G-IC_even) which includes an odd / even mode select pin and operates in an excellent operation mode according to an excellent mode selection signal applied to the odd / )to be.

6, the gate driver circuit disposed on the left side is referred to as an odd gate drive circuit (G-IC_odd) 630 and the gate driver circuit disposed on the right side is described as an excellent gate drive circuit (G-IC_even) 630 ' The location and function may be interchanged.

(Odd) gate lines among the N gate lines, and N / 2 gate link lines 612 are connected to the left non-display region of the display panel Respectively.

In addition, the outermost gate driver circuit (G-IC_even) 630 'is connected to an even (even) gate line among the N gate lines, and N / 2 gate link lines 612 are connected to the right And is formed in the display area.

Meanwhile, the timing controller 640 according to the present embodiment generates a gate control signal, transfers it to the odd gate driving circuit (G-IC_odd) 630 and the superior gate driving circuit (G-IC_even) 630 ' And provides it to the data driving circuit (D-IC) 620.

At this time, the gate control signal provided by the timing controller 640 to the odd gate driving circuit (G-IC_odd) 630 and the extra gate driving circuit (G_IC_even) 630 'is one or two gate start pulses GSP1 (GSP2), a common gate shift clock (common GSC) and a common gate output enable (common GOE) signal having one horizontal period (1H).

That is, the gate control signals GSP, GSC, and GOE used in the present embodiment are basic signal waveforms generated by a timing controller of a general structure, and it is necessary to change gate control signals as in the first method shown in FIG. 2 and FIG. There is no.

More specifically, GSP1 is a signal pulse generated by the timing controller for starting scanning, and the common GSC and the common GOE are basic signal pulses having one horizontal period (1H).

Thus, the gate control signals GSP, GOE, and GSC used in the present embodiment are the same as the gate control signals used by the timing controller of the general display device described with reference to FIG. 1, so that the conventional general- It can be used as it is.

In addition to the gate control signal, the timing controller 640 generates a radix / superior mode selection signal for selecting the odd / even operation mode of the gate drive circuit at the time of the first drive of the display panel or the like, To a control pin (710 of FIG. 7). Of course, the odd / even mode selection signal according to the present embodiment does not need to be controlled by the timing controller. By inputting a high or low signal to the odd / even mode select pin 710 from the outside, Or an even gate drive circuit.

On the other hand, a first GSP wiring, a common GSC wiring, a common GOE wiring, a second GSP wiring and a mode selection wiring may be arranged on a display panel between the timing controller, the odd gate driving circuit and the excellent gate driving circuit.

8 shows a gate control signal configuration of a display panel, a signal flow and signal wiring necessary for the signal flow according to an embodiment of the present invention.

8, between the timing controller 640 and the odd gate driving circuit 630 and the outgassing gate driving circuit 630 ', a first GSP wiring for transmitting the GSP1 simultaneously applied to the two gate driving circuits, (Not shown).

Similarly, between the timing controller 640 and the odd gate driving circuit 630 and the superior gate driving circuit 630 ', a common GSC signal and a common GOE signal, which are simultaneously applied to the two gate driving circuits, A common GOE wiring 633 and a common GOE wiring 632 are formed.

Further, between the timing controller 640 and the odd gate driving circuit 630 and between the timing controller and the superior gate driving circuit 630 ', a mode selection wiring for transmitting the odd / even mode selection signal to the two gate driving circuits (635) may be further formed. Of course, the odd / even mode selection signal according to the present embodiment does not need to be controlled by the timing controller. By inputting a high or low signal to the odd / even mode select pin 710 from the outside, Or an even gate drive circuit. In this case, the mode selection wiring 635 may not be formed on the display panel as shown in Fig.

In addition, a second GSP wiring 634 for transmitting GPS2 used for inverting driving may be further formed between the odd gate driving circuit 630 and the superior gate driving circuit 630 '.

GSP2 may not be used in normal operation and may only be used in Inversion Driving, which first scans from the last gate line (GL # N).

The odd gate drive circuit 630 according to the present embodiment is configured to output only the odd gate output signals Vout1, Vout3, ..., Vout (N-1) of the gate output signals generated by the gate control signal to the odd gate lines GL 1, 3, 5, ..., (N-1), and the extraordinary gate drive circuit 630 'outputs the exceptional gate output signals Vout2, Vout4, VoutN) to the even-numbered gate lines (GL # 2, 4, 6, ..., N).

Alternatively, the odd gate drive circuit 630 recognizes only the odd-numbered pulses among the pulses of the common GSC and the common GOE signal among the gate control signals and outputs the odd gate output signals Vout1, Vout3, ..., Vout (N-1) (GL # 1, 3, 5, ..., (N-1)).

That is, the odd gate drive circuit 630 and the extraordinary gate drive circuit 630 'according to the present embodiment generate and output a gate output signal using the gate control signal received from the timing controller, It is possible to generate and output only a gate output signal for a line (odd or even), to generate all the gate output signals, but to skip the output signal of the gate line which is not responsible for itself, Quot; output "

This function can be implemented by a certain software or algorithm in the gate drive circuit 630, 630 'according to the present embodiment.

Meanwhile, in the case of the liquid crystal display panel, the display panel 610 used in the display device according to the embodiment of the present invention includes a plurality of gate lines, a data line and a pixel defined in the intersection area, An upper substrate having a color filter and / or a black matrix, and a liquid crystal material layer interposed between the upper substrate and the array substrate.

The term " display device " is used herein to refer to a display device such as a liquid crystal module (LCM) including a display panel and a driver for driving the display panel, as well as a notebook computer , A set of electronic devices or set devices such as a television, a computer monitor, a mobile electronic device such as a smart phone or an electronic pad, and the like.

That is, the display device in this specification is used to mean not only a conferring display device such as LCM but also a set device which is an application including the display device.

Although the display device according to various embodiments of the present invention has been described as an example of a display device including a liquid crystal display panel for the sake of convenience of explanation, the present invention is not limited thereto, and the field emission display device, the plasma display panel, The present invention can be applied to all kinds of display devices that operate by driving a plurality of gate lines, such as a light emitting display, an organic light emitting display, and an electrophoretic display.

As described above, according to the embodiment of the present invention, since the gate control signal generated by the timing controller 640 is the same as the general gate control signal, it is not necessary to change the structure of the timing controller and three or four gate control signals GSP1 , GSP2, common GSC, and common GOE), the signal structure is simple and the wiring design is easy.

4 and 5, the structure according to the present embodiment is a structure in which there is a possibility that unevenness in luminance due to the resistance difference of the gate link line or the right and left waveform changes of the gate output signal occurs as a complete left- There is no advantage.

Referring to FIG. 9, the driving operation of the display apparatus according to the embodiment of the present invention will now be described.

9 is a timing chart of a gate control signal supplied to the odd gate driving circuit (G-IC_odd) and the superior gate driving circuit (G-IC_even) according to the embodiment of the present invention and a gate output signal outputted from each gate driving circuit to be.

As shown in FIG. 9, in the embodiment of the present invention, a radar / superior mode selection signal is first applied to the mode selection pins of the left and right gate drive circuits at the time of the first driving of the display panel or the manufacturing time of the panel, One of the driver circuits is set as the odd gate drive circuit, and the other one thereof is set as the outermost gate drive circuit.

For example, if the odd / even mode select signal is Low, the odd mode operation mode is indicated. If the odd / even mode select signal is HIGH, the odd mode operation mode can be indicated.

Thus, a mode selection signal of LOW from the outside is generated and transmitted to the mode selection pin of the left odd gate drive circuit (G-IC-odd) 630, and the left gate drive circuit, Set to the operation mode.

That is, the gate driving circuit receiving the radix mode operation signal operates the internal algorithm to generate only the radix gate output signals Vout1, Vout3, ..., Vout (N-1) as described in FIG. 9 (a) Or outputs a signal.

At the same time, the timing controller 640 or another external device generates a mode selection signal of HIGH and transmits the mode selection signal to the mode selection pin of the right gate drive circuit 630 ', and the right gate drive circuit, By setting the mode to the excellent operation mode, it operates to generate or output only the good gate output signals Vout2, Vout4, ..., VoutN as described in FIG. 9 (b).

After the mode selection is completed, the timing controller 640 outputs the same gate control signal, GSP1 having one ON pulse, and one horizontal period (1H) as shown in the upper part of Figs. 9A and 9B, And a common GOE signal which is a gate shift clock having a pulse repeated in one horizontal period (1H) and outputs it to the left odd gate drive circuit (G-IC_odd) 630 And the right superior gate drive circuit (G-IC_even) 630 '.

That is, according to the present embodiment, the timing controller 640 generates the same gate control signal combination composed of three signals, GSP1, common GSC, and common GOE signal, and simultaneously transmits them to two gate driving circuits.

As shown in FIG. 9A, the radix gate drive circuit (G-IC_odd) 630 receiving the gate control signal GSP1, the common GSC, and the common GOE signal is similar to the conventional one- And generates all the gate output signals Vout1, Vout2, Vout3, ..., VoutN every one horizontal period (1H).

However, only the odd gate output signals Vout1, Vout3, ..., Vout (N-1) of the gate output signals generated using the internal algorithm are supplied to the odd gate lines GL # 1, 3, 5, ..., (N-1).

Of course, as described above, the algorithm implemented in the radix gate driving circuit (G-IC_odd) 630 does not generate all the gate output signals, and the odd-numbered pulses 1, Vout (N-1), and then outputs them to the odd-numbered gate lines GL # 1, ..., N-1 It is possible.

Similarly, as shown in FIG. 9B, the good gate drive circuit (G-IC_even) 630 'receiving the gate control signal GSP1, the common GSC, and the common GOE signal outputs Vout2, Vout4, ..., VoutN among the gate output signals generated using the internal algorithm after generating the gate output signals Vout1, Vout2, Vout3, # 2, 4, 6, ..., N).

Of course, as described above, the algorithm implemented in the outermost gate driving circuit (G-IC_even) 630 'does not generate all the gate output signals, and the pulse of the common GSC and common GOE signal among the gate control signals Only the pulse can be recognized and only the output signal of the excellent gate can be generated and output to the outgoing gate line.

The number of gate control signals is reduced in comparison with the first method or the second method shown in FIGS. 2 to 5 using the embodiment of the present invention. As shown in FIG. 8, the timing controller and the gate driver circuits The number and structure of the wirings to be formed on the display panel for the display panel are simplified, which is advantageous for the panel design and advantageous for the narrow bezel.

Since the GSP1, the common GSC, and the common GOE signal, which are the gate control signals, are the same as the signals generated and used by the timing controller in the general full-drive display device, it is necessary to change the general- It can be used as it is.

On the other hand, the present invention can include not only the entire display device described above, but also the gate drive circuit itself operating in the above-described manner.

FIG. 7 shows a chip structure of a gate drive circuit which can be used in an embodiment of the present invention, and shows a structure including a mode select pin.

The gate drive circuit 700 shown in FIG. 7 is a gate drive circuit which is mounted on a display panel for display devices in which N gate lines are arranged and operates in accordance with a control signal from a timing controller, And a pin 710.

When the mode selection signal applied from the timing controller or an external device is an odd number selection signal, only the odd numbered gate output signal of the gate output signal generated by the gate control signal received from the timing controller is input to the odd numbered gate line When the mode selection signal received from the timing controller or an external device is an even selection signal, the output circuit outputs only the outgoing gate output signal out of the generated gate output signal to the outgoing gate line.

In addition, the gate driving circuit 700 according to the present embodiment can select a normal mode operation which is operated to output a gate output signal generated by the gate control signal received from the timing controller to the corresponding gate line (720 in Fig. 7), which is a normal mode selection pin.

The gate drive circuit 700 according to the present embodiment includes the above-described nudity / excellent mode select pin 710 and the normal mode select pin 720 in addition to the various data input / output terminals or pins of the general gate drive circuit chip, As shown in FIG.

When the odd mode selection signal or the odd mode selection signal is applied to the gate drive circuit 700 according to the present embodiment through the odd / even mode select pin 710, the gate line Only the output signal of the gate line which does not take charge of itself is skipped, and only the output signal of the gate line which is responsible for itself is generated Software or algorithms that "output" the function are included.

When the normal mode selection signal is applied through the normal mode selection pin 720, the gate driving circuit 700 according to the present embodiment outputs all the gate output signals Vout1, Vout2, Vout3, ..., VoutN) to all the corresponding gate lines (GL # 1, 2, 3, ..., N).

As described above, since the gate driving circuit 700 according to the present embodiment can be selected and operated in the normal mode as described above, There is an advantage that it can be used in the structure as shown in FIG. 1 for controlling the gate line.

As described above, by using the embodiment of the present invention, it is possible to select the odd driving mode in which only the odd gate line is controlled by the gate driving circuit (G-IC) and the excellent driving mode in which only the even gate line is controlled The number of the gate control signals and the wiring therefor are reduced, which is advantageous for the panel design and has an advantageous effect on the narrow bezel.

Since the GSP1, the common GSC, and the common GOE signal used in the present embodiment are the same as the signals generated and used by the timing controller in the general full-drive type display apparatus, the conventional general- There is an advantage that it can be used as it is without needing to implement an additional function.

In addition, since the structure for driving the gate lines is perfectly symmetrical on the left and right sides of the display panel, the gate block dimming phenomenon, which is a phenomenon of luminance unevenness due to the resistance difference as in the left-right asymmetric structure And also has an effect of preventing a phenomenon (Gate Block Dim).

It will be apparent to those skilled in the art that various modifications and variations can be made in the present invention without departing from the spirit or scope of the inventions. , Separation, substitution, and alteration of the invention will be apparent to those skilled in the art. Therefore, the embodiments disclosed in the present invention are intended to illustrate rather than limit the scope of the present invention, and the scope of the technical idea of the present invention is not limited by these embodiments. The scope of protection of the present invention should be construed according to the following claims, and all technical ideas within the scope of equivalents should be construed as falling within the scope of the present invention.

600: Display panel 620: Data driver circuit (D-IC)
630: Odd gate drive circuit 630 ': Even gate drive circuit
640: timing controller (T-con) 700: gate drive circuit
710: Rider / Excellent mode selection pin 720: Normal mode selection pin

Claims (7)

A display panel including a plurality of data lines, a total of N gate lines and a plurality of pixels;
Wherein the odd gate driving circuit includes odd / even mode select pins and is connected to odd (odd) gate lines of the N gate lines, The odd gate driving circuit includes a odd gate driving circuit and an excellent gate driving circuit, which include odd / even mode select pins and are connected to even (odd) gate lines among the N gate lines.
Generates a gate control signal including one or two gate start pulses GSP1 and GSP2 and a common gate shift clock (common GSC) and common gate output enable (common GOE) signal having one horizontal period 1H To the odd gate driving circuit and the extraordinary gate driving circuit;
. The method according to claim 1,
The odd gate drive circuit is set by the odd mode select signal applied to the odd / even mode select pin, and only the odd gate output signal of the gate output signal generated by the gate control signal is output to the odd gate line, Wherein the gate driving circuit is set by an excellent mode selection signal applied to the odd / even mode select pin, and outputs only the outgoing gate output signal of the gate output signal generated by the gate control signal to the outgoing gate line. 3. The method of claim 2,
And a first GSP wiring, a common GSC wiring, a common GOE wiring and a second GSP wiring are arranged on a display panel between the timing controller, the odd gate driving circuit and the excellent gate driving circuit. The method of claim 3,
Wherein the odd gate driving circuit and the extraordinary gate driving circuit further include a normal mode select pin capable of selecting a normal mode operation to output all the gate output signals to corresponding gate lines. A gate drive circuit mounted on a display panel for a display in which N gate lines are arranged and operated in accordance with a control signal from a timing controller,
The mode selection signal applied to the odd / even mode select pin includes an odd / even mode select pin. When the mode select signal applied to the odd / even mode select pin is an odd select signal, the gate drive circuit includes a gate output signal When the mode selection signal applied to the odd / even mode select pin is a good select signal, only the output of the odd-numbered gate signal is output to the odd-numbered gate line, A gate drive circuit for a display device which outputs only a gate output signal to an even gate line. 6. The method of claim 5,
The gate control signal provided from the timing controller is generated by one or two gate start pulses GSP1 and GSP2, a common gate shift clock (common GSC) having one horizontal period 1H and a common gate output enable ) Signal for a display device. The method according to claim 6,
And a normal mode selection pin operable to output a gate output signal generated by the gate control signal received from the timing controller to a corresponding gate line, Gate drive circuit.

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