KR102353274B1 - Video Wall device And Display Device - Google Patents

Abstract

The present invention relates to a video wall device that implements a large screen by arranging a plurality of display devices in a tile form, and a display device constituting the video wall device.
A video wall device according to an embodiment of the present invention displays an image by connecting a plurality of display devices, and includes a first display device disposed at an upper side of a screen, a second display device disposed below the first display device; a main controller and a signal delay unit, wherein the main controller supplies image data, a timing signal and a control signal to each of the first and second display devices, and the signal delay unit is disposed between the main controller and the first and second display devices, , The control signal and image data input to each of the first and second display devices are selectively delayed for a predetermined time and output, and the image is displayed at the lower end of the first display device and the image is displayed at the upper end of the second display device. The display timing coincides with the output timing of the gate driving signal supplied to the gate line disposed at the lowermost end adjacent to the second display device in the first display device, and the second display device is disposed at the uppermost end adjacent to the first display device By matching the output timing of the gate driving signal supplied to the corresponding gate line, it is possible to prevent image shaking at the interface between the first and second display devices.

Description

Video Wall Device And Display Device

The present invention relates to a video wall device that implements a large screen by arranging a plurality of display devices in a tile form, and a display device constituting the video wall device.

Until now, display devices such as a liquid crystal display device, a plasma display panel, and an organic light emitting display device have been developed. Such a display device includes a display panel for displaying an image and a driving circuit for driving the display panel.

1 is a diagram schematically showing a video wall device according to the prior art. FIG. 2 is a diagram illustrating a problem in which motion judder occurs in images displayed in display devices arranged vertically adjacent to each other.

1 and 2, recently, a video wall device (1, video wall device) that implements a large screen by arranging a plurality of display devices (10, 20, 30, 40) in the form of a tile has been developed and have. In FIG. 1 , a video wall device 1 is configured by arranging four display devices in a 2x2 form as an example.

Although the screen size of display devices has continuously increased thanks to technological advances, there is a limit to realizing extra-large screens such as electronic boards and billboards. The video wall device 1 can adjust the screen size and shape by connecting and disposing several display devices.

FIG. 2 is a diagram illustrating a problem in that an image motion judder occurs due to a time difference between images displayed on display devices arranged vertically adjacent to each other. 2 shows a first display device 10 disposed on an upper side and a second display device 20 disposed on a lower side among display devices constituting the video wall device.

Referring to FIG. 2 , the first and second display devices 10 and 20 sequentially output gate driving signals from the top of the liquid crystal panel, and output the gate driving signals to the bottom of the liquid crystal panel. That is, the gate driving signal is sequentially supplied from the first gate line to the last gate line disposed on the liquid crystal panel, and images are sequentially displayed from the upper end to the lower end of the liquid crystal panel.

As described above, when an image is sequentially displayed from the top to the bottom of the liquid crystal panel, there is no problem in displaying the image in one display device. However, when a video wall device 1 is configured by connecting a plurality of display devices, an image is smoothly displayed at the boundary between the first display device 10 disposed on the upper side and the second display device 20 disposed on the lower side. There is a problem in that it does not continue, and motion judder occurs.

Here, the lowermost portion of the first display device 10 displays an image at D+16.7 ms (the end point of one frame), and the uppermost portion of the second display device 20 displays D+0 ms at D+0ms (1). Since the image is displayed at the starting point of the frame), motion judder occurs due to the time difference between the images displayed on the first and second display devices 10 and 20 disposed adjacent to each other. .

In particular, when the image moves from left to right or from right to left, motion judder occurs at the boundary between the first display device 10 and the second display device 20 . have. Due to this, the display quality of the video wall device is deteriorated.

The inventors of the present application recognized the problems of the prior art described above and presented the following technical problems.

The present invention is to solve the problems of the prior art described above, and it is a technical task to improve the display quality of a video wall device.

SUMMARY OF THE INVENTION The present invention is to solve the problems of the prior art described above, and it is a technical task to adjust the timing at which an image is displayed in a first display device and a second display device disposed vertically adjacent to each other.

The present invention is to solve the problems of the prior art described above, and it is a technical task to ensure that there is no time difference between images displayed on a plurality of display devices arranged vertically adjacent to each other (so that the time difference becomes zero). do.

SUMMARY OF THE INVENTION The present invention is to solve the problems of the prior art described above, and it is a technical task to control an output timing of a gate driving signal and an output timing of a data voltage of each display device constituting a video wall device.

The problems to be solved according to the embodiment of the present invention are not limited to the problems mentioned above, and other problems not mentioned will be clearly understood by those skilled in the art from the following description.

In order to achieve the technical problem described above, a video wall device according to an embodiment of the present invention displays an image by connecting a plurality of display devices. The video wall device includes a first display device disposed above the screen, a second display device disposed below the first display device, a main controller, and a signal delay unit. The main controller supplies image data, a timing signal, and a control signal to each of the first and second display devices. The signal delay unit is disposed between the main controller and the first and second display devices, and selectively delays and outputs a control signal and image data input to each of the first and second display devices for a predetermined time. Here, the timing at which the image is displayed at the bottom of the first display device coincides with the timing at which the image is displayed at the top of the second display device, and is disposed at the lowermost end adjacent to the second display device in the first display device. The output timing of the gate driving signal supplied to the gate line coincides with the output timing of the gate driving signal supplied to the uppermost gate line disposed adjacent to the first display device in the second display device, so that the first and second Prevents image shaking at the interface of the display device.

In order to achieve the technical problem described above, a video wall device according to an embodiment of the present invention displays an image by connecting a plurality of display devices. The video wall device includes a first display device disposed above the screen, a second display device disposed below the first display device, a main controller, and a signal delay unit. The main controller supplies image data, a timing signal, and a control signal to each of the first and second display devices. The signal delay unit is disposed inside each of the first and second display apparatuses, and selectively delays a control signal and image data for a predetermined time in the first and second display apparatuses. In the video wall device including such a configuration, the timing at which the image is displayed at the lower end of the first display device coincides with the timing at which the image is displayed at the top of the second display device, and in the first display device, the second The output timing of the gate driving signal supplied to the lowermost gate line adjacent to the display device coincides with the output timing of the gate driving signal supplied to the uppermost gate line adjacent to the first display device in the second display device to prevent image shaking at the interface between the first and second display devices.

In addition, the signal delay unit of the video wall device of the present invention is configured to include a plurality of shift registers. The delay time of the control signal and the image data increases in proportion to the number of shifter registers through which the signal passes.

In addition, the signal delay unit of the video wall device of the present invention is composed of a flash memory. The output timing of the control signal and image data input to the signal delay unit is adjusted according to a preset delay selection signal.

In addition, in the video wall device of the present invention, the output timing of the gate driving signal supplied to the lowermost gate line of the first display device and the gate driving signal supplied to the uppermost gate line of the second display device Match the output timing of the signal.

In order to achieve the technical problem described above, a display device according to an embodiment of the present invention includes a liquid crystal panel in which a plurality of sub-pixels are disposed and a driving circuit unit. The driving circuit unit includes a signal delay unit, a timing controller, a gate driver, and a data driver. The signal delay unit delays the input control signal and image data for a predetermined time and outputs the delay. The timing controller controls the output of the gate driving signal according to the control signal input from the signal delay unit, and outputs image data. The gate driver outputs a gate driving signal to a plurality of gate lines disposed on the liquid crystal panel. The data driver converts the image data into a data voltage and supplies the data voltage to the plurality of sub-pixels according to the gate driving signal. A display device including these components may change a time point at which an image is displayed according to a signal delay in the signal delay unit.

In addition, the signal delay unit of the display device of the present invention is configured to include a plurality of shift registers. The delay time of the control signal and the image data increases in proportion to the number of shifter registers through which the signal passes.

In addition, the signal delay unit of the display device of the present invention is composed of a flash memory. The output timing of the control signal and image data input to the signal delay unit is adjusted according to a preset delay selection signal.

According to an embodiment of the present invention, the display quality of a video wall device may be improved.

In addition, according to the present invention, it is possible to adjust the timing at which an image is displayed on the first and second display devices arranged vertically adjacent to each other.

In addition, there is no time difference between the images displayed on the first display device and the second display device disposed vertically adjacent to each other (so that the time difference becomes zero), so that at the boundary between the first and second display devices, there is no difference in time. Avoid screen shake.

In addition, the present invention can control the output timing of the gate driving signal and the output timing of the data voltage of each of the display devices constituting the video wall device.

The effect of the present invention is not limited to the above-mentioned effects, and another effect not mentioned will be clearly understood by those skilled in the art from the following description.

Since the content of the invention described in the problem to be solved above, the means for solving the problem, and the effect do not specify the essential characteristics of the claim, the scope of the claim is not limited by the matters described in the content of the invention.

1 is a diagram schematically showing a video wall device according to the prior art.
FIG. 2 is a diagram illustrating a problem in that an image motion judder occurs due to a time difference between images displayed on display devices arranged vertically adjacent to each other.
3 is a diagram schematically illustrating a video wall apparatus according to an embodiment of the present invention.
4 is a diagram illustrating a display device according to an embodiment of the present invention.
5 is a diagram illustrating a signal delay unit according to an embodiment of the present invention.
6 is a diagram illustrating a video wall apparatus and a display apparatus according to another embodiment of the present invention, and is a diagram illustrating that a shift register is applied as a signal delay unit and disposed on the display apparatus.
7 is a diagram illustrating a video wall apparatus and a display apparatus according to another embodiment of the present invention, and is a diagram illustrating that a flash memory is applied as a signal delay unit and disposed on the display apparatus.
8 is a diagram illustrating a video wall apparatus and a display apparatus according to another embodiment of the present invention, and is a diagram illustrating that a signal delay unit is disposed inside a timing controller.
9 is a diagram illustrating an effect of improving motion judder because a time difference between images displayed on display devices arranged vertically adjacent to each other in a video wall device does not occur.

Advantages and features of the present invention, and a method for achieving them will become apparent with reference to the embodiments described below in detail in conjunction with the accompanying drawings. However, the present invention is not limited to the embodiments disclosed below, but will be implemented in a variety of different forms, and only these embodiments make the disclosure of the present invention complete, and those of ordinary skill in the art to which the present invention pertains. It is provided to fully inform the person of the scope of the invention, and the present invention is only defined by the scope of the claims.

The shapes, sizes, proportions, angles, numbers, etc. disclosed in the drawings for explaining the embodiments of the present invention are exemplary, and thus the present invention is not limited to the illustrated matters. Like reference numerals refer to like elements throughout. In addition, in describing the present invention, if it is determined that a detailed description of a related known technology may unnecessarily obscure the gist of the present invention, the detailed description thereof will be omitted. When 'including', 'having', 'consisting', etc. mentioned in this specification are used, other parts may be added unless 'only' is used. When a component is expressed in the singular, cases including the plural are included unless otherwise explicitly stated.

In interpreting the components, it is construed as including an error range even if there is no separate explicit description.

In the case of a description of the positional relationship, for example, when the positional relationship of two parts is described as 'on', 'on', 'on', 'beside', etc., 'right' Alternatively, one or more other parts may be positioned between two parts unless 'directly' is used.

In the case of a description of a temporal relationship, for example, 'immediately' or 'directly' when a temporal relationship is described with 'after', 'following', 'after', 'before', etc. It may include cases that are not continuous unless this is used.

Although the first, second, etc. are used to describe various elements, these elements are not limited by these terms. These terms are only used to distinguish one component from another. Accordingly, the first component mentioned below may be the second component within the spirit of the present invention.

Each feature of the various embodiments of the present invention may be partially or wholly combined or combined with each other, technically various interlocking and driving are possible, and each embodiment may be independently implemented with respect to each other or implemented together in a related relationship. may be

Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the drawings.

3 is a diagram schematically illustrating a video wall apparatus according to an embodiment of the present invention.

Referring to FIG. 3 , the video wall apparatus 1000 of the present invention includes a plurality of display apparatuses 100 to 400 , a main controller 500 , and a signal delay unit 600 . The video wall display apparatus 1000 is configured by arranging a plurality of display apparatuses 100 to 400 in the form of a 2X2 tile. In FIG. 3 , the video wall apparatus 1000 is configured by arranging four display apparatuses 100 to 400 in the form of a 2X2 tile, but the number and arrangement structure of the display apparatuses constituting one video wall apparatus 1000 . There are no restrictions on

Each of the plurality of display apparatuses 100 to 400 is individually driven based on a control signal and image data supplied from the main controller 500 , and each display apparatus 100 to 400 displays an image individually. An image displayed on each of the plurality of display apparatuses 100 to 400 becomes a part of the entire screen, and the image displayed on the plurality of display apparatuses 100 to 400 is combined to form the entire screen of the video wall apparatus 1000 . will become

To this end, the main controller 500 generates a control signal for individually driving each of the plurality of display apparatuses 100 to 400 , and supplies the generated control signal to the plurality of display apparatuses 100 to 400 .

In addition, the main controller 500 converts image data of the entire screen (hereinafter, referred to as full image data) into sub image data of each of the plurality of display apparatuses 100 to 400 , and the plurality of display apparatuses 100 to 400 . Sub-image data is supplied to each. That is, the first sub image data is supplied to the first display device 100 , the second sub image data is supplied to the second display device 200 , and the third sub image data is supplied to the third display device 300 . is supplied, and the fourth sub image data is supplied to the fourth display device 400 .

When the first sub-image data, the second sub-image data, the third sub-image data, and the fourth sub-image data are combined, the entire image data of the main controller 500 is obtained. Here, the entire image data may be input to the main controller 500 from the outside. As another example, the entire image data may be stored in a memory separately configured in the video wall device 1000 .

In the video wall apparatus 1000 , on the boundary surface between the first display apparatus 100 and the second display apparatus 200 arranged vertically adjacent to each other, image shaking may occur due to a time difference between the displayed images. In the present invention, in order to prevent such image shake, the control signal and image data output from the main controller 500 are supplied to each of the display devices 100 to 4000 through the signal delay unit 600 . The configuration and function of the signal delay unit 600 will be described in detail with reference to FIG. 5 .

4 is a diagram illustrating a display device according to an embodiment of the present invention. The first display apparatus 100 , the second display apparatus 200 , the third display apparatus 300 , and the fourth display apparatus 400 have the same configuration. Accordingly, FIG. 4 illustrates the first display apparatus 100 among the plurality of display apparatuses 100 to 400 constituting the video wall apparatus 1000 .

Referring to FIG. 4 , the display apparatus 100 according to an embodiment of the present invention includes a liquid crystal panel 110 , a gate driver 120 , a data driver 130 , a timing controller 140 , a power supply unit, and a backlight unit. . 4 , the power supply unit and the backlight unit are not shown. The gate driver 120 , the data driver 130 , and the timing controller 140 are the liquid crystal panel 110 in whole or in part in a Chip On Glass (COG) or Chip On Flexible Printed Circuit (COF) method. can be placed in

The liquid crystal panel 110 includes a TFT array substrate in which a plurality of sub-pixels are arranged in a matrix form, a TFT, a pixel electrode, a common electrode, and a storage capacitor (Cst) are arranged, and RGB color filters are arranged to correspond to each sub-pixel. A color filter array substrate and a liquid crystal layer interposed between the two substrates.

The plurality of subpixels is defined by a plurality of data lines and a plurality of gate lines crossing each other. A TFT and a storage capacitor Cst are disposed in each region where the data line and the gate line cross each other.

A pixel electrode is disposed in each subpixel of the TFT array substrate, and a common electrode is disposed to correspond to all subpixels or a plurality of subpixels. The pixel electrode and the common electrode are formed of a transparent conductive material such as indium tin oxide (ITO).

The timing controller 140 controls driving of the gate driver 120 and the data driver 130 . The timing controller 140 converts the sub image data DATA inputted using the timing signal TSS outputted from the main controller 500 and input via the signal delay unit 600 to RGB image data in units of frames. converted, and the RBG image data is supplied to the data driver 130 . In this case, the timing signal TSS includes a vertical synchronization signal V-sync, a horizontal synchronization signal H-sync, and a clock signal CLK.

Also, the timing controller 140 generates a gate control signal (GCS) for controlling the gate driver 120 using the timing signal TSS and supplies it to the gate driver 120 . The gate control signal GCS may include a gate start pulse (GSP), a gate shift clock (GSC), and a gate output enable (GOE).

Also, the timing controller 140 generates a data control signal (DCS) for controlling the data driver 130 by using the timing signal TSS and supplies it to the data driver 130 . The data control signal (DCS) is a source start pulse (SSP: Source Start Pulse), a source sampling clock (SSC: Source Sampling Clock), a source output enable (SOE: Source Output Enable) and a polarity control signal (POL: Polarity), etc. may include

The data driver 130 converts digital RGB image data supplied from the timing controller 140 into an analog image signal, that is, an analog data voltage. Then, based on the data control signal DCS from the timing controller 140 , the data voltage is supplied to the plurality of data lines when the TFTs of each subpixel are turned on according to the gate driving signal.

A data voltage is supplied to the subpixels connected to each gate line disposed on the liquid crystal panel 110 . That is, when the first gate driving signal is supplied to the first gate line, the data voltages of the subpixels connected to the first gate line are supplied to the plurality of data lines. Through this, the data voltage is supplied to the turned-on sub-pixels connected to the first gate line. Similarly, when the second gate driving signal is supplied to the second gate line, the data voltages of the subpixels connected to the second gate line are supplied to the plurality of data lines. Through this, the data voltage is supplied to the turned-on sub-pixels connected to the second gate line. As described above, from the first gate driving signal to the last gate driving signal are sequentially output, and all sub-pixels are sequentially turned on in accordance with each gate driving signal. A common voltage Vcom is supplied to the common electrode of each sub-pixel together with the data voltage supply to display an image. The common voltage may be generated by the data driver 130 and supplied to the common electrode, or the common voltage may be generated by the power supply and supplied to the common electrode.

In the main controller 500 shown in FIG. 3 , the control signal including the timing signal TSS and the sub image data DATA are output to the signal delay unit 600 , and the control signal passed through the signal delay unit 600 . and sub-image data DATA are supplied to the timing controller 140 .

Here, the control signal and sub-image data DATA are generated for each of the plurality of display apparatuses 100 to 400 , and a control signal is provided to each of the second to fourth display apparatuses 200 to 400 as well as the first display apparatus 100 . and sub image data DATA are supplied. The control signal and sub-image data DATA supplied to the second to fourth display devices 200 to 400 are also output from the main controller 500 and then pass through the signal delay unit 600 .

5 is a diagram illustrating a signal delay unit according to an embodiment of the present invention.

3 and 5 , the signal delay unit 600 according to an embodiment of the present invention is disposed between the main controller 500 and the first to fourth display devices 100 to 400 .

The signal delay unit 600 transmits a control signal from the timing controller 500 to an input terminal to which a control signal and sub-image data are input, a plurality of shift registers 610 , a multiplexer 620 , and an individual display device 100 to 400 . and an output terminal for outputting sub image data.

A plurality of shift registers 610 are disposed between the input terminal and the multiplexer 620, and each shift register 610 outputs an input signal after delaying it for a predetermined time.

Here, the signal (control signal and sub-image data) input to the signal delay unit 600 does not necessarily pass through the shift register 610 , and the control signal and sub-image data of the display device that do not require a signal delay are transferred to the shift register. It is output directly without passing through. On the other hand, the control signal and sub-image data of the display device requiring signal delay are output after passing through one or more shift registers. In this case, the delay time of the signal increases in proportion to the number of shift registers passing through it.

The delay time may be variously adjusted according to the size of the individual shift register 610 . For example, each shift register 610 delays the input signal for a time of 2 frames, 1 frame, 1/2 frame, 1/3 frame, 1/4 frame, 1/8 frame, or 1/16 frame. It can be printed later.

For example, when one shift register has a delay time corresponding to 1/4 frame, after a signal (control signal and sub-image data) input from the main controller 500 passes through one shift register 610 , When input to the timing controller of the display device, the control signal and sub-image data passing through the signal delay unit 600 are delayed by a time corresponding to 1/4 frame. Accordingly, compared to a signal that does not pass through the shift register 610 of the signal delay unit 600, the signal passing through one shift register 610 is delayed by a time corresponding to 1/4 frame and output.

In the same way, when the signal (control signal and sub-image data) input from the main controller 500 passes through the two shift registers 610 and is then input to the timing controller of the display device, it passes through the signal delay unit 600 . The control signal and sub-image data are delayed by a time corresponding to 1/2 frame. Accordingly, the signal passing through the two shift registers 610 compared to the signal not passing through the shift register 610 of the signal delay unit 600 is delayed by a time corresponding to 1/2 frame and output.

In the same way, when the signal (control signal and sub-image data) input from the main controller 500 passes through the three shift registers 610 , it corresponds to 3/4 frame compared to the signal that does not pass through the shift register 610 . The output is delayed by the amount of time. And, when the signal (control signal and sub-image data) input from the main controller 500 passes through the four shift registers 610 , it is delayed by a time corresponding to one frame compared to the signal that does not pass through the shift register 610 . and will be output.

As another example, when one shift register has a delay time corresponding to 1/2 frame, the signal (control signal and sub image data) input from the main controller 500 passes through one shift register 610 . Then, when input to the timing controller of the display device, the control signal and sub-image data passing through the signal delay unit 600 are delayed by a time corresponding to 1/2 frame. Accordingly, the signal passing through one shift register 610 compared to the signal not passing through the shift register 610 of the signal delay unit 600 is delayed by a time corresponding to 1/2 frame and then output.

In the same way, when the signal (control signal and sub-image data) input from the main controller 500 passes through the two shift registers 610 and is then input to the timing controller of the display device, it passes through the signal delay unit 600 . The control signal and sub-image data are delayed by a time corresponding to one frame. Accordingly, the signal passing through the two shift registers 610 compared to the signal not passing through the shift register 610 of the signal delay unit 600 is delayed by a time corresponding to one frame to be output.

The control signal and sub-image data directly input to the multiplexer 620 without going through the shift register 610 are transmitted to the first display apparatus 100, the second display apparatus 200, and the third display apparatus according to the output selection signal SEL. It is selectively output to the display device 300 or the fourth display device 400 .

In addition, the control signal and sub-image data input to the multiplexer 620 after passing through one or more shift registers 610 are transmitted to the first display apparatus 100 and the second display apparatus 200 according to the output selection signal SEL. ), is selectively output to the third display device 300 or the fourth display device 400 .

In FIG. 5 , the control signal and sub-image data of each of the display apparatuses 100 to 400 are illustrated as a low-voltage differential signaling (LVDS) method or a mini LVDS method. However, the present invention is not limited thereto, and not only LVDS and mini LVDS, but also eDP, EPI, or Vx1 (V by one) schemes may be used.

9 is a diagram illustrating an effect of improving motion judder because a time difference between images displayed on display devices disposed vertically adjacent to each other in a video wall device does not occur.

Referring to FIG. 9 , among a plurality of display devices constituting the video wall device 1000 , a first display device 100 disposed above (arranged in odd columns) and a second display device disposed below (arranged in even rows) An image displayed on the display device 200 is shown.

When the display apparatuses 100 to 400 of the present invention are disposed on the video wall apparatus 1000, the time difference between the images displayed on the plurality of display apparatuses arranged vertically adjacent to each other in order to prevent image shaking on the screen is reduced. (so that the time difference becomes zero).

Specifically, in order to prevent screen shake from occurring at the interface between the first display apparatus 100 and the second display apparatus 200 , an image is displayed in sub-pixels disposed in the lowermost row of the first display apparatus 100 . The timing at which an image is displayed in the sub-pixels disposed in the uppermost column of the second display apparatus 200 may coincide with the timing at which the image is displayed.

The control signal and sub-image data of the first display apparatus 100 are directly output from the signal delay unit 600 without going through the shift register 610 and are input to the first display apparatus 100 without a signal delay. Therefore, the image is displayed on the liquid crystal panel without delay.

The control signal and sub-image data of the second display apparatus 200 are inputted to the second display apparatus 200 after passing through one or more shift registers 610 in the signal delay unit 600 and delayed for a predetermined time. Accordingly, the image is displayed on the liquid crystal panel with a delay equal to the delay time of one shift register x the number of shift registers passed through.

Here, when an image is displayed at a 60Hz driving frequency (1 frame = 16.7ms), the time point at which the image is displayed in the subpixels arranged in the uppermost column of the liquid crystal panel of the first display apparatus 100 is D1+0ms, and , the time point at which an image is displayed in the sub-pixels arranged in the lowermost column of the liquid crystal panel is D1+16.7ms.

A signal to match the time point at which an image is displayed in the subpixels disposed in the lowermost column of the first display apparatus 100 and the time point at which the image is displayed in the subpixels disposed in the uppermost column of the second display device 200 . The delay unit 600 delays the control signal and sub-image data of the second display apparatus 200 for a period of time (16.7 ms) corresponding to one frame, and then outputs them. Through this, the time point at which an image is displayed in the subpixels arranged in the uppermost column of the liquid crystal panel of the second display device 200 becomes D2 (D1+17.6ms), and the subpixels arranged in the lowermost column of the liquid crystal panel The time at which the image is displayed in , becomes D2+16.7ms.

In the video wall device of the prior art, when an image moves from left to right, there is a problem in that motion judder occurs at the interface between the first and second display devices 100 and 200 adjacent up and down. .

On the other hand, in the video wall device 1000 of the present invention, an image is displayed in subpixels disposed at the bottom of the first display device 100 that are vertically adjacent to each other, and the video wall device 1000 is disposed at the top of the second display device 200 . The timing at which the image was displayed in the subpixels was matched. Through this, generation of motion judder at the boundary between the vertically adjacent display devices 100 and 200 is prevented.

In other words, the video wall device 1000 of the present invention includes a time point at which a gate driving signal is output and an image display time point, and a time point at which an image is displayed, which is supplied to a gate line disposed at the lower end of the first display device 100 adjacent vertically. The output timing of the gate driving signal supplied to the gate line disposed on the upper end of the display device 200 coincides with the timing of displaying the image. Through this, generation of motion judder at the boundary between the vertically adjacent display devices 100 and 200 is prevented.

In the above description, the expression "time point coincided" includes not only the case where the deviation between the two signals is mathematically zero, but also includes a minute time deviation including general signal delay occurring in the circuit configuration. Therefore, in the present invention, even if a minute time deviation occurs between the first signal and the second signal due to a signal delay that can be tolerated in a general electronic device, the input/output timing of the first signal and the second signal is regarded as coincident. can be considered

Hereinafter, a video wall apparatus and a display apparatus according to another embodiment of the present invention will be described with reference to FIGS. 7 to 9 .

7 is a diagram illustrating a video wall device and a display device according to another embodiment of the present invention, and is a view showing that a flash memory is applied as a signal delay unit and disposed on the display device. 8 is a diagram illustrating a video wall device and a display device according to still another embodiment of the present invention, wherein a signal delay unit is disposed inside a timing controller.

7 and 8 , a signal delay unit 700 is disposed in each of the plurality of display devices 100 to 400 constituting the video wall device 1000 . 7 and 8 illustrate the first display apparatus 100 among the plurality of display apparatuses 100 to 400 as an example.

As shown in FIG. 7 , the signal delay unit 700 may be disposed as a separate component in the display apparatus 100 . As another example, as shown in FIG. 8 , the signal delay unit 700 may be disposed inside the timing controller 140 . Here, a flash memory may be applied to the signal delay unit 700 , and a control signal and image data are stored in units of one frame and then output.

For example, the control signal and sub-image data input to the timing controller 140 are stored in the signal delay unit 700 . At this time, the delay selection signal SEL for controlling the output of the frame data (control signal and sub-image data) is input to the timing controller 140 . The timing controller 140 delays the frame data for a predetermined time according to the input delay selection signal SEL, and then loads the frame data from the signal delay unit 700 and outputs it. The output of the frame data may be delayed according to the delay selection signal SEL.

9 is a diagram illustrating an effect of improving motion judder because a time difference between images displayed on display devices disposed vertically adjacent to each other in a video wall device does not occur.

Referring to FIG. 9 , among a plurality of display devices constituting the video wall device 1000 , a first display device 100 disposed above (arranged in odd-numbered columns) and a second display device disposed below (arranged in even-numbered columns) An image displayed on the display device 200 is shown.

When the display apparatuses 100 to 400 of the present invention are disposed on the video wall apparatus 1000, the time difference between the images displayed on the plurality of display apparatuses arranged vertically adjacent to each other in order to prevent image shaking on the screen is reduced. (so that the time difference becomes zero).

Specifically, in order to prevent screen shake from occurring at the interface between the first display apparatus 100 and the second display apparatus 200 , an image is displayed in sub-pixels disposed in the lowermost row of the first display apparatus 100 . The timing at which an image is displayed in the sub-pixels disposed in the uppermost column of the second display apparatus 200 may coincide with the timing at which the image is displayed.

Frame data (control signal and sub-image data) of the first display apparatus 100 is directly output without a time delay from the signal delay unit 700 and is input to the first display apparatus 100 . Therefore, the image is displayed on the liquid crystal panel without delay.

Frame data (control signal and sub-image data) of the second display apparatus 200 is delayed by the signal delay unit 700 for a time set in the delay selection signal SEL and is input to the second display apparatus 200 . Accordingly, the image is displayed on the liquid crystal panel with a delay by the time set in the delay selection signal SEL.

Here, when an image is displayed at a 60Hz driving frequency (1 frame = 16.7ms), the time point at which the image is displayed in the subpixels arranged in the uppermost column of the liquid crystal panel of the first display apparatus 100 is D1+0ms, and , the time point at which an image is displayed in the sub-pixels arranged in the lowermost column of the liquid crystal panel is D1+16.7ms.

A signal to match the time point at which an image is displayed in the subpixels disposed in the lowermost column of the first display apparatus 100 and the time point at which the image is displayed in the subpixels disposed in the uppermost column of the second display device 200 . The delay unit 700 delays the frame data (control signal and sub-image data) of the second display apparatus 200 for a period of time (16.7 ms) corresponding to one frame and then outputs it. Through this, the time point at which an image is displayed in the subpixels arranged in the uppermost column of the liquid crystal panel of the second display device 200 becomes D2 (D1+17.6ms), and the subpixels arranged in the lowermost column of the liquid crystal panel The time at which the image is displayed in , becomes D2+16.7ms.

In the video wall device of the prior art, when an image moves from left to right, there is a problem in that motion judder occurs at the interface between the first and second display devices 100 and 200 adjacent up and down. .

On the other hand, in the video wall device 1000 of the present invention, an image is displayed in subpixels disposed at the bottom of the first display device 100 that are vertically adjacent to each other, and the video wall device 1000 is disposed at the top of the second display device 200 . The timing at which the image was displayed in the subpixels was matched. Through this, generation of motion judder at the boundary between the vertically adjacent display devices 100 and 200 is prevented.

In other words, the video wall device 1000 of the present invention includes a time point at which a gate driving signal is output and an image display time point, and a time point at which an image is displayed, which is supplied to a gate line disposed at the lower end of the first display device 100 adjacent vertically. The output timing of the gate driving signal supplied to the gate line disposed on the upper end of the display device 200 coincides with the timing of displaying the image. Through this, generation of motion judder at the boundary between the vertically adjacent display devices 100 and 200 is prevented.

In the above description, the expression "time point coincided" includes not only the case where the deviation between the two signals is mathematically zero, but also includes a minute time deviation including general signal delay occurring in the circuit configuration. Therefore, in the present invention, even if a minute time deviation occurs between the first signal and the second signal due to a signal delay that can be tolerated in a general electronic device, the input/output timing of the first signal and the second signal is regarded as coincident. can be considered

The video wall device having the above-described configuration may improve display quality by preventing image blur at the boundary surface of a plurality of display devices. In addition, according to the present invention, it is possible to adjust the timing at which an image is displayed on the first and second display devices arranged vertically adjacent to each other. In addition, there is no time difference between the images displayed on the first display device and the second display device disposed vertically adjacent to each other (so that the time difference becomes zero), so that at the boundary between the first and second display devices, there is no difference in time. Avoid screen shake. In addition, the present invention can control the output timing of the gate driving signal and the output timing of the data voltage of each of the display devices constituting the video wall device. The effect of the present invention is not limited to the above-mentioned effects, and another effect not mentioned will be clearly understood by those skilled in the art from the following description.

Although the embodiments of the present invention have been described in more detail with reference to the accompanying drawings, the present invention is not necessarily limited to these embodiments, and various modifications may be made within the scope without departing from the spirit of the present invention. Therefore, the embodiments disclosed in the present invention are not intended to limit the technical spirit of the present invention, but to explain, and the scope of the technical spirit of the present invention is not limited by these embodiments. Therefore, it should be understood that the embodiments described above are illustrative in all respects and not restrictive. The protection scope of the present invention should be interpreted by the claims, and all technical ideas within the scope equivalent thereto should be construed as being included in the scope of the present invention.

100: first display device
110: liquid crystal panel
120: gate driver
130: data driver
140: timing controller
200: second display device
300: third display device
400: fourth display device
500: main controller
600: signal delay unit
700: signal delay unit
1000: video wall device

Claims (8)

A video wall device for displaying an image by connecting a plurality of display devices, the video wall device comprising:
a first display device disposed at an upper side of the screen;
a second display device disposed below the first display device;
a main controller supplying image data, a timing signal, and a control signal to each of the first and second display devices; and
a signal delay unit disposed between the main controller and the first and second display devices;
The signal delay unit selectively delays the control signal and image data input to each of the first and second display devices for a predetermined time and outputs them,
Match a time point at which an image is displayed at the lower end of the first display device and a time point at which an image is displayed at the upper end of the second display device;
an output timing of the gate driving signal supplied to the lowermost gate line disposed adjacent to the second display device in the first display device, and the uppermost gate line disposed adjacent to the first display device in the second display device. A video wall device that matches the output timing of the supplied gate drive signal. A video wall device for displaying an image by connecting a plurality of display devices, the video wall device comprising:
a first display device disposed at an upper side of the screen;
a second display device disposed below the first display device;
a main controller supplying image data, a timing signal, and a control signal to each of the first and second display devices; and
and a signal delay unit disposed inside each of the first and second display devices;
The signal delay unit selectively delays a control signal and image data within the first and second display devices for a predetermined time,
Match a time point at which an image is displayed at the lower end of the first display device and a time point at which an image is displayed at the upper end of the second display device;
an output timing of the gate driving signal supplied to the lowermost gate line disposed adjacent to the second display device in the first display device, and the uppermost gate line disposed adjacent to the first display device in the second display device. A video wall device that matches the output timing of the supplied gate drive signal. 3. The method according to claim 1 or 2,
The signal delay unit is configured to include a plurality of shift registers,
A video wall device in which delay times of the control signal and image data increase in proportion to the number of shifter registers through which the signal passes. 3. The method according to claim 1 or 2,
The signal delay unit includes a flash memory, and the video wall device adjusts output timing of the control signal and image data input to the signal delay unit according to a preset delay selection signal. delete delete delete delete

Images