KR102196180B1 - Display device - Google Patents

Abstract

An object of the present invention is to provide a method of improving product yield by preventing defects caused by static electricity when a floating dummy link wiring is formed on an array substrate for a display device.
To this end, the present invention relates to a display panel including an array substrate having a display area and a non-display area, a plurality of link wirings formed in a non-display area of the array substrate, a plurality of dummy link wirings, and the ratio of the array substrate. A display device including a ground pad formed in a display area and electrically connected to the plurality of dummy link wirings, and a driving board including a ground terminal electrically connected to the ground pad is provided.

Description

Display device}

The present invention relates to a display device, and more particularly, to a display device capable of providing a discharge path capable of discharging static electricity to a dummy link wiring configured in a non-display area of an array substrate of the display device. About.

As the information society develops, the demand for display devices for displaying images is increasing in various forms, and in recent years, liquid crystal displays (LCDs), plasma display panels (PDPs), organic light emitting devices Various flat display devices such as OLED (organic light emitting diodes) are being used.

Among these flat panel display devices, liquid crystal display devices are widely used at present because they have advantages of miniaturization, weight reduction, thinness, and low power driving.

The liquid crystal display includes a liquid crystal panel that displays an image, a driving board on which various circuit parts are mounted, a flexible circuit film (FPC (Flexible Printed Circuit) film) for connecting the driving board and the liquid crystal panel, and a flexible circuit film. It includes a driving-integrated circuit (D-IC) mounted on the liquid crystal panel in order to drive the liquid crystal panel according to the electric signal transmitted from the driving board.

As such, a case in which the driving integrated circuit is directly mounted on a liquid crystal panel, that is, an array substrate of a liquid crystal panel, is referred to as a COG (chip on glass) method.

In the non-display area of the array substrate of the COG type liquid crystal panel, the liquid crystal panel includes an input pad and an output pad corresponding to each of the input and output bumps of the driving integrated circuit. In addition, the output pad is connected to the corresponding data line and the gate line through a link line, so that a signal applied to the output pad is transmitted to the data line and the gate line.

On the other hand, on the array substrate, a dummy link wiring, which is not used for signal transmission, is formed in addition to the link wiring for transmitting signals as described above. Such a dummy link wiring is formed around the link wiring in the same process as the signal transmission link wiring, but does not have a signal transmission purpose, and thus has an electrically floating state. That is, the dummy link wiring is formed in an electrically insulated state so that no electrical signal is transmitted.

As described above, in a conventional liquid crystal display device, since the dummy link wiring has a floating state, a separate static discharge path does not exist in the dummy link wiring.

Accordingly, defects may be caused by static electricity generated in the manufacturing process of the liquid crystal display device. That is, static electricity generated in the rubbing process or the driving integrated circuit mounting process, etc., cannot escape through the floating dummy link wiring and is transferred to the data wiring or the gate wiring through the surrounding link wiring. Electrical open (open) or short (short) occurs along the wiring.

This causes a line defect of the liquid crystal panel, resulting in a problem of lowering the product yield of the liquid crystal display.

Meanwhile, the same problem occurs in other display devices that use an array substrate on which dummy link wiring is formed in addition to the liquid crystal display device.

An object of the present invention is to provide a method of improving product yield by preventing defects caused by static electricity when a floating dummy link wiring is formed on an array substrate for a display device.

In order to achieve the above-described problems, the present invention provides a display panel including an array substrate having a display area and a non-display area, a plurality of link wirings formed in the non-display area of the array substrate, and a plurality of dummy link wirings. And a ground pad formed in a non-display area of the array substrate and electrically connected to the plurality of dummy link wirings, and a driving board including a ground terminal electrically connected to the ground pad.

Here, it may include a discharge wiring formed in a non-display area of the array substrate and connecting the dummy link wiring and the ground pad.

In addition, the discharge wiring may be composed of a plurality.

In addition, the plurality of dummy link wirings include first dummy link wirings and second dummy link wirings formed on different layers in cross-sectional area, and the discharge wiring is a first dummy link wiring extending and directly connected. And a second discharge wire connected through a first discharge wire and a connection pattern with the second dummy link wire, and the connection pattern includes the second dummy link through a first contact hole formed on the second dummy link wire. The link wiring may be contacted, and the second discharge wiring may be contacted through a second contact hole formed on the second discharge wiring.

In addition, it includes a discharge connection pattern connecting the discharge wiring and the ground pad, wherein the discharge connection pattern is in contact with the discharge wiring through a third contact hole formed on the discharge wiring, and is formed on the ground pad. The ground pad may be contacted through the fourth contact hole.

In addition, the ground pad may be configured in plural to correspond to each of the plurality of discharge wirings.

Further, in the display area, a gate line, a data line crossing the gate line with a gate insulating layer therebetween, and a pixel electrode located in the pixel area and formed on the protective layer on the data line are formed, and the first dummy The link wiring and the discharge wiring may be formed on the same layer as the gate wiring, the second dummy link wiring may be formed on the same layer as the data wiring, and the connection pattern may be formed on the same layer as the pixel electrode.

In the display area, a gate line, a data line crossing the gate line with a gate insulating layer therebetween, and a pixel electrode located in the pixel area and formed on the protective layer on the data line are formed, and the discharge line It is formed on the same layer as the gate wiring, and the discharge connection pattern may be formed on the same layer as the pixel electrode.

And a flexible circuit film connecting the driving board and the array substrate, wherein the flexible circuit film includes a first ground bump connected to the driving board and electrically connected to the ground terminal, and a first ground bump connected to the ground pad. It may include two ground bumps, and a ground wiring pattern connecting the first ground bump and the second ground bump.

Also, the display panel may be a liquid crystal panel.

According to the present invention, in the manufacturing process of the array substrate for a display device, the dummy link wiring is electrically connected to the ground terminal of the mother substrate to form the first discharge path. After the array substrate is manufactured, the dummy link wiring is connected to the driving board. It is electrically connected to the ground terminal to form a second discharge path.

Accordingly, even if static electricity is generated in the dummy link wiring during the manufacturing process of the array substrate or the manufacturing process of the liquid crystal display that proceeds thereafter, the generated static electricity can escape through the first discharge path or the second discharge path.

Accordingly, it is possible to prevent line defects due to the generation of static electricity, and thus, product yield can be improved.

1 is a schematic view schematically showing a discharge path structure of a dummy link wiring in a manufacturing process of an array substrate according to an embodiment of the present invention.
2 is a schematic diagram showing a discharge path structure of a dummy link wiring after manufacturing of an array substrate according to an embodiment of the present invention is completed.
3 is a schematic view showing a first mother substrate in which a plurality of array substrates are formed in cell area units according to an embodiment of the present invention.
4 is a diagram schematically showing a cell area in a state of a first mother substrate according to an embodiment of the present invention.
5 is an enlarged view of a portion "A" of FIG. 4;
6 and 7 are cross-sectional views taken along line VI-VI and VII-VII of FIG. 4, respectively.
8 is a schematic cross-sectional view of a pixel structure of a liquid crystal display according to an exemplary embodiment of the present invention.
9 is a schematic view of a liquid crystal display device including a liquid crystal panel, a driving board, and a driving integrated circuit according to an exemplary embodiment of the present invention.
10 schematically illustrates a method of manufacturing a liquid crystal display device according to an exemplary embodiment of the present invention.

Hereinafter, embodiments of the present invention will be described with reference to the drawings.

In the following embodiments, for convenience of description, a liquid crystal display device and an array substrate used therein as an example of a display device and an array substrate used therein will be described.

First, a discharge path of a dummy link wiring configured on an array substrate of a liquid crystal display according to an exemplary embodiment of the present invention will be schematically described with reference to FIGS. 1 and 2.

1 is a schematic diagram showing a structure of a discharge path of a dummy link wiring in a manufacturing process of an array substrate according to an embodiment of the present invention, and FIG. 2 is a dummy link after manufacturing of an array substrate according to an embodiment of the present invention is completed. It is a schematic diagram schematically showing the structure of a discharge path of a wiring.

First, referring to FIG. 1, in the manufacturing process of the array substrate 110, a plurality of array substrate formation regions (ie, cell regions) CA are defined on a mother glass, and each cell region CA ), the array substrate 110 is manufactured in units of the cell area CA. Here, for convenience of explanation, the mother substrate on which the array substrate 110 is manufactured is referred to as a first mother substrate.

At this time, in the non-display area of each cell area CA, a link wiring and a dummy link wiring DLL formed between or outside the link wiring, that is, around the link wiring, are formed in a specific area, that is, a link area. On the other hand, an IC area on which the driving integrated circuit is mounted is located outside the link area, and a connection area to which a flexible printed circuit (FPC) film is connected is located outside the IC mounting area.

Here, the dummy link wiring DLL is formed in a form that does not extend to the display area of each cell area CA. That is, the dummy link wiring (DLL) is a wiring that is not related to the image display in the display area, and does not perform a signal transmission function to the display area, so the dummy link wiring (DLL) exists only in the non-display area and It is not formed by extending with.

Meanwhile, a ground terminal, that is, a ground terminal GT1, is formed outside the cell area CA of the mother substrate, that is, in a peripheral area. For convenience of explanation, the ground terminal GT1 formed on the mother substrate is referred to as the first ground terminal GT1.

At this time, in the embodiment of the present invention, in the manufacturing process of the array substrate 110, a discharge path DP1 is formed by connecting the dummy link wiring DLL to the first ground terminal GT1 formed in the peripheral area of the mother substrate. Is done. Here, for convenience of explanation, the discharge path DP1 in the manufacturing process of the array substrate 110 is referred to as a first discharge path DP1.

As described above, in the manufacturing process of the array substrate 110, the dummy link wiring DLL is electrically connected to the first ground terminal GT1 provided on the mother substrate to form the first discharge path DP1, so that the array substrate Even if static electricity is generated in the dummy link wiring DLL during the manufacturing process of 110, the static electricity can escape to the first ground terminal GT1 along the first discharge path DP1.

As a result, line defects due to static electricity are prevented, so that a product yield of the liquid crystal display device can be improved.

Meanwhile, the first discharge path DP1 is configured to pass through the ground pad GPS configured in the connection area of each cell area CA, and a detailed structure thereof will be described later.

Next, referring to FIG. 2, after manufacturing of each cell region of the first mother substrate is completed, that is, after manufacturing of the array substrate 110 is completed, the first mother substrate is bonded to the second mother substrate. Here, the second mother substrate is for forming a counter substrate, for example, a color filter substrate, which faces the array substrate in cell area units, and the second mother substrate on which the color filter substrate is manufactured is bonded to the first mother substrate.

The first and second parent substrates bonded in this way are cut in cell units to form a liquid crystal panel, and in the liquid crystal panel cut in cell units, the non-display area of the array substrate 110 is not covered by the color filter substrate. It has a state that is exposed to the outside without a state.

At this time, the array substrate 110 of the liquid crystal panel cut in units of cells is connected to the driving board using an FPC film, and a driving integrated circuit is mounted on the array substrate 110.

As described above, after the fabrication of the array substrate 110 is completed, the discharge path DP1 between the dummy link wiring DLL and the first ground terminal GP1 of the first mother substrate is cut off by cell unit cutting. That is, the dummy link wiring (DLL) is in a floating state.

In this way, when the floating state is reached, static electricity generated during the process of mounting the driving integrated circuit on the array substrate 110 may not escape, thereby causing a defect due to static electricity.

To prevent this, for the array substrate 110 of the liquid crystal panel cut in units of cells, the dummy link wiring DLL is connected to the ground terminal GT2 of the driving board, that is, the second ground terminal GT2. DP2) is formed. Here, for convenience of description, the discharge path DP2 after fabrication of the array substrate 110 is referred to as a second discharge path DP2.

As such, after manufacturing the array substrate 110, the dummy link wiring DLL is electrically connected to the second ground terminal GT2 provided on the driving board to form the second discharge path DP2, thereby forming the array substrate. Even if static electricity is generated in the dummy link wiring DLL during the manufacturing process of the liquid crystal display device 110 after manufacturing, the static electricity may escape to the second ground terminal GT2 along the second discharge path DP2.

As a result, line defects due to static electricity are prevented, so that a product yield of the liquid crystal display device can be improved.

Meanwhile, the second discharge path DP2 is also configured to pass through a ground pad (GCP) provided in a non-display area of the array substrate 110, and a detailed structure thereof will be described later.

As described above, according to the embodiment of the present invention, not only during the manufacturing process of the array substrate 110 but also during the subsequent process, that is, throughout the manufacturing process of the liquid crystal display, the dummy link wiring DLL is a discharge path DP1 consisting of a ground path. , DP2).

Therefore, even if static electricity is generated in the dummy link wiring DLL during the manufacturing process of the liquid crystal display device, the generated static electricity can escape along the discharge paths DP1 and DP2 connected to the dummy link wiring DLL. It is possible to prevent line defects caused by the dummy link wiring in a floating state, and as a result, product yield can be improved.

Hereinafter, a discharge path structure of the dummy link wiring DLL according to the embodiment of the present invention will be described in more detail with reference to the drawings.

First, the structure of the discharge path in the manufacturing process of the array substrate will be described.

3 is a diagram schematically showing a first mother substrate in which a plurality of array substrates are formed in cell area units according to an embodiment of the present invention, and FIG. 4 is a cell area in a state of a first mother substrate according to an embodiment of the present invention. FIG. 5 is a diagram schematically illustrating a portion "A" of FIG. 4 on an enlarged scale. 6 and 7 are cross-sectional views taken along cutting lines VI-VI and VII-VII of FIG. 4, respectively, and FIG. 8 is a schematic cross-sectional view showing a pixel structure of a liquid crystal display according to an exemplary embodiment of the present invention. .

Referring to FIG. 3, a plurality of cell areas CA are defined in a first mother substrate MG1 according to an embodiment of the present invention, and an array substrate 110 is formed in units of cell areas CA.

In the first mother substrate MG1, a first ground terminal GT1 is formed in a peripheral area OA around a plurality of cell areas CA.

At this time, one or a plurality of first ground terminals GT1, that is, at least one, may be formed on the first mother substrate MG1. Here, for convenience of description, a case in which two first ground terminals GT1 are formed on the first mother substrate MG1 will be exemplified.

In this case, some of the plurality of cell areas CA are connected to one of the two first ground terminals GT1, and the remaining part of the plurality of cell areas CA is the two first ground terminals GT1. It may be configured to be connected to the other one.

That is, a plurality of cell regions may be divided into blocks BL, and one first ground terminal GT1 may be configured to correspond to each block BL.

Here, each first ground terminal GT1 is electrically connected to a dummy link wiring DLL formed in each of the cell regions CA of the corresponding block BL to form a first ground path DP1. .

In this case, the first ground terminal GT1 and the cell regions CA are configured to be electrically connected through the ground wiring LG. That is, the ground wiring LG is electrically connected to the dummy link wiring DLL formed inside the cell area CA, and extends along the outside of the cell area CA and is connected to the corresponding first ground terminal GT1. .

As such, as each cell area CA is connected to the ground terminal GT1 formed on the first mother substrate MG1 through the ground wiring LG, the dummy link wiring DLL configured in the cell area CA is removed. It has 1 ground path DP1.

The connection between the dummy link wire (DLL) and the ground wire (LG) will be described in more detail.

Referring to FIG. 4, a display area DA and a non-display area NA are defined in the cell area CA, that is, the array substrate 110.

In the display area DA, a plurality of gate lines GL extending in a first direction, a plurality of data lines DL extending in a second direction crossing the first direction, a plurality of gate lines crossing each other, and A plurality of pixels P are defined by data wirings GL and DL and arranged in a matrix form.

In this case, referring to FIG. 8 with respect to the pixel structure of the array substrate 110, a thin film transistor T connected to the gate wiring and data wiring GL and DL corresponding to each pixel P, and a thin film The pixel electrode 130 connected to the transistor T is formed.

The thin film transistor T includes a gate electrode 111 formed on the substrate 110, a gate insulating film 113 formed on the gate electrode 111, a semiconductor layer 115 formed on the gate insulating film 113, and , And source electrodes and drain electrodes 121 and 123 formed on the semiconductor layer 115 and spaced apart from each other.

Meanwhile, the gate line GL is formed of the same material in the same process as the gate electrode 111, and the data line DL is formed of the same material in the same process as the source and drain electrodes 121 and 123.

A passivation layer 125 is formed on the source and drain electrodes 121 and 123, and a drain contact hole 127 exposing the drain electrode 123 is formed in the passivation layer 125. Meanwhile, the pixel electrode 130 is electrically connected to the drain electrode 123 through the drain contact hole 127.

Although not shown, a common electrode is formed on a counter substrate, that is, a color filter substrate, corresponding to the pixel electrode 130 to form an electric field with the pixel electrode 130, and the arrangement of liquid crystal molecules is changed by the electric field thus formed. .

When the pixel electrode 130 and the common electrode are formed on different substrates as described above, liquid crystal molecules are driven using an electric field perpendicular to the substrate.

As another example, the common electrode may be formed on the same array substrate 110 as the pixel electrode 130, and in this case, liquid crystal molecules may be driven by an electric field substantially horizontal to the substrate.

Meanwhile, referring to FIG. 4, various wires and pads for transmitting a signal for driving the pixel P are formed in the non-display area NA outside the display area DA.

In the non-display area NA, a link area A1, an IC area A2, and a connection area A3 may be configured toward one edge of the cell area CA.

The connection area A3 corresponds to an area to which one side of the FPC film connecting the array substrate 110 of the liquid crystal panel and the driving board is connected. In the connection area A3, a plurality of connection pads CP corresponding to a plurality of output bumps formed on one side of the FPC film are formed.

In particular, among the plurality of connection pads CP, a ground pad GCP is provided as a pad used for grounding purposes. Such a ground pad (GCP) is electrically connected to a second ground terminal provided on the driving board while the driving board is connected.

On the other hand, the IC area A2 corresponds to an area in which the COG type driving integrated circuit is mounted. Here, in the embodiment of the present invention, for convenience of description, a case where one driving integrated circuit is used for each array substrate 110 is exemplified, but the present invention is not limited thereto.

As described above, when one driving integrated circuit is used, the driving integrated circuit performs a function of processing both the gate signal and the data signal and outputting them to the corresponding wiring.

In such an IC area A2, a plurality of input pads (IP) corresponding to a plurality of input bumps formed on one side of the driving integrated circuit are formed, and a plurality of input pads (IP) corresponding to a plurality of output bumps formed on the other side of the driving integrated circuit are formed. The output pad OP of is formed.

At this time, the input pad (IP) and the corresponding connection pad (CP) are electrically connected through a transmission line (TL) formed therebetween, and the electrical signal transmitted to the connection pad (CP) through the transmission line (TL) is It is sent to the input pad (IP).

Here, in addition to the output pad OP that outputs an electrical signal, a dummy pad DOP that does not output a separate electrical signal may be formed in the IC area A2.

Meanwhile, the link area A1 corresponds to an area in which a link wiring LL for electrically connecting the IC area A2 and the display area DA is formed. In other words, the link wiring LL has one end connected to the corresponding gate wire GL or the data line DL, and the other end is connected to the corresponding output pad OP, and the electrical output from the output pad OP. The signal is transmitted to the gate line GL or the data line DL.

At this time, in the link area A1, a plurality of dummy link wirings DLLs configured not to transmit separate electrical signals other than the link wirings LL transmitting electrical signals are formed.

The dummy link wiring DLL may be formed between the link wirings LL or may be formed outside the link wirings LL. That is, the dummy link wiring DLL may be formed around the link wiring LL.

One end of the dummy link wiring DLL is connected to a corresponding dummy pad DOP, and the other end is formed to have a disconnected state in the non-display area NA without extending into the display area DA.

The dummy link wiring DLL configured as described above is configured to be electrically connected to the discharge wiring LD formed in the non-display area DA.

On the other hand, the discharge wiring LD connected to the dummy link wiring DLL is connected to the ground pad (GCP) described above. In particular, the ground wiring LG formed on the first mother substrate MG1 via the ground pad (GCP). And is electrically connected.

Accordingly, the dummy link wiring DLL is connected to the first ground terminal GT1 provided of the first mother substrate MG1 through the discharge wiring LD and the ground wiring LG, and thus the dummy link wiring DLL A first ground path DP1 for can be formed.

In this case, the discharge wiring LD formed in the non-display area NA may be formed to extend along one direction, for example, to be formed to extend along the edge direction of the array substrate 110 near the connection pad CP. I can. In addition, one end of the extended discharge line LD may be positioned to correspond to the ground pad GCP.

The discharge wiring LD formed in the non-display area NA and the ground wiring LG formed outside the cell area CA are electrically connected, and a discharge connection pattern LDP may be formed to electrically connect them. .

The discharge connection pattern LDP may be configured to be connected to the discharge line LD at one end and extend across the edge of the cell area CA to be connected to the ground line LG at the other end.

Accordingly, the dummy link wiring DLL can be electrically connected to the ground wiring LG, so that the first discharge path DP1 from the dummy link wiring DLL to the ground terminal GT1 of the first mother substrate MG1 ) Can be formed.

Meanwhile, the discharge connection pattern LDP extended to the ground wiring LG may be formed to pass through the ground pad GCP, and may be configured to contact the ground pad GCP. Accordingly, the discharge wiring LD can be electrically connected to the ground pad (GCP) as well as the ground wiring (LG), so that even after the cell area CA is cut, the dummy link wiring DLL is the ground pad (GCP). It has a state in which it is electrically connected to, and as a result, a second discharge path can be formed from the dummy link wiring DLL to the ground terminal of the driving board.

Hereinafter, the electrical connection structure between the discharge wiring LD and the discharge connection pattern LDP, the ground pad CGP and the ground wiring LG will be described in more detail with reference to FIGS. 5 to 7.

In an embodiment of the present invention, for convenience of explanation, the discharge wiring LD, the ground pad GCP, and the ground wiring LG are formed of a gate wiring material, that is, a gate material in the process of forming the gate wiring GL. Take the case as an example. Of course, some of these components may be formed of a data line material, that is, a data material during the process of forming the data line DL.

Meanwhile, the discharge connection pattern LDP is a pixel electrode material in the process of forming the pixel electrode 130, and may be formed of, for example, a transparent conductive material such as ITO or IZO.

In such a case, the discharge connection pattern LDP can contact the discharge wiring LD, the ground pad GCP, and the ground wiring LG through the contact holes CH3, CH4, and CH5. Here, for convenience of explanation, the contact holes formed on the discharge line LD, the ground pad GCP, and the ground line LG are respectively a third contact hole CH3, a fourth contact hole CH4, and a fifth contact hole. It is called a contact hole (CH5).

The third to fifth contact holes CH3 to CH5 may be formed through the passivation layer and the gate insulating layers 125 and 113.

In particular, a region between the discharge wiring LD and the ground pad GCP is formed in the same process as these, and a wiring may be positioned for power or signal transmission. In this case, it may be difficult to directly connect the discharge wiring LD, the ground pad, and the ground wiring (GCP, LG) with a pattern made of a gate material. Therefore, by forming a discharge connection pattern (LDP) made of a pixel electrode material as a bridge pattern, the discharge wiring (LD), the ground pad, and the ground wiring (GCP, LG) can be electrically connected in the form of jumping. have.

The electrical connection structure between the dummy link wiring DLL and the discharge wiring LD will be described in more detail.

In the embodiment of the present invention, the dummy link wirings DLL formed in the non-display area NA are located on different layers in cross-sectional area. For example, some of them are formed of a gate material and some of them are formed of a data wiring. An example is a case where a data wiring material is formed during the process. Of course, all of the dummy link wires DLL may be formed of the same material on the same layer.

Here, for convenience of explanation, the dummy link wiring (DLL) formed of the gate material is referred to as the first dummy link wiring (DLL1), and the dummy link wiring (DLL) formed of the data material is referred to as the second dummy link wiring (DLL2). do.

At this time, the first dummy link wire DLL1 is formed to extend to the discharge wire LD formed on the same layer, so that it may directly contact the discharge wire LD.

Meanwhile, since the second dummy link wiring DLL2 is formed on a layer different from the discharge wiring LD, it extends in the direction of the discharge wiring LD, and the extended portion, that is, the extension portion, is the discharge wiring through the connection pattern LP. (LD) can be contacted. The connection pattern LP may be formed of a pixel electrode material in the process of forming the pixel electrode 130, and may be in contact with the second dummy link wiring and discharge wiring DLL2, LD through the contact holes CH1 and CH2. I can. Here, for convenience of explanation, the contact holes formed on the second dummy link wiring and the discharge wiring DLL2 and LD are referred to as a first contact hole CH1 and a second contact hole CH2, respectively.

The first and second contact holes CH1 and CH2 may be formed through the passivation layer and the gate insulating layers 113 and 125.

On the other hand, the discharge wiring (LD) may be composed of a plurality, for example, the first discharge wiring (LD1) connected to the first dummy link wiring (DLL1) and the second dummy link wiring (DLL2). It may include a second discharge wiring (LD2). In addition, the discharge connection pattern LDP may be composed of a plurality, for example, the first and second discharge connection patterns LDP1 and LDP2 respectively connected to the first and second discharge wirings LD1 and LD2. I can. Moreover, ground pads (GCP) may also be composed of a plurality, for example, first and second ground pads (GCP1, GCP2) respectively connected to the first and second discharge connection patterns (LDP1, LDP2). have.

In this way, as the discharge wiring (LD), the discharge connection pattern (LDP), and the ground pad (GCP) are formed in a large number, the path of the discharge path to the dummy link wiring (DLL) also becomes a number, thereby discharging against static electricity. It will be more stable and effective than this.

Meanwhile, the structure of the components constituting the above-described discharge path is an example, and it is obvious that various modifications are possible.

As described above, during the manufacturing process for the array substrate 110, the dummy link wiring DLL is electrically connected to the ground terminal GT1 provided on the mother substrate MG1 to form the discharge path DP1. . Accordingly, even if static electricity generated in the rubbing process or the like is applied to the dummy link wiring DLL, such static electricity can escape to the ground terminal GT1 of the mother substrate MG1 through the discharge path DP1.

Accordingly, it is possible to prevent static electricity failure due to the dummy link wiring (DLL) formed in a conventional floating state, and thus, product yield can be improved.

Hereinafter, the structure of the discharge path of the dummy link wiring DLL after fabrication of the array substrate 110 will be described with reference to FIG. 9. 9 is a diagram schematically showing a liquid crystal display device including a liquid crystal panel, a driving board, and a driving integrated circuit according to an exemplary embodiment of the present invention.

In FIG. 9, for convenience of explanation, the second discharge path DP2 for the dummy link wiring DLL is schematically illustrated, and the omitted configuration may be described with reference to FIGS. 4 and 5 together. .

Referring to FIG. 9, the liquid crystal display device 10 includes a liquid crystal panel 100 cut into cells and a driving board (CB) connected to the liquid crystal panel 100 through a flexible circuit film (FF), that is, an FPC film (FF). ) Can be included.

Here, the liquid crystal panel 100 is formed by performing a cutting process in units of cells for the bonded first and second parent substrates.

The liquid crystal panel 100 formed as described above includes an array substrate 110 and a color filter substrate 160 as a counter substrate facing the array substrate 110 and a liquid crystal layer (not shown) formed therebetween. Here, the non-display area NA of the array substrate 110 protrudes to the outside of the color filter substrate 160.

The first ground path (refer to DP1 in FIG. 4) for the array substrate 110 in the liquid crystal panel state no longer exists by the cell-by-cell cutting process. That is, the array substrate 110 is separated from the first mother substrate (refer to MG1 in FIG. 3) by the cell-unit cutting process, so that the dummy link wiring (DLL) of each array substrate 110 and the first mother substrate are electrically connected. The relationship is cut off, and the first ground path of the dummy link wiring DLL also disappears.

On the other hand, in the embodiment of the present invention, by electrically connecting the dummy link wiring DLL to the ground terminal of the driving board CB, that is, the second ground terminal GT2, the dummy link wiring DLL in the liquid crystal panel state is A ground path for the ground, that is, a second ground path DP2 is formed. In this case, the second ground path DP2 may be implemented through the FPC film FF connecting the driving board CB and the liquid crystal panel 100.

The driving board CB is a component for generating and supplying electrical signals driving the liquid crystal panel 100, and a plurality of driving circuits including a timing controller are mounted on the driving board CB. Meanwhile, a second ground terminal GT2 is provided on the driving board CB.

The FPC film (FF) is connected to the driving board (CB) on one side and the liquid crystal panel (100) on the other side, and functions to transmit the electrical signal output from the driving board (CB) to the liquid crystal panel (100). .

The FPC film FF includes a plurality of wiring patterns (FLP), a plurality of FPC input bumps (FIP) formed on one side connected to the driving board (CB), and a plurality of FPCs formed on the other side connected to the liquid crystal panel 100. Output bump (FOP) is configured.

A plurality of FPC input bumps (FIP) are connected to a plurality of output pads (not shown) formed on the driving board (CB), respectively, and receive signals output from the driving board (CB).

A plurality of FPC output bumps (FOP) are connected to a plurality of connection pads (see CP in FIG. 4) formed on the liquid crystal panel 100, respectively, to output a signal applied from the driving board (CB) to the liquid crystal panel 100. do.

Each wiring pattern (FLP) is connected to the FPC input bump (FIP) at one end and the FPC output bump (FOP) at the other end, so that the signal input to the FPC input bump (FIP) is transmitted to the FPC output bump (FOP). do.

Meanwhile, in each of the plurality of FPC input bumps (FIP), the plurality of wiring patterns (FLP), and the plurality of FPC input bumps (FOP) configured on the above-described FPC film FF, a second configuration of the driving board CB It consists of a grounding input bump (GIP) connected to the ground terminal (GT2), a grounding wiring pattern (GLP), and a grounding output bump (GOP). Here, for convenience of explanation, the input bump for grounding is called a first ground bump (GIP), the output bump for grounding is called a second ground bump (GOP), and the wiring pattern for grounding is called a ground wiring pattern (GLP). do.

In this way, the first and second ground bumps (GIP, GOP) and ground wiring patterns (GLP), which are components for grounding configured on the FPC film (FF), are electrically connected to the ground pad (GCP in FIG. 4) of the liquid crystal panel 100. Connected. That is, the ground pad connected to the dummy link wiring DLL as the ground pad of the liquid crystal panel 100 is connected to the second ground bump GOP. At this time, the second ground bump GOP is in contact with the discharge connection pattern LDP in contact with the ground pad, and is electrically connected to the ground pad.

In addition, the first ground bump GIP is connected to the second ground terminal GT2 through the ground wiring pattern GCL configured on the driving board CB.

Accordingly, the dummy link wiring (DLL) of the liquid crystal panel 100 is electrically connected to the second ground terminal (GT2) of the driving board (CB) through the ground pad and the FPC film (FF), A second ground path DP2 for the link wiring DLL can be formed.

Therefore, even after the formation of the array substrate 110, the ground path DP2 for the dummy link wiring DLL can be implemented, and thus a liquid crystal display device such as a process of attaching a driving integrated circuit (DIC) to the liquid crystal panel 100 Even if static electricity is generated in the dummy link wiring DLL during the manufacturing process of (10), the generated static electricity can escape through the second ground path DP2. As a result, defects due to generation of static electricity are prevented, and product yield can be improved.

Meanwhile, as described above, after connecting the driving board CB to the liquid crystal panel 100 through the FPC film FF, driving the non-display area NA of the array substrate 110 of the liquid crystal panel 100 An integrated circuit (DIC) can be mounted. The driving integrated circuit DIC is mounted in the IC area of the non-display area NA (see A2 in FIG. 4), so that the input bump and the output bump of the driving integrated circuit DIC are It is connected to an input pad and an output pad (see IP and OP in Fig. 4).

Hereinafter, a method of manufacturing a liquid crystal display device having the above-described configuration will be briefly described with reference to FIG. 10.

Referring to FIG. 10, a plurality of array substrates are manufactured in cell area units in a first mother substrate (S11), and a plurality of color filter substrates are manufactured in cell area units in a second mother substrate (S12). Here, in manufacturing the array substrate in the state of the first mother substrate, a first ground path is formed by connecting the dummy link wiring to the first ground terminal of the first mother substrate.

Next, the first and second mother substrates are bonded (S20). In such a bonding process, a liquid crystal layer may be filled between the array substrate and the color filter substrate.

Next, a cutting process is performed in units of cells for the bonded first and second parent substrates (S30). The cut liquid crystal panel is formed by such a cell unit cutting process.

Next, the driving board is connected to the liquid crystal panel (S40). At this time, the driving board is connected to the liquid crystal panel through the flexible circuit film. Accordingly, the dummy ring-large wiring in the liquid crystal panel state is connected to the second ground terminal of the driving board, thereby forming a second ground path.

Next, a driving integrated circuit is mounted in the non-display area of the liquid crystal panel (S50).

Through the above process, a liquid crystal display according to an embodiment of the present invention can be manufactured.

As described above, according to an embodiment of the present invention, during the manufacturing process of the array substrate, the dummy link wiring is electrically connected to the ground terminal of the mother substrate to form the first discharge path, and after the array substrate is manufactured, the dummy link The wiring is electrically connected to the ground terminal of the driving board to form a second discharge path.

Accordingly, even if static electricity is generated in the dummy link wiring during the manufacturing process of the array substrate or the manufacturing process of the liquid crystal display that proceeds thereafter, the generated static electricity can escape through the first discharge path or the second discharge path.

Accordingly, it is possible to prevent line defects due to the generation of static electricity, and thus, product yield can be improved.

Meanwhile, in the foregoing description, for convenience of explanation, a liquid crystal display has been described as an example, but it is understood by those skilled in the art that the embodiment of the present invention can be applied to an array substrate with dummy link wiring and all types of display devices using the same. It's self-evident.

The above-described embodiment of the present invention is an example of the present invention, and can be freely modified within the scope of the spirit of the present invention. Accordingly, the present invention includes modifications of the present invention within the scope of the appended claims and equivalents thereto.

10: liquid crystal display device 100: liquid crystal panel
110: array substrate 160: color filter substrate
MG1: first mother substrate CA: cell area
LL: Link wiring DLL: Dummy link wiring
LD: Discharge wiring LG: Ground wiring
LDP: discharge connection pattern GCL: ground wiring pattern
GT1: 1st ground terminal GT2: 2nd ground terminal

Claims (11)

A display panel including an array substrate having a display area and a non-display area;
A plurality of link wirings and a plurality of dummy link wirings formed in a non-display area of the array substrate;
A ground pad formed in a non-display area of the array substrate and electrically connected to the plurality of dummy link wirings;
A driving board having a ground terminal electrically connected to the ground pad;
A discharge wiring formed in a non-display area of the array substrate and connecting the dummy link wiring and a ground pad;
Discharge connection pattern connecting the discharge wiring and the ground pad
Including,
The discharge connection pattern is in contact with the discharge wire through a third contact hole formed on the discharge wire, and the ground pad through a fourth contact hole formed on the ground pad.
Display device.
delete The method of claim 1,
A display device comprising a plurality of discharge wirings.
The method of claim 3,
The plurality of dummy link wirings include a first dummy link wiring and a second dummy link wiring formed on different layers in cross section,
The discharge wiring includes a first discharge wiring directly connected by extending the first dummy link wiring, and a second discharge wiring connected to the second dummy link wiring through a connection pattern,
The connection pattern is in contact with the second dummy link wiring through a first contact hole formed on the second dummy link wiring, and the second discharge wiring through a second contact hole formed on the second discharge wiring. In contact
Display device.
delete The method of claim 3,
The ground pad is composed of a plurality to correspond to each of the plurality of discharge wiring
Display device.
The method of claim 4,
In the display area, a gate line, a data line crossing the gate line with a gate insulating layer therebetween, and a pixel electrode located in the pixel area and formed on the protective layer on the data line are formed,
The first dummy link wiring and the discharge wiring are formed on the same layer as the gate wiring,
The second dummy link wiring is formed on the same layer as the data wiring,
The connection pattern is formed on the same layer as the pixel electrode.
Display device.
The method of claim 1,
In the display area, a gate line, a data line crossing the gate line with a gate insulating layer therebetween, and a pixel electrode located in the pixel area and formed on the protective layer on the data line are formed,
The discharge wiring is formed on the same layer as the gate wiring,
The discharge connection pattern is formed on the same layer as the pixel electrode.
Display device.
The method of claim 1,
Including a flexible circuit film connecting the driving board and the array substrate,
The flexible circuit film,
A first ground bump connected to the driving board and electrically connected to the ground terminal;
A second ground bump connected to the ground pad;
Including a ground wiring pattern connecting the first ground bump and the second ground bump
Display device.
The method according to any one of claims 1, 3, 4, and 6 to 9,
The display panel is a liquid crystal panel.
A display panel including an array substrate having a display area and a non-display area;
A plurality of link wirings and a plurality of dummy link wirings formed in a non-display area of the array substrate;
A ground pad formed in a non-display area of the array substrate and electrically connected to the plurality of dummy link wirings;
A driving board having a ground terminal electrically connected to the ground pad;
Discharge wiring formed in the non-display area of the array substrate and connecting the dummy link wiring and the ground pad
Including,
The discharge wiring is composed of a plurality,
The plurality of dummy link wirings include a first dummy link wiring and a second dummy link wiring formed on different layers in cross section,
The discharge wiring includes a first discharge wiring directly connected by extending the first dummy link wiring, and a second discharge wiring connected to the second dummy link wiring through a connection pattern,
The connection pattern is in contact with the second dummy link wiring through a first contact hole formed on the second dummy link wiring, and the second discharge wiring through a second contact hole formed on the second discharge wiring. In contact
Display device.

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