KR20080020168A - Array substrate and display panel having the same - Google Patents

Abstract

An array substrate and a display panel having the same are provided to form a static electricity preventing unit on the outer wall of a display area and connect the static electricity preventing unit with a ground, thereby inducing static electricity applied from the outside to the ground. A base substrate comprises a display area(DA), where plural pixel units(P) are formed, and a peripheral area(PA) surrounding the display area. A pad unit(120) is formed in the peripheral area, and comprises a driving pad(122b) for receiving a driving signal from the outside and a ground pad(122a) for receiving a ground signal. A static electricity preventing unit(130) is formed in the peripheral area, and emits static electricity to the outside by being electrically connected with the ground pad.

Description

Array board and display panel having same {ARRAY SUBSTRATE AND DISPLAY PANEL HAVING THE SAME}

1 is a perspective view illustrating a display panel according to a first exemplary embodiment of the present invention.

FIG. 2 is a plan view illustrating the array substrate of FIG. 1. FIG.

3 is an enlarged plan view of a portion of an array substrate in a display panel according to a second exemplary embodiment of the present invention.

4 is a plan view illustrating an array substrate in a display panel according to a third exemplary embodiment of the present invention.

FIG. 5 is an enlarged plan view of an array substrate and an opposing substrate of part A illustrated in FIG. 4.

FIG. 6 is a cross-sectional view illustrating a portion of an array substrate and a counter substrate which are cut along the cutting line I ′ I ′ illustrated in FIG. 4.

<Description of the symbols for the main parts of the drawings>

100: array substrate 120: pad portion

122: first connection pad portion 124: second connection pad portion

122a: first ground pad 124a: second ground pad

130a: dummy metal pattern 130b: dummy wiring

130,131: first antistatic portion 200: counter substrate

230: second static electricity prevention unit

The present invention relates to an array substrate and a display panel having the same, and more particularly, to an array substrate for removing defects caused by static electricity and a display panel having the same.

In general, a liquid crystal display device includes a liquid crystal display panel for displaying an image by using the light transmittance of the liquid crystal, and a driving chip for driving the liquid crystal display panel.

The liquid crystal display panel includes an array substrate on which a plurality of switching elements are formed, a color filter substrate facing the array substrate and on which a color filter and a common electrode are formed, and a liquid crystal layer interposed between the array substrate and the color filter substrate.

The array substrate includes a plurality of gate lines, a plurality of data lines, and pixel portions formed in an area defined by the gate lines and data lines. Thin film transistors and pixel electrodes connected to the gate lines and the data lines are formed in the pixel units, respectively.

The color filter substrate includes a black matrix, a color filter, and a common electrode. In order to apply a common voltage to the common electrode of the color filter substrate, a plurality of short points made of a conductive material are formed on the array substrate. The short point electrically connects the common electrode of the array substrate and the color filter substrate to apply a common voltage input to the array substrate to the common electrode.

On the other hand, due to the application of a new high integration technology, such as ASG (Amorphous Silicon Gate), Chip On Glass (COG), a large number of metal patterns including the short point is formed on the outside of the array substrate. Accordingly, the static electricity generated in the display panel manufacturing process is introduced along the metal patterns from the outside, thereby causing a problem of damaging the driving chip or the switching element.

Accordingly, the technical problem of the present invention is to solve such a conventional problem, and an object of the present invention is to provide an array substrate for controlling defects caused by static electricity.

Another object of the present invention is to provide a display panel having the above-described array substrate.

In order to realize the above object of the present invention, an array substrate includes a base substrate, a pad portion, and an antistatic portion. The base substrate includes a display area in which a plurality of pixel parts are formed and a peripheral area surrounding the display area. The pad part is formed in the peripheral area, and has a driving pad to which a driving signal is transmitted from the outside and a ground pad to which a ground signal is transmitted. The antistatic portion is formed in the peripheral area and is electrically connected to the ground pad to discharge static electricity to the outside.

In this case, the antistatic portion preferably includes a dummy metal pattern formed in the peripheral area and a dummy wiring connecting the dummy metal pattern and the ground pad, and is preferably formed in the peripheral area to surround the display area. Do.

In addition, in order to realize the above object of the present invention, the display panel according to the exemplary embodiment includes a display area and a peripheral area surrounding the display area, and includes an array substrate, an opposite substrate, and a liquid crystal layer. The array substrate has a pad portion formed in the peripheral region and having a ground pad, and a first antistatic portion formed in the peripheral region and electrically connected to the ground pad. The opposing substrate faces the array substrate, and the liquid crystal layer is interposed between the array substrate and the opposing substrate.

The first antistatic unit may be formed in the peripheral area to surround the display area, and the counter substrate may further include a second antistatic unit electrically connected to the first antistatic unit.

According to such an array substrate and a display panel having the same, an electrostatic prevention part is formed outside the display area to induce static electricity to the outside, thereby eliminating defects caused by static electricity.

Hereinafter, with reference to the accompanying drawings, it will be described in detail the present invention.

<First Embodiment of Display Panel>

1 is a perspective view illustrating a display panel according to a first exemplary embodiment of the present invention.

Referring to FIG. 1, the display panel 600 includes an array substrate 100, a counter substrate 200, and a liquid crystal layer (not shown) interposed between the array substrate 100 and the counter substrate 200.

The array substrate 100 is a substrate in which a thin film transistor (TFT), which is a switching element, is formed in a matrix form. Data lines and gate lines are respectively connected to the source and gate terminals of the TFTs, and pixel electrodes made of a transparent conductive material are connected to the drain terminals.

The counter substrate 200 is disposed to face the array substrate 100, and is a substrate in which RGB pixels for realizing color are formed in a thin film form. The counter substrate 200 is formed with a common electrode made of a transparent conductive material so as to face the pixel electrode formed on the array substrate 100.

A liquid crystal layer (not shown) is disposed between the array substrate 100 and the counter substrate 200, and the arrangement of the liquid crystals is changed by an electric field formed between the pixel electrode and the common electrode. As the arrangement of the liquid crystals is changed, the light transmittance may be changed to display an image having a desired gray scale.

In addition, the driving chip 400 and the flexible circuit board 500 for driving the display panel 600 are connected to one end of the display panel 600.

The driving chip 400 may output, for example, a driving signal including a gate signal and a data signal for driving the display panel 600 in response to various driving control signals applied through the flexible circuit board 500. have. For example, the driving chip 400 may be directly mounted on the array substrate 100 through a chip on glass (COG) method through an anisotropic conductive film (not shown).

The flexible circuit board 500 is electrically connected to one end of the array substrate 100 by a film on glass (FOG) process, and applies various driving control signals provided from the outside to the driving chip 400.

FIG. 2 is a plan view illustrating the array substrate of FIG. 1. FIG.

1 and 2, the array substrate 100 includes a display area DA and a peripheral area PA surrounding the display area DA. In this case, the peripheral area PA includes first, second, third, and fourth peripheral areas PA_1, PA_2, PA_3, and PA_4 formed on the upper side, the lower side, the left side, and the right side of the display area DA.

The display area DA includes a plurality of gate lines GL extending in a first direction, a plurality of data lines DL and gate lines GL extending in a second direction crossing the first direction. And a plurality of pixel portions P are formed in an area defined by the data lines DL.

In each pixel portion P, a thin film transistor TFT connected to the gate line GL and a data line DL and a pixel electrode PE connected to the thin film transistor TFT are formed.

In the first peripheral area PA_1, a pad part 120 to which a driving signal is applied to drive the pixel part P is formed. In detail, a first connection pad portion 122 to which the driving chip 400 is connected and a second connection pad portion 124 to which the flexible circuit board 500 is connected are formed in the first peripheral area PA.

The first connection pad part 122 is electrically connected to the driving chip 400 and includes a first ground pad 122a and a first driving pad 122b through which a driving signal is transmitted from the outside.

The ground signal is transmitted to the first ground pad 122a, and is preferably electrically connected to the first antistatic unit 130 to be described later. That is, the first ground pad 122a is connected to the first static electricity prevention unit 130 to induce static electricity introduced from the outside to the ground to dissipate it. In this case, the first ground pad 122a may be formed at both ends of the first connection pad part 122. Alternatively, the first ground pad 122a may be formed at one end of the first connection pad portion 122.

The first driving pad 122b receives a driving signal from the driving chip 400 and transmits the driving signal to the display area DA. The first driving pad 122b may include a plurality of pads for driving the pixel portion P of the display area DA. For example, the first driving pad 122b may include a common voltage pad connected to the common voltage line 140, a gate pad connected to the gate driving circuits 150 and 160, and a data pad connected to the data line DL. Include.

The second connection pad part 124 is electrically connected to the flexible circuit board 500 and includes a second ground pad 124a and a second driving pad 124b through which a drive control signal is transmitted from the outside.

The ground signal is transmitted to the second ground pad 124a and is preferably electrically connected to the first static electricity prevention unit 130. That is, the second ground pad 124a is connected to the first static electricity prevention unit 130 to induce static electricity flowing from the outside to the ground and dissipate it. The second ground pad 124a is preferably formed at both ends of the second connection pad portion 124. Alternatively, the second ground pad 124a may be formed at one end of the second connection pad part 124.

The second driving pad 124b receives a driving control signal from the flexible circuit board 500 and transmits the driving control signal to the driving chip 400. The second driving pad 124b may include a plurality of pads for driving the driving chip 400.

In addition, in the present exemplary embodiment, the first and second connection pad parts 122 and 124 are formed together in the first peripheral area PA_1, but differently from the second, third and fourth peripheral areas PA_2, PA_3, and PA_4. It may be formed in each.

The first gate driving circuit 150 is formed in the third peripheral area PA_3. The first gate driving circuit 150 is electrically connected to the gate pad, and sequentially outputs gate signals to the gate lines GL of the first group of the gate lines GL. For example, the first group of gate lines GL may be odd-numbered gate lines GL.

The second gate driving circuit 160 is formed in the fourth peripheral area PA_4. The second gate driving circuit 160 is electrically connected to the gate pad, and sequentially outputs gate signals to the gate lines GL of the second group of the gate lines GL. For example, the second group of gate lines GL may be even-numbered gate lines GL.

The common voltage wiring 140 is formed in the second, third, and fourth peripheral areas PA_2, PA_3, and PA_4 along the periphery of the display area DA. The common voltage line 140 is electrically connected to a common electrode (not shown) of the opposing substrate 200 to transfer the common voltage introduced from the outside to the common electrode. For example, first short points SP_1 may be formed at both ends of the second peripheral area PA_2 to electrically connect the common voltage line 140 and the common electrode.

Meanwhile, a first static electricity prevention unit 130 is formed in the peripheral area PA of the array substrate 100 to prevent static electricity from flowing into the display area DA. In this case, the first antistatic part 130 is electrically connected to the first ground pad 122a of the first connection pad part 122 and the second ground pad 124a of the second connection pad part 124, respectively. It is preferable. Accordingly, the first antistatic unit 130 discharges static electricity to the outside through the first and second ground pads 122a and 124a, respectively. In contrast, the first antistatic unit 130 may be electrically connected to any one of the first and second ground pads 122a and 124a.

Referring to FIG. 2, the first antistatic unit 130 may be formed in the second, third and fourth peripheral areas PA_2, PA_3, and PA_4 so as to surround the outside of the display area DA. In this case, the first antistatic portion 130 is formed outside the common voltage line 140.

For example, the first antistatic unit 130 may be a metal wire that extends to a predetermined width and surrounds the outside of the display area DA. In this case, the first antistatic unit 130 may be formed of the same metal layer as the gate line GL or the data line DL.

As such, the first antistatic unit 130 is formed outside the display area DA of the array substrate 100, and the first antistatic unit 130 and the first and second ground pads 122a and 124a are formed. By electrically connecting, static electricity may be emitted to the outside of the display area DA.

Second Embodiment of Display Panel

3 is an enlarged plan view of a portion of an array substrate in a display panel according to a second exemplary embodiment of the present invention.

Except for the first antistatic portion, the display panel according to the present exemplary embodiment has the same configuration as the display panel of the first exemplary embodiment described above, and thus the detailed description thereof will be omitted, and like reference numerals refer to like elements. Let's use the name.

2 and 3, the first antistatic portion 131 includes a dummy metal pattern 131a and a dummy wiring 131b.

The dummy metal pattern 131a is formed at one end of the first peripheral area PA_1 adjacent to the pad part 120. Alternatively, the dummy metal pattern 131a may be formed in the second, third, and fourth peripheral regions PA_2, PA_3, and PA_4. In this case, the dummy metal pattern 131a may be formed at an edge of the array substrate 100.

In addition, the dummy metal pattern 131a may be formed to have the largest area by utilizing the empty space of the peripheral area PA.

The dummy wiring 131b connects the dummy metal pattern 131a and the first and second ground pads 122a and 124a. The dummy wiring 131b induces static electricity flowing from the outside through the dummy metal pattern 131a to the first and second ground pads 122a and 124a. For example, the dummy wiring 131b may be formed of the same metal layer as the gate wiring GL or the data wiring DL.

Meanwhile, the dummy wiring 131b may extend to any empty space among the peripheral area PA of the array substrate 100 or the counter substrate 200. Accordingly, the static electricity introduced into the empty space is induced to the first and second ground pads 122a and 124a through the dummy wiring 131b.

As such, the static electricity flowing into the empty space or the dummy metal pattern 131a from the outside flows to the ground through the dummy wiring 131b to discharge the static electricity into the display area DA.

<Third Embodiment of Display Panel>

4 is a plan view illustrating an array substrate in a display panel according to a third exemplary embodiment of the present invention. FIG. 5 is an enlarged plan view of an array substrate and an opposing substrate of part A illustrated in FIG. 4. FIG. 6 is a cross-sectional view illustrating a portion of an array substrate and a counter substrate which are cut along the cutting line I ′ I ′ illustrated in FIG. 4.

The display panel according to the present exemplary embodiment has the same configuration as the display panel of the first exemplary embodiment described above, except that the display panel further includes a second antistatic part, and thus, detailed description thereof will be omitted. The same reference numerals and names are used.

4, 5, and 6, the display panel 600 includes an array substrate 100, an opposite substrate 200 facing the array substrate 100, and an array substrate 100 between the array substrate 100 and the opposite substrate 200. A liquid crystal layer 300 interposed therebetween is divided into a display area DA and a peripheral area PA surrounding the display area DA. For reference, the first antistatic portion 130 is formed in the peripheral area PA of the array substrate 100 so as to surround the outside of the display area DA.

The array substrate includes a transparent first base substrate 110, and the pixel portions P including the thin film transistor TFT and the pixel electrode PE are formed on the first base substrate 110.

In detail, the gate electrode 20 connected to the gate line GL, the common voltage line 140, and the first antistatic portion 130 are formed on the first base substrate 110. For example, the gate electrode 20, the common voltage wiring 140, and the first antistatic portion 130 may be made of aluminum-neodynium material.

In this case, the gate electrode 20 is formed in the pixel portion P of the display area DA, and the common voltage line 140 and the first antistatic portion 130 are formed in the peripheral area PA. The first antistatic unit 130 may be formed in the second, third and fourth peripheral areas PA_2, PA_3, and PA_4 so as to surround the outside of the display area DA.

The gate insulating layer 30 is formed on the first base substrate 110 on which the gate electrode 20 and the common voltage wiring 140 are formed. The gate insulating layer 30 is formed of, for example, a silicon nitride film (SiNx) or a silicon oxide film (SiOx).

The channel layer 40 is formed on the first base substrate 110 on which the gate insulating layer 30 is formed. The channel layer 40 includes an active layer 40a and an ohmic contact layer 40b that are sequentially stacked. For example, the active layer 40a is made of amorphous silicon (a-Si), and the ohmic contact layer 40b is made of amorphous silicon (n + a-Si) doped with a high concentration of n + ions.

The source electrode 54 and the drain electrode 55 are formed on the first base substrate 110 on which the channel layer 40 is formed. The source electrode 54 is connected from the data line DL and overlaps the channel layer 40 with a predetermined region. The drain electrode 55 is formed to be spaced apart from the source electrode 54 by a predetermined interval, and overlaps the channel layer 40 with a predetermined region. In this case, the ohmic contact layer 40b is removed between the source electrode 54 and the drain electrode 55 corresponding to the upper portion of the gate electrode 20, and the active layer 40a is exposed.

For reference, the thin film transistor TFT formed on the array substrate 100 includes a gate electrode 20, an active layer 40a, an ohmic contact layer 40b, a source electrode 54, and a drain electrode 55. It is electrically connected to the electrode PE.

The passivation layer 60 is formed on the gate insulating layer 30 on which the source electrode 54 and the drain electrode 55 are formed. The passivation layer 60 may be formed of, for example, a silicon nitride film (SiNx), a silicon oxide film (SiOx), or the like.

Here, the passivation layer 60 formed on one end of the drain electrode 55 is removed, and a contact hole CH exposing a part of the drain electrode 55 is formed. The pixel electrode PE is formed on the passivation layer 60 corresponding to the contact hole CH. The pixel electrode PE contacts the drain electrode 55 through the contact hole CH. For example, the pixel electrode PE may be made of indium tin oxide (ITO) or indium zinc oxide (IZO), which is a transparent conductive material.

In addition, the gate insulating layer 30 and the passivation layer 60 formed on the common voltage line 140 are removed, and a via hole VH exposing a part of the common voltage line 140 is formed. The voltage transfer pad 142 is formed on the passivation layer 60 corresponding to the via hole VH. For example, the voltage transfer pad 142 may be made of the same material as the pixel electrode PE.

The voltage transfer pad 142 contacts the first connection member 3 through the via hole VH. The first connection member 3 serves to transfer the common voltage applied to the array substrate 100 to the common electrode 240 of the opposing substrate 200. Accordingly, the common voltage line 140 may be electrically connected to the common electrode 240 of the opposing substrate 200 by the first connection member 3.

The opposite substrate 200 includes a transparent second base substrate 210, and a color filter layer 220 and a common electrode 240 are formed on one surface of the second base substrate 210 facing the array substrate 100. Is formed.

The color filter layer 220 is formed to face the pixel electrodes PE formed on the array substrate 100 and includes a plurality of color filters of red (R), green (G), and blue (B). Although not shown, a black matrix is formed at the boundary of the color filters.

The common electrode 240 is formed on the front surface of the counter substrate 200 and is formed of the same transparent conductive material as the pixel electrode PE. The common electrode 240 is electrically connected to the common voltage line 140 formed on the array substrate 100 by the first connection member 3 to receive a common voltage. For example, the common electrode 240 may be made of indium tin oxide (ITO) or indium zinc oxide (IZO), which is a transparent conductive material.

In the present embodiment, the second antistatic portion 230 is formed in the peripheral area PA of the opposing substrate 200. The second static electricity preventer 230 is electrically connected to the first static electricity protector 130 formed on the array substrate 100. For example, the first antistatic unit 130 and the second antistatic unit 230 may be electrically connected by the second connection member 5 formed between the array substrate 100 and the counter substrate 200. . For example, the second connection member 5 may be made of silver (Au), which is a conductive material.

The second antistatic portion 230 is formed on the outer side of the common electrode 240 spaced apart from the common electrode 240. Accordingly, the static electricity flowing from the outside can be prevented from being induced to the common electrode 240 formed in the peripheral area PA. The second antistatic portion 230 is formed of the same metal layer as the common electrode 240. For example, the second antistatic portion 230 may be made of indium tin oxide (ITO) or indium zinc oxide (IZO), which are transparent conductive materials.

In addition, the second antistatic portion 230 may be formed to correspond to the outside of the common voltage line 140 connected to the common electrode 240. Accordingly, the static electricity may be prevented from being guided along the common voltage line 140 to the display area DA.

Meanwhile, second short points SP_2 are formed at both ends of the second peripheral area PA_2 to electrically connect the first antistatic unit 130 and the second antistatic unit 230. Here, the second short point SP_2 is formed outside the peripheral area PA than the first short point SP_1.

As such, the first antistatic unit 130 is electrically connected to the second antistatic unit 230 formed in the peripheral area PA of the opposing substrate 200, and the first and second ground pads 122a and 124a. ), The static electricity introduced from the outside of the display panel 600 may be discharged to the outside through the first and second ground pads 122a and 124a.

As described above, according to the present invention, the static electricity introduced from the outside can be induced to the ground by forming an antistatic portion outside the display area and connecting the ground. Accordingly, static electricity may be prevented from flowing into the display panel and the driving chip, and wiring defects, damage to the thin film transistor, and the like caused by the static electricity may be prevented.

Although described above with reference to the embodiments, those skilled in the art can be variously modified and changed within the scope of the invention without departing from the spirit and scope of the invention described in the claims below. I can understand.

Claims (11)

A base substrate including a display area in which a plurality of pixel portions are formed and a peripheral area surrounding the display area; A pad unit formed in the peripheral area and having a driving pad to which a driving signal is transmitted from the outside and a ground pad to which a ground signal is transmitted; And And an antistatic portion formed in the peripheral area and electrically connected to the ground pad to discharge static electricity to the outside. The array substrate of claim 1, wherein the antistatic part comprises a dummy metal pattern formed in the peripheral area, and a dummy wiring connecting the dummy metal pattern and the ground pad. The array substrate of claim 2, wherein the dummy metal pattern is formed at an edge of the array substrate. The array substrate of claim 1, wherein the antistatic part is formed in the peripheral area to surround the display area. A display panel comprising a display area and a peripheral area surrounding the display area, An array substrate having a pad portion formed in the peripheral region and having a ground pad, and a first antistatic portion formed in the peripheral region and electrically connected to the ground pad; Opposing substrate facing the array substrate: And And a liquid crystal layer interposed between the array substrate and the counter substrate. The display panel of claim 5, wherein the first antistatic portion is formed in the peripheral area to surround the outside of the display area. The display panel of claim 5, wherein the opposing substrate further comprises a second antistatic unit electrically connected to the first antistatic unit. The display panel of claim 7, wherein the first and second antistatic portions are electrically connected by a connecting member formed between the array substrate and the counter substrate. The display panel of claim 7, wherein the array substrate further comprises a common voltage line formed between the first antistatic portion and the display area. The display panel of claim 9, wherein the second antistatic portion is formed to correspond to an outer edge of the common voltage line. The method of claim 5, wherein the pad part includes a first connection pad part electrically connected to a driving chip and a second connection pad part electrically connected to a flexible circuit board. And the first antistatic portion is electrically connected to at least one of a first ground pad of the first connection pad portion and a second ground pad of the second connection pad portion.

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