KR20070016602A - Display apparatus - Google Patents

Abstract

A display device for preventing an electrostatic defect is disclosed. In the display substrate, a plurality of gate lines, a plurality of data lines, a plurality of pixel parts defined by the gate lines and the data lines, and lines for transmitting various signals are formed in the display area. The gate driver control signal line for transmitting a signal input from the outside into the non-display area to the gate driver includes a dummy switching element to protect from static electricity. Accordingly, the gate driver can be prevented from defects from static electricity.

Static, Dummy Switching Devices, Displays

Description

Display device {DISPLAY APPARATUS}

1 is a plan view of a display device according to an exemplary embodiment of the present invention.

FIG. 2 is a layout view of an external terminal unit for connecting with the flexible circuit film of FIG. 1.

3 is an enlarged plan view of a portion A and one pixel unit shown in FIG. 1.

4A through 4C are process diagrams for describing a method of manufacturing the display substrate illustrated in FIG. 3.

<Description of the symbols for the main parts of the drawings>

100: lower substrate 114a, 114b: gate driver control signal line

120: pixel portion 121: thin film transistor (TFT)

200: upper substrate 270: dummy switching element

274: data metal patterns 450 and 451: gate driver

The present invention relates to a display device, and more particularly, to a display device for preventing static electricity failure.

In general, a liquid crystal display device includes an array substrate on which switching elements are arrayed, an opposing substrate facing the array substrate, and a liquid crystal layer interposed between the substrates.

Recently, due to the application of new high-density technologies such as ASG (Amorphous Silicon Gate) and Chip On Glass (COG), an array of high-density metal patterns is used to increase static electricity defects. Typical antistatic measures applied to switching elements formed in the pixel portion of the array substrate are antistatic diodes and dummy switching elements.

The antistatic diode performs a function of distributing the static electricity flowing from one end of the lines to other lines, and the dummy switching element serves to protect the switching element by receiving the damage caused by the static electricity instead of the switching element of the pixel portion.

In general, since the antistatic diode is formed inside the driving portion of the gate and data of the array substrate, when the static electricity flows from the outside, the electrostatic defect cannot be prevented and the element of the driving portion cannot be protected. Accordingly, there is a need for a display device capable of suppressing an electrostatic defect even when an external signal is transmitted to a substrate.

An object of the present invention is to provide a display substrate to reduce the occurrence of static electricity failure due to an external signal.

Technical problems to be achieved by the present invention are not limited to the technical problems mentioned above, and other technical problems not mentioned will be clearly understood by those skilled in the art from the following description.

In accordance with another aspect of the present invention, a display device includes a first substrate, a second substrate coupled to the first substrate to accommodate a liquid crystal layer, and data lines and gate lines on the second substrate. A display unit for displaying an image, a gate driver connected to the gate lines to provide a gate signal to the gate lines, a data driver connected to the data lines to provide a data signal, and on the substrate A first pad part including a plurality of pads configured to receive an external signal, and electrically connecting the pad and the gate driver to the first pad part, and including a plurality of dummy switching elements. Include.

According to the display substrate and the display device having the same, it is possible to prevent static electricity from causing a defect in the driver circuit of the display device.

Specific details of other embodiments are included in the detailed description and the accompanying drawings.

Advantages and features of the present invention, and methods for achieving them will be apparent with reference to the embodiments described below in detail in conjunction with the accompanying drawings. However, the present invention is not limited to the embodiments disclosed below, but will be implemented in various forms, and only the present embodiments are intended to complete the disclosure of the present invention, and the general knowledge in the art to which the present invention pertains. It is provided to fully convey the scope of the invention to those skilled in the art, and the present invention is defined only by the scope of the claims. Like reference numerals refer to like elements throughout.

Hereinafter, with reference to the accompanying drawings, it will be described in detail the present invention.

1 is a plan view of a display device according to an exemplary embodiment of the present invention. FIG. 2 is a layout view of an external terminal unit for connecting with the flexible circuit film of FIG. 1. 3 is an enlarged plan view of a portion A and one pixel unit shown in FIG. 1.

Referring to FIG. 1, the liquid crystal display 700 according to the present invention integrates a dual gate driving circuit as an embodiment. The liquid crystal display device includes a lower substrate 100 and an upper substrate 200.

The lower substrate 100 is divided into a first region 100a on which the upper substrate 200 is superimposed and a second region 100b not superimposed.

The first region 100a includes a display region 104 and a non-display region 106 surrounding the display region 104, and after the liquid crystal is injected into the display region 104, the peripheral portion thereof is sealed with a sealing material. . In the left and right non-display areas 106 of the display area 104, first and second gate driving circuits 450 and 451 which receive a gate signal and output a gate signal are disposed. The gate drivers 450 and 451 are formed together in the same process as the process of forming the thin film switching element 121.

However, the gate drivers 450 and 451 may be embedded in the driving chip 400 or may be formed as a separate chip and mounted in the non-display area 106 of the lower substrate 100.

When the gate drivers 450 and 451 are embedded in the driving chip 400 of the data driver, the driving chip 400 of the data driver outputs a gate signal to the gate lines GL.

The data driver and the external connection terminal 114 are formed in the second region 100b, and one end of the flexible circuit film 500 is attached to the external connector 114. The data driver is manufactured in a chip shape and mounted on the lower substrate 100.

 The other end of the flexible circuit film 500 is attached to an integrated printed circuit board (not shown). The flexible circuit film 500 is electrically connected to the driving chip 400 of the data driver to provide a control signal for controlling the data driver to the data driver chip 400. In addition, a signal for controlling the gate drivers 450 and 451 is provided to the gate drivers 450 and 451.

 The flexible circuit film 500 may include a timing controller for adjusting the timing of the control signal, a memory for storing the data signal, and the like.

1 and 3, the lower substrate 100 includes data lines DL electrically connected to the data driving chip 400, gate lines GL electrically connected to the gate drivers 450 and 451, and Thin Film Transistor (TFT) 121 connected to the data line DL and the gate line GL, a gate insulating film (not shown), a protective film (not shown) and a thin film transistor 121 provided on the gate insulating film. A pixel electrode 286 electrically connected to the pixel electrode 286 is formed.

The display area 104 includes data lines DL extending in the D1 direction, gate lines GL, data lines DL, and the gate lines GL extending in the D2 direction crossing the D1 direction. A plurality of pixel units 120 defined by the plurality are formed.

The data lines DL receive a data signal from the driving chip 400 and transmit the data signal to the display area 104. The gate lines GL receive gate signals from the gate drivers 450 and 451 and transmit gate signals to the display area 104.

Each pixel unit 120 includes a thin film transistor 121, a liquid crystal capacitor CLC, and a storage capacitor CST. The common voltage is applied to the storage voltage line (not shown) and transferred to the storage capacitor CST formed in each pixel unit 120.

The thin film transistor 121 is provided in the display region 104 and operates as a switch element. The thin film transistor 121 is connected to the gate line GL and the data line DL to apply or block a signal voltage to the pixel electrode 286. The lower substrate 100 includes a plurality of thin film transistors 121, and the thin film transistors 121 are provided for each pixel area defined by the gate lines GL and the data lines DL.

A light blocking pattern (not shown), a color filter pattern (not shown), and a common electrode layer (not shown) are formed on the upper substrate 200.

The light blocking pattern is formed to correspond to the display area 104 and the non-display area 106 of the lower substrate 100 to block leakage light, and to form internal spaces corresponding to the pixel parts 120 of the display area 104. define. The color filter pattern is formed in the internal spaces defined by the light shielding pattern to express transmitted light in a unique color. The common electrode layer is a counter electrode corresponding to the pixel electrode 286 of the lower substrate 100 and is a common electrode of the liquid crystal capacitor CLC defined in the pixel unit 120.

The liquid crystal layer (not shown) is interposed between the lower substrate 100 and the upper substrate 200. The arrangement angle of the liquid crystal layer is changed by a potential difference between the pixel electrode 286 and the common electrode layer, and an image is displayed using the same.

The non-display area 106 includes diodes dispersing static electricity flowing from the gate pad (not shown) and the data pad part (not shown) during the manufacturing process of the liquid crystal display device 700. Therefore, by preventing the static electricity flowing into the display area 104 by the diode of the electrostatic dispersion it is possible to reduce the loss due to the electrostatic failure. The electrostatic diode may be connected to a storage voltage line (not shown).

In an exemplary embodiment of the present invention, part “A” of FIG. 1 is a gate driver control signal line through which an external signal is transmitted to the gate drivers 450 and 451. The gate driver control signal line includes a start signal input terminal ST signal line, a clock signal input terminal CK signal line, a first power supply voltage terminal VOFF or VSS signal line, and a second power supply voltage terminal VON or VDD signal line. When static electricity flows into the gate driver control signal line, it may flow into the circuits of the gate drivers 450 and 451 to cause a defect. Therefore, the start signal input terminal (ST) signal line, the clock signal input terminal (CK) signal line, the first power voltage terminal (VOFF or VSS) signal line, and the second power voltage terminal to protect the circuits of the gate drivers 450 and 451. The (VON or VDD) signal line includes a dummy switching element. That is, a dummy antistatic switching element is formed in the “A” portion formed in the non-display area 106 so as to reduce defects caused by static electricity.

That is, since the dummy antistatic switching device is first damaged by static electricity generated outside, damage to the gate drivers 450 and 451 may be prevented.

The structures of the gate driver control signal line and the dummy switching element of the portion "A" will be described later in detail.

As shown in FIG. 2, the start signal input terminal ST, the first clock signal input terminal CK, the first power supply voltage terminal VOFF or VSS, and the second power supply voltage terminal of the external connection terminal 114 ( Four terminals 114a of the VON or VDD are connected to the first gate circuit and include a second clock signal input terminal CKB, a first power voltage terminal VOFF or VSS, and a second power voltage terminal VON or VDD. The three terminals 114b of VDD are coupled to the second gate circuit. The channel terminals 114c of the external connection terminal 114 are connected to the driving chip 400 of the data driver.

Referring to FIGS. 1 and 3 again, the pixel unit 120 may be electrically connected to the data line DL and the gate line GL through the thin film transistor 121, the thin film transistor 121, and the contact hole 285. Connected pixel electrodes 286 are formed. The thin film transistor 121 includes a gate electrode 281 connected to the gate line GL, a source electrode 283 connected to the data line DL, and a drain electrode 284 connected to the pixel electrode. An active layer 282 interposed between the 281 and the data / drain electrodes 283 and 284.

In addition, the portion labeled "A" in FIG. 1 is enlarged to the portion "A" in FIG. 3 to show a detailed structure. That is, the "A" portion represents the CK signal line, the VDD signal line, the VSS signal line, and the ST signal line, which are the gate driver control signal lines that transmit external signals to the gate drivers 450 and 451, and the data lines DL and the gate line GL. ) And dummy thin film switching elements 270 formed simultaneously when the gate electrode lines GL are formed. The dummy thin film switching element 270 is formed on the CK signal line, the VDD signal line, the VSS signal line, and the ST signal line, respectively, and includes a plurality of diodes.

Each dummy switching element 270 faces the gate electrode 271 connected to the gate line GL, the active layer 272, and the data electrode 273 and the data electrode 273 connected to the data line DL. And a drain electrode 274 defining a channel region. The dummy switching element 270 defines a predetermined capacitance by the gate electrode 273 and the drain electrode 274.

The dummy switching elements 270 are separated into a plurality of groups by the drain electrodes 274, and each group of the dummy switching elements 270 has a random capacitance by the drain electrode 274. That is, each of the drain electrodes 274 of the dummy switching elements 270 is integrally formed by the first data metal pattern 274a and grouped into a first group.

The drain electrodes 274 of the other dummy switching devices 270 are integrally formed by the second data metal pattern 274b and grouped into a second group.

Each of the drain electrodes 274 of the other dummy switching elements 270 is integrally formed by the third data metal pattern 274c and grouped into a third group.

The drain electrode 274 of another dummy switching element 270 is grouped into a fourth group by the fourth data metal pattern 274d.

The capacitances of the first to fourth groups correspond to the sizes of the first to fourth data metal patterns 247a, 247b, 247c, and 247d.

Instead of forming the drain electrodes 270 of the dummy switching elements 270 into a single data metal pattern, the drain electrodes 270 are separately formed into data metal patterns 247a, 247b, 247c, and 247d of various sizes. It is possible to prevent the circuits of the gate drivers 450 and 451 from being damaged by the static electricity flowing from the same. The first group of dummy switching elements in which the drain electrodes 270 are integrally formed by the first data metal pattern 274a is damaged by the first static electricity having a relatively large voltage, and is caused by the second data metal pattern 274b. The second group of dummy switching elements in which the drain electrodes 270 are integrally formed are damaged by a second static electricity smaller than the first static electricity. In addition, the fourth group of dummy switching elements in which the drain electrode 270 is formed by the fourth data metal pattern 274d is damaged by a third static electricity smaller than the second static electricity. Therefore, the circuits of the gate drivers 450 and 451 may be protected through various sizes of static electricity and various paths.

4A through 4C are process diagrams for describing a method of manufacturing the display substrate illustrated in FIG. 3.

1 to 3 and 4A, a gate metal layer is formed on the lower substrate 100, and gate metal patterns are formed through a photo process. The gate metal patterns include the gate lines GL, the dummy electrodes 270 connected to the gate electrodes 281 of the pixel portion 120 thin film transistors 121 connected to the gate line GL, and the gate line GL. Gate electrodes 271 are included.

Subsequently, a gate insulating layer (not shown) is formed on the gate metal patterns. The gate insulating layer is formed of an insulating material such as silicon nitride and silicon oxide.

1 to 3 and 4B, active layers 272 and 282 are formed on the gate insulating layer. Specifically, an amorphous silicon film and an n ⁺ amorphous silicon film doped in-situ are sequentially deposited on the gate insulating layer by a plasma chemical vapor deposition method. The stacked amorphous silicon film and the n ⁺ amorphous silicon film are patterned to form an active layer 282 of the thin film transistors 121 of the pixel unit 120 and an active layer 272 of the dummy switching elements 270.

1 to 3 and 4C, a data metal layer is formed on the active layers 272 and 282, and data metal patterns are formed through a photo process. That is, data lines DL, CK signal lines, VDD signal lines, VSS signal lines, and ST signal lines are simultaneously formed.

The data metal patterns include the data line DL, the CK signal line, the VDD signal line, the VSS signal line, the ST signal lines, the data electrodes 273 and the drain electrodes 274 of the dummy switching elements 270, and the thin film of the pixel portion 120. Data electrodes 283 and transistors 284 of the transistors. Drain electrodes 274 of the dummy switching elements 270 are formed by separating data metal patterns of different sizes.

In detail, each of the drain electrodes 274 of the first group of dummy switching elements 270 is integrally formed by the first data metal pattern 274a having the first size.

Each of the drain electrodes 274 of the second group of dummy switching elements 270 is integrally formed by a second data metal pattern 274b having a second size smaller than the first size.

Each of the drain electrodes 274 of the third group of dummy switching elements 270 is integrally formed by a third data metal pattern 274c having a second size.

The drain electrode 274 of the fourth group of dummy switching elements 270 is formed by the fourth data metal pattern 274d having a third size smaller than the second size.

As described above, the drain electrodes 274 of the dummy switching elements 270 are not integrally formed in one data metal pattern on the CK signal line, the VDD signal line, the VSS signal line, and the ST signal lines, and data metal patterns having different sizes are formed. As it is formed separately, the damage of the gate drivers 450 and 451 may be prevented from static electricity of various capacities.

1 to 3, a protective layer (not shown) is formed on the data metal patterns. Subsequently, a portion of the protective layer is removed to form the contact hole 285.

The pixel electrode layer 286 is formed on the passivation layer on which the contact hole 285 is formed. The pixel electrode layer 286 is a transparent conductive material, and may be indium-tin-oxide (ITO), indium-zinc-oxide (IZO), or indium-tin-zinc oxide (Indium- Tin-Zinc-Oxide). The pixel electrode layer 286 is patterned through a photo process to form the pixel electrode 286 in the pixel portion 120.

As can be seen from the above description, dummy switching is performed on the start signal (ST) signal line, the clock signal (CK) signal line, the first power supply voltage (VOFF or VSS) signal line, and the second power supply voltage (VON or VDD) signal line connected to an external terminal. By forming the devices 270, the static electricity flowing from the outside may be blocked to prevent damage to the gate drivers 450 and 451 or other circuit parts.

In addition, by randomly configuring the capacitance by setting the dummy switching element 270 for preventing static electricity in various sizes, it is possible to effectively reduce the electrostatic failure.

As described above, according to the present invention, a failure of the electrostatic discharge can be prevented by forming a dummy switching element on the gate driver control signal line that transmits an external signal to the circuit portion of the display device.

Claims (7)

A first substrate; A second substrate coupled to the first substrate to receive a liquid crystal layer; A display unit including a plurality of pixels defined by data lines and gate lines on the second substrate and displaying an image; A gate driver connected to the gate lines to provide a gate signal to the gate lines; A data driver connected to the data lines to provide a data signal; A first pad part provided on the substrate and including a plurality of pads for receiving an external signal; And And a gate driver control signal line electrically connecting the pad and the gate driver to the first pad part and including a plurality of dummy switching elements. According to claim 1, The data driver is electrically connected to a second pad part including a plurality of pads connected to the data line, and receives a data control signal applied through the first pad part and outputs a data driving signal through an output terminal. Display device comprising a. The method of claim 2, And the external signal is input to the first pad portion and / or the second pad portion through a flexible circuit film. According to claim 1, The dummy switching device includes a diode. The method of claim 4, wherein The diode is formed in two or more parts. According to claim 1, The dummy switching element includes a gate electrode connected to the gate line, a data electrode connected to the data line, and a drain electrode defining a channel region facing the data electrode. The method of claim 6, And the gate electrode and the drain electrode of the switching element define capacitance.

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