KR20080018773A - Liquid crystal display device - Google Patents

Abstract

A liquid crystal display device is provided to form resistance parts between gate lines and gate pads to delay gate signals before entering a display area to reduce a delay change range of the gate signals and a kickback voltage change range, thereby improving brightness uniformity. A liquid crystal display device includes a first substrate having a display area, a second substrate opposite to the first substrate, and a liquid crystal layer interposed between the first substrate and the second substrate. The first substrate includes gate lines(121) placed in the display area, gate pads(124) placed outside the display area, and resistance parts(163) electrically connecting the gate lines with the gate pads, made of a material having resistance higher than resistance of the gate lines.

Description

Liquid crystal display {LIQUID CRYSTAL DISPLAY DEVICE}

1 is a layout view of a first substrate in a liquid crystal display according to a first embodiment of the present invention;

FIG. 2 is an enlarged view of portion A of FIG. 1,

3 is a cross-sectional view taken along line III-III of FIG. 2,

4 is a view showing transmittance according to pixel voltage in the liquid crystal display according to the first embodiment of the present invention.

5 is an equivalent circuit diagram of a pixel in a liquid crystal display according to a first embodiment of the present invention;

6A to 6C are diagrams for describing luminance unevenness according to a gate signal delay.

7 is an enlarged view of a portion B of FIG. 1,

8 is a cross-sectional view taken along the line VIII-VIII of FIG. 7,

9 is a view for explaining the luminance non-uniformity improvement in the liquid crystal display device according to the first embodiment of the present invention,

10 is a diagram illustrating a relationship between a gate signal delay and luminance.

11 is a view showing a change between parasitic capacitance and luminance,

12 is a diagram illustrating a gate signal delay according to a resistance value of a resistor unit;

13 is a diagram illustrating pixel voltages according to resistance values of a resistor unit;

14 is a view for explaining a liquid crystal display device according to a second embodiment of the present invention;

15 is a cross-sectional view taken along the line VV-VV of FIG. 14,

16 is an equivalent circuit diagram of a pixel in a liquid crystal display according to a third exemplary embodiment of the present invention.

17 illustrates a principle of improving visibility in a liquid crystal display according to a third exemplary embodiment of the present invention.

18 is a layout view of a liquid crystal display according to a third embodiment of the present invention;

19 is a layout view of a liquid crystal display according to a fourth exemplary embodiment of the present invention.

Explanation of Signs of Major Parts of Drawings

121: gate line 122: gate electrode

123: fan-out 124: gate pad

131: gate insulating film 151: protective film

161: pixel electrode 166: pixel electrode incision pattern

163: resistor 200: second substrate

251: common electrode 252: common electrode incision pattern

300: sealant

The present invention relates to a liquid crystal display device, and more particularly, to a liquid crystal display device having improved luminance uniformity by reducing a gate signal delay difference.

The liquid crystal display device includes a first substrate on which a thin film transistor is formed, a second substrate disposed opposite to the first substrate, and a liquid crystal layer disposed therebetween.

The gate line and the data line provided on the thin film transistor substrate cross each other to form pixels, and each pixel is connected to the thin film transistor. When the gate signal (gate on voltage Von) is applied to the gate line and the thin film transistor is turned on, the data voltage Vd applied through the data line is charged in the pixel.

The arrangement state of the liquid crystal layer is determined according to the electric field formed between the pixel voltage Vp charged in the pixel and the common voltage Vcom formed on the common electrode of the second substrate. The data voltage Vd is applied with different polarities for each frame.

The data voltage Vd applied to the pixel is dropped by the parasitic capacitance Cp between the gate electrode and the source electrode (drain electrode) to form the pixel voltage Vp. The voltage difference between the data voltage Vd and the pixel voltage Vp is called a kickback voltage Vkb.

The gate line receives a gate signal through a gate pad connected to an end of the gate line. A gate signal having a low delay is applied to a pixel adjacent to the gate pad, and a gate signal having a large delay due to the resistance of the gate line is applied to a pixel far from the gate pad.

However, the magnitude of the kickback voltage varies according to the delay level of the gate signal, and the luminance of the screen becomes uneven due to the change of the pixel voltage due to the change of the kickback voltage.

Accordingly, an object of the present invention is to provide a liquid crystal display device in which luminance unevenness due to a difference in gate signal delay is reduced.

An object of the present invention is to provide a liquid crystal display device comprising a first substrate having a display area, a second substrate facing the first substrate, and a liquid crystal layer positioned between the first substrate and the second substrate. The first substrate may include a gate main line positioned in the display area; A gate pad positioned outside the display area; It is achieved by electrically connecting the gate main line and the gate pad and including a resistor part made of a material having a higher resistance than the gate main line.

The first substrate may include a thin film transistor connected to the gate main line; The pixel electrode may further include a pixel electrode electrically connected to the thin film transistor.

Preferably, the resistor unit is made of the same material as the pixel electrode.

The resistance unit preferably includes indium tin oxide (ITO) or indium zinc oxide (IZO).

Preferably, the resistance unit is provided with a smaller resistance value as the distance between the gate main line connecting the gate pad and the gate pad is increased.

The apparatus may further include a fan-out part disposed between the gate pad and the resistor part.

Preferably, the gate main line, the gate pad, and the fan-out portion are formed of the same layer.

It is preferable to further include a sealant which is formed on the fan-out part and which couples the first substrate and the second substrate.

The apparatus may further include a fan-out part disposed between the gate pad and the resistor part.

Preferably, the gate pad, the fan-out part and the resistor part are made of the same layer.

At least a part of the resistance portion is preferably formed in a zigzag.

The liquid crystal layer is preferably in VA (vertical alignment) mode.

The pixel electrode may include a pixel electrode cutting pattern, and the second substrate may include a common electrode on which a common electrode cutting pattern is formed.

The pixel electrode includes a first pixel electrode and a second pixel electrode which are separated from each other, and different pixel voltages are applied to the first pixel electrode and the second pixel electrode.

The thin film transistor includes a drain electrode, and the drain electrode includes a first drain electrode applying a data voltage directly to the first pixel electrode and a second drain electrode forming a coupling capacitance with the second pixel electrode. desirable.

The thin film transistor may include a first thin film transistor connected to the first pixel electrode and a second thin film transistor connected to the second pixel electrode.

The total resistance of the resistor unit is preferably 10% to 50% of the total resistance of the gate main line.

The change in the gate signal delay of the gate main line is preferably within 100%.

An object of the present invention is to provide a liquid crystal display comprising a first substrate having a display area, a second substrate facing the first substrate, and a liquid crystal layer positioned between the first substrate and the second substrate. The first substrate may include: a gate main line positioned in the display area; A gate pad positioned outside the display area; A resistor unit electrically connecting the gate main line and the gate pad and having a resistance higher than that of the gate main line; A thin film transistor connected to the gate main line; And a pixel electrode electrically connected to the thin film transistor and made of the same material as the resistor, wherein the liquid crystal layer is also in VA mode.

An object of the present invention is to provide a substrate having a display area and a non-display area, a gate main line located in the display area; A gate pad positioned outside the display area; A resistor unit electrically connecting the gate main line to the gate pad and having a resistance higher than that of the gate main line; A thin film transistor connected to the gate main line; It is also achieved by a liquid crystal display including a thin film transistor array substrate electrically connected to the thin film transistor and including a pixel electrode made of the same material as the resistor.

Hereinafter, the present invention will be described in more detail with reference to the accompanying drawings. In the following, a film is formed (located) on top of another film, not only when two films are in contact with each other but also when another film is between two layers. It also includes the case where it exists.

A liquid crystal display according to the present invention will be described with reference to FIGS. 1 to 3.

The liquid crystal display device 1 is positioned between the first substrate 100 on which the thin film transistor T is formed, the second substrate 200 facing the first substrate 100, and both substrates 100 and 200. And a sealant 400 for bonding the liquid crystal layer 300 and both substrates 100 and 200.

The first substrate 100 is divided into a display area and a non-display area surrounding the display area. The gate line 121 of the display area is connected to the gate pad 124 through the fan-out part 123 of the non-display area.

First, the first substrate 100 will be described.

Gate wiring is formed on the first insulating substrate 111. The gate wiring can be a metal single layer or multiple layers. The gate wiring is located in the display area and extends in the horizontal direction to the gate main line 121, the gate electrode 122 connected to the gate main line 121, and the fan-out extending from the gate main line 121 to the non-display area. The gate pad 124 connected to the end of the unit 123, the fan-out unit 123, and the storage electrode line 125 extending in parallel with the gate line 121 are included.

The gate pad 124 is connected to a gate driver (not shown) to receive a gate signal. The gate pad 124 is larger in width than the gate main line 121.

On the first insulating substrate 111, a gate insulating layer 131 made of silicon nitride (SiNx) or the like covers the gate wiring.

A semiconductor layer 132 made of a semiconductor such as amorphous silicon is formed on the gate insulating layer 131 of the gate electrode 122, and n + is doped with silicide or n-type impurities at a high concentration on the semiconductor layer 132. An ohmic contact layer 133 made of a material such as hydrogenated amorphous silicon is formed. The ohmic contact layer 133 is removed from the channel portion between the source electrode 142 and the drain electrode 143.

The data line is formed on the ohmic contact layer 133 and the gate insulating layer 131. The data line may also be a single layer or multiple layers of a metal layer. The data line is a branch of the data line 141 and the data line 141 which are formed in the vertical direction and intersect the gate line 121 to form a pixel, and extends to the upper portion of the ohmic contact layer 133. ) And a fan-out separated from the source electrode 142 and extending from the data line 141 to the non-display area of the drain electrode 143 and the data line 141 formed on the resistive contact layer 133 opposite to the source electrode 142. And a data pad 145 connected to the end of the portion 144 and the fan-out portion 144.

The data pad 145 is connected to a data driver (not shown) and receives a data driving signal. The data pad 145 is larger in width than the data main line 141.

The passivation layer 151 is formed on the data line and the semiconductor layer 132 that does not cover the data line. A contact hole 152 exposing the drain electrode 143 is formed in the passivation layer 151. 7 and 8, contact holes 153, 154, and 155 are further formed in the passivation layer 151, and the gate insulating layer 131 is also removed therein.

The pixel electrode 161 is formed on the passivation layer 151. The pixel electrode 161 is usually made of a transparent conductive material such as indium tin oxide (ITO) or indium zinc oxide (IZO). The pixel electrode 161 is connected to the drain electrode 143 through the contact hole 152. The pixel electrode cut pattern 166 is formed on the pixel electrode 161.

The pixel electrode cutout pattern 166 of the pixel electrode 161 divides the liquid crystal layer 300 into a plurality of regions together with the common electrode cutout pattern 252 described later.

Next, the second substrate 200 will be described.

The black matrix 221 is formed on the second insulating substrate 211. The black matrix 221 generally distinguishes between red, green, and blue filters, and serves to block direct light irradiation to the thin film transistor positioned on the first substrate 100. The black matrix 221 is usually made of a photosensitive organic material to which black pigment is added. As the black pigment, carbon black or titanium oxide is used.

The color filter 231 is formed by repeating the red, green, and blue filters with the black matrix 221 as the boundary. The color filter 231 serves to impart color to light emitted from the backlight unit (not shown) and passed through the liquid crystal layer 300. The color filter 231 is usually made of a photosensitive organic material.

An overcoat layer 241 is formed on the black matrix 221 not covered by the color filter 231 and the color filter 231. The overcoat layer 241 serves to protect the color filter 231 while planarizing the color filter 231. The overcoat layer 241 may be a photosensitive acrylic resin.

The common electrode 251 is formed on the overcoat layer 241. The common electrode 251 is made of a transparent conductive material such as indium tin oxide (ITO) or indium zinc oxide (IZO). The common electrode 251 directly applies a voltage to the liquid crystal layer 300 together with the pixel electrode 161 of the thin film transistor substrate.

The common electrode cutting pattern 252 is formed on the common electrode 251. The common electrode cutout pattern 252 divides the liquid crystal layer 300 into a plurality of regions together with the pixel electrode cutout pattern 166 of the pixel electrode 161. The pixel electrode cut pattern 166 and the common electrode cut pattern 252 may be formed in various shapes without being limited to the exemplary embodiments. In another embodiment, a protrusion may be provided instead of the cutting patterns 166 and 252 to divide the liquid crystal layer 300 into a plurality of regions.

The liquid crystal layer 300 is positioned between the first substrate 100 and the second substrate 200. The liquid crystal layer 300 is a VA (vertically aligned) mode, and the liquid crystal molecules are vertical in the length direction when no voltage is applied. When voltage is applied, the liquid crystal molecules lie perpendicular to the electric field because the dielectric anisotropy is negative.

However, when the incision patterns 166 and 252 are not formed, the liquid crystal molecules are arranged in a random order in various directions because the azimuth angles of the lying are not determined, and a foreground line is formed at the boundary planes having different alignment directions. The cutting patterns 166 and 252 form a fringe field when a voltage is applied to the liquid crystal layer 300 to determine the azimuth angle of the liquid crystal alignment. In addition, the liquid crystal layer 300 is divided into multiple regions according to the arrangement of the cutting patterns 166 and 252.

The liquid crystal display device 1 according to the first embodiment is a normally black mode, and the transmittance according to the pixel voltage is shown in FIG. 4. The change in transmittance at low gradation shown in part C of FIG. 4 is about three times faster than that of TN (twisted nematic) liquid crystal.

In the liquid crystal display device 1 described above, the gate main line 121 receives a gate signal through a gate pad 124 connected to an end thereof. The gate signal having a low delay is applied to the thin film transistor T adjacent to the gate pad 124, that is, the thin film transistor T on the left side by the resistance of the gate main line 121. On the other hand, a gate signal with a large delay is applied to the thin film transistor T far from the gate pad 123, that is, the thin film transistor T on the right side.

The change in the screen brightness according to the difference in the gate signal delay will be described with reference to FIGS. 5 to 6C.

The kickback voltage Vkb is expressed by Equation 1 as follows.

Equation 1

Vkb = (Von-Voff) * Cp / (Clc + Cst + Cp)

3 and 5, Cp is the parasitic capacitance (Cgs) between the gate electrode and the source electrode + parasitic capacitance (Cgd) between the gate electrode and the drain electrode, Clc is the liquid crystal capacitance, Cst is the storage capacitance, Von is the gate-on voltage , Voff represents the gate off voltage.

If the gate signal delay is large, the gate-on voltage is poorly applied and the kickback voltage is decreased, and the kickback voltage is larger when the negative pixel voltage is applied than when the positive pixel voltage is applied.

6A and 6B illustrate kickback voltages for pixels on the left of the display area having a small delay of the gate signal and pixels on the right of the display area having a large delay of the gate signal, respectively.

In the case of the left pixel illustrated in FIG. 6A, the kickback voltage is 1V when the positive pixel voltage is applied, and the kickback voltage is 1.2V when the negative pixel voltage is applied. In the case of the right pixel shown in Fig. 8B, the kickback voltage is 0.8V both when the positive pixel voltage is applied and when the negative pixel voltage is applied.

Accordingly, the root mean square pixel voltage at which the left pixel is finally left in the pixel becomes larger, and the screen corresponding to the left pixel is more brightly recognized.

Referring to FIG. 6C, the closer to the gate pad 124, the smaller the gate signal delay and the larger the kickback voltage Vkb. On the other hand, the further away from the gate pad 124, the greater the gate signal delay and the smaller the kickback voltage Vkb. Therefore, the left pixel is brighter because the root mean square pixel voltage is larger than that of the right pixel.

As described above, the brightness of the left and right sides of the screen is changed, and thus a horizontal line is recognized. This problem is further exacerbated in a large liquid crystal display device in which the gate main line 121 is long and a large gate signal delay occurs.

In the first embodiment of the present invention, the problem caused by the gate delay difference is solved by forming the resistor unit 163 between the gate main line 121 and the gate pad 124.

The resistor unit 163 will be described with reference to FIGS. 7 to 9.

The resistor unit 163 is positioned between the fan-out unit 123 and the gate main line 121 in the non-display area. The resistor unit 163 is formed of the same layer as the pixel electrode 161, and includes a first part 163a connected to the fan-out part 123, a second part 163b connected to the gate main line 121, and A third portion 163c positioned between the first portion 163a and the second portion 163b.

The first portion 163a contacts the fan-out portion 123 through the contact hole 154, and the second portion 163b contacts the gate main line 121 through the contact hole 155.

The gate pad 124 exposed by the contact hole 153 is covered by a contact member 162 made of the same layer as the pixel electrode 161.

The resistor unit 163 is made of ITO, IZO, or the like, and these materials have a higher resistance than the metal materials forming the gate main line 121. Due to the resistance 163 having a large resistance, a delay is already generated as shown in FIG. 9 before the gate signal enters the display area.

Therefore, the delay variation of the gate signal and the variation of the kickback voltage Vkb decrease. In addition, the luminance difference on the left and right of the display area is also reduced.

The total resistance of the gate main line 121 is typically 4000 Ω to 7000 Ω, and the total resistance of the resistor unit 163 may be 10% to 50% of the total resistance of the gate main line 121. The resistance value of the resistor unit 163 may be changed by adjusting the thickness, width, and length of the resistor unit 163.

The resistance value of the resistor unit 163 is preferably determined so that the change in the gate delay is within 100%, that is, the gate delay value of the rightmost pixel of the display area is less than twice the gate delay value of the leftmost pixel of the display area. Do.

On the other hand, the distance between the gate main line 121 and the gate pad 124 varies, which causes a problem in that the luminance is changed due to a change in resistance between the gate main line 121 and the gate pad 124.

The length of the third portion 163c of the resistor unit 163 is provided in inverse proportion to the distance between the corresponding gate main line 121 and the gate pad 124. As a result, unevenness in luminance due to the difference in distance between the gate main line 121 and the gate pad 124 is reduced.

The sealant 400 is located on the fan-out part 123, and the resistor part 163 is located in the sealant 400. Since the resistor unit 163 is not exposed to the outside, the problem of corrosion of the resistor unit 163 does not occur.

In the manufacturing process, the static electricity flowing from the outside may cause a problem of damaging the thin film transistor (T). According to the first embodiment, the static electricity introduced through the gate pad 124 may be dissipated to some extent in the resistor 163 having a large resistance, thereby reducing the problem caused by static electricity.

In another embodiment, the resistor unit 163 may be formed of another material having a higher resistance than the gate main line 121, separately from the pixel electrode 161. In another embodiment, the shape of the resistor unit 163 is the same, and the distance difference between the gate main line 121 and the gate pad 124 may be solved by changing the shape of the fan-out unit 123.

Hereinafter, the reason why the gate signal delay is adjusted to adjust the luminance nonuniformity will be described.

10 illustrates a luminance deviation rate according to a gate signal delay value in the display area. The luminance deviation ratio is (luminance at the left of the display area-luminance at the center of the display area) / luminance * 100 at the center of the display area, where a large value indicates that the luminance difference is large.

10, when the gate signal delay increases by about 43% (2.55 GHz to 3.67 GHz), the luminance deviation increases by about 64% (30.6% to 50.3%).

FIG. 11 shows the luminance deviation ratio according to Cp / (Clc + Cst + Cp) proportional to the kickback voltage. 11, when Cp / (Clc + Cst + Cp) increases by 24% (0.037 to 0.046), the luminance deviation increases by about 26.4% (35.6% to 45%).

10 and 11, it can be seen that it is effective to adjust the gate signal delay value in order to improve luminance unevenness.

The gate signal delay and the pixel voltage are changed by the resistance in the non-display area, that is, the resistance from the gate pad to the main line, which will be described with reference to FIGS. 12 and 13.

12 and 13, the resistance in the non-display area has four values of 1/6 kΩ, 1/3 kΩ, 1/2 kΩ, and 2/3 kΩ. The data indicated by 0 kΩ is a case where no resistance portion exists and the gate main line and the gate pad are integrally formed.

12, it can be seen that as the resistance of the non-display area increases, the gate signal delay value increases as a whole. On the other hand, as the non-display area resistance increases, the right gate signal delay value / left gate signal delay value decreases.

That is, in the case of 0 kΩ, the right gate signal delay value / left gate signal delay value is 6.53 (4.18 / 0.64), whereas in the case of 2/3 kΩ, the right gate signal delay value / left gate signal delay value is 1.77 (8.12 / 4.57).

13, it can be seen that as the non-display area resistance increases, the pixel voltage as a whole decreases. On the other hand, as the resistance of the resistor increases, the left pixel voltage / right pixel voltage decreases. That is, in the case of 0 kΩ, the left pixel voltage / right pixel voltage is 1.028 (3.3 / 3.21), whereas in the case of 2/3 kΩ, the left pixel voltage / right pixel voltage is 1.012 (3.19 / 3.15).

12 and 13, it can be seen that increasing the non-display area resistance can reduce the gate signal delay and the difference in the left and right display areas of the pixel voltage. However, since the gate signal transmission becomes difficult when the non-display area resistance increases, the non-display area resistance should be determined in consideration of the total resistance of the gate main line 121 and the like.

Hereinafter, a second embodiment will be described with reference to FIGS. 14 and 15.

According to the second embodiment, the gate pad 164 and the fan-out part 165 are integrally formed with the resistor part 163 and are made of ITO or IZO. The resistor unit 163 is connected to the gate main line 121 and the contact hole 156. In the second embodiment, the gate pad 164 and the fan-out part 165 also function as the resistor part 163 of the first embodiment.

As in the first embodiment, the resistor unit 163 is provided to be inversely proportional to the distance between the corresponding gate main line 121 and the gate pad 164. As a result, unevenness in luminance due to the difference in distance between the gate main line 121 and the gate pad 164 is reduced.

In another embodiment, the fan-out unit 165 may be made of ITO or IZO without the resistor unit 163 to delay the gate signal.

A third embodiment will be described with reference to FIGS. 16 to 18.

Referring to FIG. 16, two liquid crystal capacitors C _LC1 and C _LC2 are connected to the thin film transistor T. The first liquid crystal capacitor C _{LC1 is} formed between the first pixel electrode PE1 and the common electrode CE, and the first pixel electrode PE1 is directly connected to the thin film transistor T. The second liquid crystal capacitor C _{LC2 is} formed between the second pixel electrode PE2 and the common electrode CE, and the second pixel electrode PE2 is indirectly through the thin film transistor T through the coupling capacitor C _CP . Connected with

Here, the first pixel electrode PE1 and the second pixel electrode PE2 are separated from each other.

According to the third embodiment, visibility is improved, which will be described with reference to FIG. 17.

The data signal is normally applied to the first pixel electrode PE1 through the thin film transistor T. On the other hand, the second pixel electrode PE2 does not receive a data signal directly from the thin film transistor T and is a coupling capacitance C _CP generated by an insulating film between the second pixel electrode PE2 and the thin film transistor T. The signal is applied by the induced voltage.

Therefore, a weaker signal is applied to the second pixel electrode PE2 than the first pixel electrode PE1, and thus, luminance of the pixel area corresponding to the first pixel electrode PE1 and corresponding to the second pixel electrode PE2 are applied. The luminance of the pixel region is different. The voltage applied to the second pixel electrode PE2 is 50% to 90% of the voltage applied to the first pixel electrode PE1.

As described above, a plurality of regions having different gamma curves exist in one pixel. As a result, the front and side luminance and color are compensated for each other, thereby improving side visibility.

Referring to FIG. 18, the pixel electrode 161 includes a first pixel electrode 161a and a second pixel electrode 161b separated from each other by the pixel electrode isolation pattern 167. The second pixel electrode 161b is trapezoidal and three surfaces thereof are surrounded by the first pixel electrode 161a. The pixel electrode cutout pattern 166 parallel to the pixel electrode isolation pattern 167 is formed on the first pixel electrode 161a and the second pixel electrode 161b, respectively.

The drain electrode 143 is connected to the first pixel electrode 161a and extends below the first drain electrode 143a and the second pixel electrode 161b for directly applying an electrical signal to the first pixel electrode 161a. The second drain electrode 143b is included. The second drain electrode 143b forms a coupling capacitor Ccp together with the second pixel electrode 161b.

The pixel electrode separation pattern 167 and the pixel electrode cutting pattern 166, along with the common electrode cutting pattern 252, divide the liquid crystal layer 300 into a plurality of regions.

On the other hand, the sustain electrode line 125 is formed along the circumference of the pixel electrode 161, and the upper and lower sustain electrode lines 125 are connected to each other through the contact hole 157 and the bridge electrode 168.

A fourth embodiment of the present invention will be described with reference to FIG.

The pixel electrode 161 is generally rectangular in shape and elongated in the extending direction of the data line 141. The pixel electrode 161 has a symmetrical shape up and down.

The pixel electrode 161 includes a first pixel electrode 161a and a second pixel electrode 161b separated from each other by the pixel electrode separation pattern 167. The first pixel electrode 161a is located in the center of the pixel and has a cramp shape. The second pixel electrode 161b surrounds the inside, the top, and the bottom of the first pixel electrode 161a. The second pixel electrode 161b is formed wider than the first pixel electrode 161a.

The thin film transistor T includes a first thin film transistor TFT1 connected to the first pixel electrode 161a and a second thin film transistor TFT2 connected to the second pixel electrode 161b.

The drain electrode 143 of each of the thin film transistors TFT1 and TFT2 overlaps the pixel electrode 161 to form a storage capacitor Cst, and the storage capacitor of the thin film transistors TFT1 and TFT2 is formed of the drain electrode 143 and the pixel electrode 161. Proportional to the overlap area.

In the fourth exemplary embodiment, different pixel voltages may be applied to the pixel electrodes 161a and 161b using independent thin film transistors TFT1 and TFT2. The principle of improving visibility in the fourth embodiment is the same as in the third embodiment, and the description thereof is omitted.

In the above-described third and fourth embodiments, the configuration of the non-display area follows the first or second embodiment.

On the other hand, in the third and fourth embodiments, the pixel electrode 161 is divided so that the liquid crystal capacitor Clc and the storage capacitor Cst are small. As a result, the kickback voltage Vkb becomes large (see Equation 1), which causes further problems in luminance difference. Therefore, in the third and fourth embodiments, it is necessary to further uniformize the gate signal delay using the resistor unit.

Although embodiments of the present invention have been shown and described, it will be apparent to those skilled in the art that the present embodiments may be modified without departing from the spirit or principles of the present invention. It is intended that the scope of the invention be defined by the claims appended hereto and their equivalents.

As described above, according to the present invention, there is provided a liquid crystal display device in which luminance unevenness due to a gate signal delay difference is reduced.

Claims (20)

A liquid crystal display device comprising a first substrate having a display area, a second substrate facing the first substrate, and a liquid crystal layer positioned between the first substrate and the second substrate. The first substrate, A gate main line positioned in the display area; A gate pad positioned outside the display area; And a resistor unit electrically connecting the gate main line and the gate pad and having a resistance higher than that of the gate main line. The method of claim 1, The first substrate, A thin film transistor connected to the gate main line; The display device further comprises a pixel electrode electrically connected to the thin film transistor. The method of claim 2, And the resistor unit is made of the same material as the pixel electrode. The method of claim 3, The resistor unit includes indium tin oxide (ITO) or indium zinc oxide (IZO). The method of claim 1, And the resistance is smaller as the distance between the gate main line and the gate pad connecting the resistor unit increases. The method of claim 1, And a fan-out part disposed between the gate pad and the resistor part. The method of claim 6, And the gate main line, the gate pad and the fan-out portion are formed of the same layer. The method of claim 6, And a sealant formed on the fan-out part, the sealant coupling the first substrate and the second substrate. The method of claim 1, And a fan-out part disposed between the gate pad and the resistor part. The method of claim 9, And the gate pad, the fan-out part and the resistor part are formed of the same layer. The method of claim 1, At least a portion of the resistor unit is formed in a zigzag. The method of claim 2, And the liquid crystal layer is in VA (vertical alignment) mode. The method of claim 12, The pixel electrode has a pixel electrode incision pattern formed thereon, And the second substrate includes a common electrode having a common electrode cutting pattern formed thereon. The method of claim 13, The pixel electrode includes a first pixel electrode and a second pixel electrode which are separated from each other, and different pixel voltages are applied to the first pixel electrode and the second pixel electrode. The method of claim 14, The thin film transistor includes a drain electrode, And the drain electrode includes a first drain electrode applying a data voltage directly to the first pixel electrode and a second drain electrode forming a coupling capacitance with the second pixel electrode. The method of claim 14, The thin film transistor includes a first thin film transistor connected to the first pixel electrode and a second thin film transistor connected to the second pixel electrode. The method of claim 1, Wherein the total resistance of the resistor unit is 10% to 50% of the total resistance of the gate main line. The method of claim 1, Liquid crystal display device characterized in that the change in the gate signal delay of the gate main line is within 100% A liquid crystal display device comprising a first substrate having a display area, a second substrate facing the first substrate, and a liquid crystal layer positioned between the first substrate and the second substrate. The first substrate, A gate main line positioned in the display area; A gate pad positioned outside the display area; A resistor unit electrically connecting the gate main line and the gate pad and having a resistance higher than that of the gate main line; A thin film transistor connected to the gate main line; A pixel electrode electrically connected to the thin film transistor and made of the same material as the resistor; The liquid crystal layer is a liquid crystal display device in VA mode. A substrate having a display area and a non-display area, A gate main line positioned in the display area; A gate pad positioned outside the display area; A resistor unit electrically connecting the gate main line and the gate pad and having a resistance higher than that of the gate main line; A thin film transistor connected to the gate main line; And a pixel electrode electrically connected to the thin film transistor, the pixel electrode being made of the same material as the resistor.

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