KR20130042242A - Liquid crystal display - Google Patents

Liquid crystal display Download PDF

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Publication number
KR20130042242A
KR20130042242A KR1020110106424A KR20110106424A KR20130042242A KR 20130042242 A KR20130042242 A KR 20130042242A KR 1020110106424 A KR1020110106424 A KR 1020110106424A KR 20110106424 A KR20110106424 A KR 20110106424A KR 20130042242 A KR20130042242 A KR 20130042242A
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KR
South Korea
Prior art keywords
reference voltage
thin film
film transistor
line
subpixel electrode
Prior art date
Application number
KR1020110106424A
Other languages
Korean (ko)
Inventor
김종인
박민욱
백범기
고준철
윤영수
최학범
김효섭
Original Assignee
삼성디스플레이 주식회사
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Priority to KR1020110106424A priority Critical patent/KR20130042242A/en
Priority to US13/517,872 priority patent/US8952878B2/en
Publication of KR20130042242A publication Critical patent/KR20130042242A/en
Priority to US14/591,833 priority patent/US9261749B2/en

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    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1343—Electrodes
    • G02F1/13439—Electrodes characterised by their electrical, optical, physical properties; materials therefor; method of making
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136204—Arrangements to prevent high voltage or static electricity failures
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136286—Wiring, e.g. gate line, drain line
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/1368—Active matrix addressed cells in which the switching element is a three-electrode device
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2330/00—Aspects of power supply; Aspects of display protection and defect management
    • G09G2330/02—Details of power systems and of start or stop of display operation
    • G09G2330/025—Reduction of instantaneous peaks of current
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3648—Control of matrices with row and column drivers using an active matrix

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  • Physics & Mathematics (AREA)
  • Nonlinear Science (AREA)
  • Mathematical Physics (AREA)
  • Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • General Physics & Mathematics (AREA)
  • Optics & Photonics (AREA)
  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Liquid Crystal (AREA)

Abstract

A liquid crystal display according to an exemplary embodiment of the present invention includes a first substrate including a display area and a peripheral area surrounding the display area, two reference voltage bars respectively positioned at both peripheral areas of the display area, and a first substrate. A plurality of gate lines positioned thereon; a plurality of reference voltage lines positioned on the first substrate and connected to two reference voltage bars; a plurality of data lines positioned on the first substrate and intersecting the gate lines; a plurality of gate lines and a plurality of data A plurality of pixels connected to the line, and an auxiliary voltage line electrically connected to the reference voltage line, wherein each pixel includes a first thin film transistor and a second thin film transistor, a gate line, and a first line connected to the gate line and the data line. 2 third thin film transistor connected to the thin film transistor and the reference voltage line, a first thin film transistor connected to the first thin film transistor Claim that is connected to the pixel electrode and the second thin film transistor includes a pixel electrode having a second sub-pixel electrode.

Description

[0001] LIQUID CRYSTAL DISPLAY [0002]

The present invention relates to a liquid crystal display device.

The liquid crystal display device is one of the most widely used flat panel display devices and is composed of two display panels having an electric field generating electrode such as a pixel electrode and a common electrode and a liquid crystal layer interposed therebetween.

An electric field is generated by applying a voltage to the field generating electrode, thereby determining an orientation of the liquid crystal molecules of the liquid crystal layer and controlling the polarization of incident light to display an image.

The liquid crystal display device further includes a switching element connected to each pixel electrode, and a plurality of signal lines such as a gate line and a data line for controlling the switching element to apply a voltage to the pixel electrode.

Among such liquid crystal displays, a vertically aligned liquid crystal display in which the long axis of the liquid crystal molecules is arranged perpendicular to the display panel without an electric field applied to the liquid crystal display device has a high contrast ratio and a wide reference viewing angle. .

However, in the vertical alignment liquid crystal display, side visibility may be inferior to that of the front visibility. In order to solve this problem, the transmittance may be changed by dividing one pixel into two subpixels and differently controlling the voltages of the two subpixels. The method was presented.

Meanwhile, when the voltages of the two subpixels are adjusted differently, the reference voltage may change in the liquid crystal display.

The problem to be solved by the present invention is to prevent the occurrence of variations in the reference voltage in the liquid crystal display device.

A liquid crystal display according to an exemplary embodiment of the present invention includes a first substrate including a display area and a peripheral area surrounding the display area, two reference voltage bars respectively positioned at both peripheral areas of the display area, and a first substrate. A plurality of gate lines positioned thereon; a plurality of reference voltage lines positioned on the first substrate and connected to two reference voltage bars; a plurality of data lines positioned on the first substrate and intersecting the respective gate lines; A plurality of pixels connected to the data line, and an auxiliary voltage line electrically connected to the reference voltage line, wherein each pixel includes a first thin film transistor, a second thin film transistor, a gate line, A third thin film transistor connected to the second thin film transistor and the reference voltage line, and connected to the first thin film transistor And a pixel electrode having a first subpixel electrode and a second subpixel electrode connected to the second thin film transistor.

The plurality of auxiliary voltage lines may be connected to each reference voltage line through the third thin film transistor in each pixel.

Each auxiliary voltage line may be positioned on each data line.

The display device may further include a signal line positioned in the peripheral area and applying a reference voltage to the reference voltage bar, and the width of the reference voltage bar may increase from the side connected to the signal line to the side facing the side connected to the signal line.

A second reference voltage equal to or greater than a magnitude of the first reference voltage and the first reference voltage may be applied to the reference voltage bar.

There are a plurality of auxiliary voltage lines, and each of the auxiliary voltage lines may be positioned only at 1/4, 1/2 and 3/4 of the interval between the two reference voltage bars.

The auxiliary voltage line may be located only at one half of the interval between two reference voltage bars.

The magnitude of the voltage applied to the auxiliary voltage line may be greater than or equal to the magnitude of the voltage applied to the reference voltage line.

The reference voltage line may include a protrusion overlapping one terminal of the third thin film transistor, and the auxiliary voltage line may include a connection member extending toward the protrusion of the reference voltage line.

The connection member may be connected to one terminal of the third thin film transistor.

The output terminal of the second thin film transistor may be connected to the input terminal of the second subpixel electrode and the third thin film transistor.

The voltage applied to the second subpixel electrode may be lower than the voltage applied to the first subpixel electrode.

An area of the second subpixel electrode may be equal to or larger than an area of the first subpixel electrode.

The first subpixel electrode and the second subpixel electrode may include a cross stem portion including a horizontal stem portion and a vertical stem portion crossing the cross stem portion, and a plurality of minute branches extending from the cross stem portion.

The gate line transfers a gate signal, and a gate signal applied to control terminals of each of the first thin film transistor, the second thin film transistor, and the third thin film transistor may be simultaneously transmitted.

A liquid crystal display according to another exemplary embodiment of the present invention includes a first substrate including a display area and a peripheral area surrounding the display area, two reference voltage bars respectively positioned at both peripheral areas of the display area, and on the first substrate. A gate line positioned thereon, a reference voltage line positioned on the first substrate and connected to two reference voltage bars, a first thin film transistor positioned on the first substrate and intersecting the gate line, and connected to the gate line and the data line; A third thin film transistor connected to a second thin film transistor, a gate line, a second thin film transistor, and a reference voltage line, a first subpixel electrode connected to a first thin film transistor, and a second subpixel electrode connected to a second thin film transistor. And a signal line positioned in the peripheral area and applying a reference voltage to the reference voltage bar. The width of the quasi-voltage bar becomes wider from the side connected to the signal line to the side facing the side connected to the signal line.

A liquid crystal display according to another exemplary embodiment of the present invention includes a first substrate including a display area and a peripheral area surrounding the display area, two reference voltage bars respectively positioned at both peripheral areas of the display area, and a first substrate. A gate line positioned above, a reference voltage line positioned on the first substrate and connected to two reference voltage bars, a first thin film transistor positioned on the first substrate and connected to the gate line and the data line crossing the gate line; A third thin film transistor connected to a second thin film transistor, a gate line, a second thin film transistor and a reference voltage line, and a first subpixel electrode connected to the first thin film transistor and a second part connected to the second thin film transistor. A pixel electrode having a pixel electrode, and a first reference voltage and a second reference voltage are applied to the reference voltage bar.

The magnitude of the second reference voltage may be equal to or greater than the magnitude of the first reference voltage.

The display device may further include a first signal line applying the first reference voltage to the reference voltage bar and a second signal line applying the second reference voltage to the reference voltage bar.

The reference voltage bar may include a pair of sides facing each other, and the sides of the reference voltage bar connected to the first signal line and the sides of the reference voltage bar connected to the second signal line may face each other.

As described above, according to an exemplary embodiment of the present invention, three auxiliary voltage lines or one auxiliary voltage line to which an auxiliary voltage greater than or equal to the reference voltage applied to the reference voltage bar is formed to form a variation in the reference voltage in the liquid crystal display. Can be prevented.

In addition, an auxiliary voltage line connected to the reference voltage line may be formed on each data line to prevent variations in the reference voltage in the liquid crystal display.

In addition, the width of the reference voltage bar may be gradually widened from the side connected to the first signal line to the side facing the side of the reference voltage bar, thereby preventing variation in the reference voltage in the liquid crystal display.

In addition, two reference voltages having the same or different magnitudes may be applied to different sides of the reference voltage bar to prevent variations in the reference voltage in the liquid crystal display.

1 is an equivalent circuit diagram of one pixel of a liquid crystal display according to an exemplary embodiment of the present invention.
2 is a diagram schematically illustrating a liquid crystal display according to an exemplary embodiment of the present invention.
FIG. 3 is a layout view of one pixel of the liquid crystal display of FIG. 2.
4 is a cross-sectional view taken along the line IV-IV of FIG. 3.
5 is a cross-sectional view taken along the cutting line VV of FIG. 3.
FIG. 6 is a view schematically illustrating a liquid crystal display according to another exemplary embodiment of the present invention.
FIG. 7 is a layout view of one pixel of the liquid crystal display of FIG. 6.
8 is a view schematically illustrating a liquid crystal display according to another exemplary embodiment of the present invention.
FIG. 9 is a layout view of one pixel of the liquid crystal display of FIG. 8.
FIG. 10 is a cross-sectional view taken along the cutting line XX of FIG. 9.
FIG. 11 is a view schematically illustrating a liquid crystal display according to another exemplary embodiment of the present invention.
12 is a schematic view of a liquid crystal display according to another exemplary embodiment of the present invention.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Reference will now be made in detail to the preferred embodiments of the present invention, examples of which are illustrated in the accompanying drawings. However, the present invention is not limited to the embodiments described herein but may be embodied in other forms. Rather, the embodiments disclosed herein are provided so that the disclosure can be thorough and complete, and will fully convey the scope of the invention to those skilled in the art.

In the drawings, the thicknesses of layers and regions are exaggerated for clarity. Also, when a layer is referred to as being "on" another layer or substrate, it may be formed directly on another layer or substrate, or a third layer may be interposed therebetween. Like numbers refer to like elements throughout the specification.

Referring to FIG. 1, a liquid crystal display according to an exemplary embodiment of the present invention will be briefly described.

1 is an equivalent circuit diagram of one pixel of a liquid crystal display according to an exemplary embodiment of the present invention.

Referring to FIG. 1, a liquid crystal display according to an exemplary embodiment includes a signal line including a gate line GL for transmitting a gate signal and a data line DL for transmitting a data signal, and a pixel PX connected thereto. Include.

The pixel PX includes first, second and third switching elements Qa, Qb, and Qc, first and second liquid crystal capacitors Clc_H and Clc_L, and a reduced pressure capacitor Cstd. The first, second and third switching elements Qa, Qb, and Qc may be three-terminal elements such as thin film transistors, respectively.

The first switching element Qa and the second switching element Qb are connected to the gate line GL and the data line DL, respectively, and the third switching element Qc is the gate line GL and the second switching. It is connected to the output terminal of element Qb.

The first switching element Qa and the second switching element Qb are three-terminal elements such as thin film transistors, and a control terminal thereof is connected to the gate line GL, and an input terminal is connected to the data line DL. The output terminal of the first switching element Qa is connected to the first liquid crystal capacitor Clc_H, and the output terminal of the second switching element Qb is the second liquid crystal capacitor Clc_L and the third switching element Qc. ) Is connected to the input terminal of).

The third switching element Qc is also a three-terminal element such as a thin film transistor. The control terminal is connected to the gate line GL, the input terminal is connected to the second liquid crystal capacitor Clc_L, and the output terminal is a reference voltage. (Vcst) is authorized.

When a gate on signal Von is applied to the gate line GL, the first switching device Qa, the second switching device Qb, and the third switching device Qc connected thereto are turned on. Accordingly, the data voltage applied to the data line DL is first and second subpixel electrodes PEa and PEb through the turned-on first switching element Qa and the second switching element Qb, respectively. Is applied. In this case, the data voltages applied to the first subpixel electrode PEa and the second subpixel electrode PEb may be charged to the same value. However, according to the exemplary embodiment of the present invention, the voltage applied to the second subpixel electrode PEb is divided by the third switching element Qc connected in series with the second switching element Qb. Since the voltage applied to the second subpixel electrode PEb is turned on, the voltage difference between the sustain voltage Vcst and the input data voltage and the third switching element Qc have the third voltage. The voltage is divided according to the resistance value. Therefore, the voltage applied to the second subpixel electrode PEb is smaller than the voltage applied to the first subpixel electrode PEa. In this case, the voltage applied to the first subpixel electrode PEa and the second subpixel electrode PEb is the positive electrode (+), and on the contrary, the first subpixel electrode PEa and the second subpixel electrode. When the voltage applied to PEb is the negative electrode (−), the voltage applied to the first subpixel electrode PEa is smaller than the voltage applied to the second subpixel electrode PEb.

As a result, the voltage charged in the first liquid crystal capacitor Clc_H and the voltage charged in the second liquid crystal capacitor Clc_L are different from each other. Since the voltage charged in the first liquid crystal capacitor Clc_H and the voltage charged in the second liquid crystal capacitor Clc_L are different from each other, the angles at which the liquid crystal molecules are inclined in the first subpixel and the second subpixel are different. The brightness of the subpixels is different. Accordingly, by properly adjusting the voltage charged in the first liquid crystal capacitor Clc_H and the voltage charged in the second liquid crystal capacitor Clc_L, the image viewed from the side may be as close as possible to the image viewed from the front. Side visibility can be improved.

Next, the structure of the liquid crystal display according to the exemplary embodiment of the present invention will be described with reference to FIGS. 2 to 5. FIG. 2 is a view schematically illustrating a liquid crystal display according to an exemplary embodiment of the present invention, and FIG. 3 is a layout view of one pixel of the liquid crystal display of FIG. 2. 4 is a cross-sectional view taken along the line IV-IV of FIG. 3, and FIG. 5 is a cross-sectional view taken along the line V-V of FIG. 3.

2, the liquid crystal display according to the present exemplary embodiment includes a lower panel 100 and an upper panel 200 facing each other.

The lower panel 100 includes a plurality of gate lines 121, a plurality of data lines 171, a plurality of reference voltage lines 131, a plurality of gate driving ICs 440, and a data driving IC 540. The gate line 121 is connected to a gate pad 129 that receives a gate signal formed by a combination of the gate-on voltage Von and the gate-off voltage Voff from the gate driver IC 440, and the data line 171. Is connected to a data pad 179 that receives a data signal from the data driver IC 540. The gate pad 129 and the data pad 179 are connected to the gate driving IC 440 and the data driving IC 540, respectively.

The gate driving IC 440 may be directly mounted on the lower panel 100 in the form of at least one integrated circuit or IC chip, mounted on a flexible film, attached to the lower panel 100, or a separate printed circuit board ( It can be mounted on a printed circuit board (not shown).

In addition, the gate driving IC 440 may be integrated in the lower panel 100 together with the gate line 121, the data line 171, and the thin film transistor.

The portion where the gate line 121 and the data line 171 intersect becomes a display area for displaying an image. Reference voltage bars 135 for applying a reference voltage to the reference voltage line 131 are formed in peripheral regions on both sides of the display area. The reference voltage bar 135 has a rectangular shape in which two sides facing each other have the same length. Although the reference voltage bar 135 is formed in a rectangular shape in this embodiment, the present invention is not limited thereto and may have various shapes such as an ellipse. In addition, in the present embodiment, the reference voltage bars 135 are located in the peripheral areas on both sides of the display area, respectively.

Here, the reference voltage line 131 is formed on the same layer as the gate line 121, and the reference voltage bar 135 is formed on the same layer as the data line 171. That is, the reference voltage line 131 and the reference voltage bar 135 are formed on different layers. The reference voltage line 131 and the reference voltage bar 135 positioned on different layers are connected to each other through a connection electrode (not shown) formed on the same layer as the pixel electrode 191 described later.

A printed circuit board 420 that receives an image signal from the outside of the liquid crystal display device and applies a driving signal to the liquid crystal display device is disposed on the lower panel 100 through the flexible printed circuit board 410. Is connected to.

The reference voltage bar 135 is connected to the first reference voltage pad 500 to which the reference voltage is applied through the first signal line 510. The first reference voltage pad 500 is formed on the printed circuit board 420.

An auxiliary voltage line 137 is formed on each data line 171. That is, the number of auxiliary voltage lines 137 and the number of data lines 171 are the same. Each auxiliary voltage line 137 is connected to the reference voltage line 131 to distribute the reference voltage.

As described above, since the reference voltage is dispersed in the liquid crystal display by the auxiliary voltage line 137, it is possible to prevent variations in the reference voltage in the liquid crystal display. In addition, since each auxiliary voltage line 137 is positioned on the data line 171, it is possible to prevent the data voltage applied to the data line 171 from affecting the liquid crystal layer 3.

Referring to FIGS. 3 to 5, the liquid crystal display shown in FIG. 2 will be described in more detail.

In the liquid crystal display according to the present exemplary embodiment, the lower panel 100 and the upper panel 200 facing each other, the liquid crystal layer 3 interposed between the two display panels 100 and 200, and the outside of the display panels 100 and 200. And a pair of polarizers (not shown) attached to the surface.

First, the lower panel 100 will be described.

The gate line 121 and the reference voltage line 131 are formed on an insulating substrate 110 made of transparent glass, plastic, or the like. The gate line 121 includes a first gate electrode 124a, a second gate electrode 124b, and a third gate electrode 124c. The reference voltage line 131 includes a reference electrode 133 surrounding the first pixel electrode 191a and a protrusion 134 protruding in the direction of the gate line 121.

The gate insulating layer 140 is formed on the gate line 121 and the reference voltage line 131. The first semiconductor 154a, the second semiconductor 154b, and the third semiconductor 154c are formed on the gate insulating layer 140.

A plurality of ohmic contacts 163a, 165a, and 165c are formed on the first semiconductor 154a and the third semiconductor 154c. An ohmic contact (not shown) is also formed on the second semiconductor 154b.

The plurality of data lines 171 and the first drain electrode 175a including the first source electrode 173a and the second source electrode 173b on the ohmic contacts 163a, 165a, and 165c and the gate insulating layer 140. The data conductors 171, 173c, 175a, 175b, and 175c including the second drain electrode 175b, the third source electrode 173a, and the third drain electrode 175c are formed. The third drain electrode 175c overlaps the protrusion 134 of the reference voltage line 131.

The first gate electrode 124a, the first source electrode 173a, and the first drain electrode 175a together with the first semiconductor 154a form a first thin film transistor Qa, and a channel of the thin film transistor. ) Is formed in the semiconductor portion 154a between the first source electrode 173a and the first drain electrode 175a.

Similarly, the second gate electrode 124b, the second source electrode 173b, and the second drain electrode 175b together with the second semiconductor 154b form a second thin film transistor Qb, and the thin film transistor Channels are formed in the semiconductor portion 154b between the second source electrode 173b and the second drain electrode 175b, and the third gate electrode 124c, the third source electrode 173c, and the third drain electrode 175c forms a third thin film transistor Qc together with the third semiconductor 154c, and a channel of the thin film transistor is a semiconductor portion 154c between the third source electrode 173c and the third drain electrode 175c. Is formed.

The passivation layer 180 is formed on the data conductors 171, 173c, 175a, 175b, and 175c and the exposed semiconductors 154a, 154b, and 154c. The protective film 180 is made of an inorganic insulating material such as silicon nitride and silicon oxide. However, the protective film 180 can be made of organic insulating material and the surface can be flat. The organic insulator may have photosensitivity and its dielectric constant may be about 4.0 or less. The passivation layer 180 may also have a double layer structure of the lower inorganic layer and the upper organic layer so as not to damage the exposed portions of the semiconductors 154a, 154b, and 154c while maintaining excellent insulating properties of the organic layer.

The passivation layer 180 may include a first contact hole 185a, a second contact hole 185b, and a third electrode exposing the first drain electrode 175a, the second drain electrode 175b, and the third drain electrode 175c, respectively. The contact hole 185c is formed.

The pixel electrode 191 including the first subpixel electrode 191a and the second subpixel electrode 191b and the auxiliary voltage line 137 are formed on the passivation layer 180. The pixel electrode 191 and the auxiliary voltage line 137 may be made of a transparent conductive material such as ITO or IZO, or a reflective metal such as aluminum, silver, chromium, or an alloy thereof.

The first subpixel electrode 191a and the second subpixel electrode 191b are adjacent to each other in a column direction, and have a cross-shaped stem portion including a rectangular shape having an overall shape and a horizontal stem portion 192 and a vertical stem portion 193 crossing the same. Include. In addition, the horizontal stem portion 192 and the vertical stem portion 193 is divided into four sub-regions, each sub-region includes a plurality of fine branch portion 194.

One of the minute branches 194 of the first subpixel electrode 191a and the second subpixel electrode 191b extends obliquely in the upper left direction from the horizontal stem 192 or the vertical stem 193. The other minute branch 194 extends obliquely in the upper right direction from the horizontal stem 192 or the vertical stem 193. In addition, the other minute branch 194 extends in the lower left direction from the horizontal stem 192 or the vertical stem 193, and the other minute branch 194 is the horizontal stem 192 or the vertical. The stem portion 193 extends obliquely in the lower right direction.

Each minute branch 194 forms an angle of about 40 degrees to 45 degrees with the gate line 121 or the horizontal stem portion 192. In particular, the minute branches 194 included in the first subpixel electrode 191a may form an angle of about 40 degrees with the horizontal stem 192, and the minute branches included in the second subpixel electrode 191b. 194 may form an angle of approximately 45 degrees with the horizontal stem 192. In addition, the minute branches 194 of two neighboring subregions may be perpendicular to each other.

Although not shown, the width of the minute branch 194 may be gradually widened.

The first subpixel electrode 191a and the second subpixel electrode 191b are physically and electrically connected to the first drain electrode 175a and the second drain electrode 175b through the contact holes 185a and 185b, respectively. The data voltage is applied from the first drain electrode 175a and the second drain electrode 175b. In this case, some of the data voltages applied to the second drain electrode 175b are divided through the third source electrode 173c, and the magnitude of the voltage applied to the second subpixel electrode 191b is equal to the first subpixel electrode ( It becomes smaller than the magnitude of the voltage applied to 191a). In this case, the voltage applied to the first subpixel electrode 191a and the second subpixel electrode 191b is a positive electrode (+), and on the contrary, the first subpixel electrode 191a and the second subpixel electrode When the voltage applied to the first subpixel electrode 191a is smaller than the voltage applied to the second subpixel electrode 191b when the voltage applied to the first subpixel electrode 191a is negative.

The area of the second subpixel electrode 191b may be one or more times two times or less than the area of the first subpixel electrode 191a.

The auxiliary voltage line 137 is positioned at a portion corresponding to each data line 171 and includes a connection member 138 extending toward the protrusion 134 of the reference voltage line 131. The connection member 138 is connected to the third drain electrode 175c through the third contact hole 185c.

The upper panel 200 will now be described.

A light blocking member 220 is formed on an insulating substrate 210 made of transparent glass or plastic. The light blocking member 220 is also called a black matrix and prevents light leakage.

A plurality of color filters 230 is also formed on the substrate 210 and the light blocking member 220. The color filter 230 is mostly present in an area surrounded by the light blocking member 220, and may extend long along the column of pixel electrodes 191. Each color filter 230 may display one of primary colors such as three primary colors of red, green, and blue. However, it is not limited to the three primary colors of red, green, and blue, and one of cyan, magenta, yellow, and white colors may be displayed.

At least one of the light blocking member 220 and the color filter 230 may be formed on the lower substrate 110.

An overcoat 250 is formed on the color filter 230 and the light blocking member 220. The overcoat 250 may be made of an insulating material to prevent the color filter 230 from being exposed and to provide a flat surface. The overcoat 250 may be omitted.

A common electrode 270 is formed on the lid 250.

Alignment layers (not shown) are formed on both surfaces of the display panels 100 and 200, and they may be vertical alignment layers.

Polarizers (not shown) are provided on the outer surfaces of the display panels 100 and 200, and the polarization axes of the two polarizers are orthogonal to each other, and one polarization axis is parallel to the gate line 121. In the case of a reflective liquid crystal display, one of two polarizers may be omitted.

The first subpixel electrode 191a and the second subpixel electrode 191b receiving the data voltage generate the electric field together with the common electrode 270 of the common electrode display panel 200 receiving the common voltage. , 191b, 270 determines the direction of the liquid crystal molecules of the liquid crystal layer 3. Polarization of light passing through the liquid crystal layer 3 varies depending on the orientation of the liquid crystal molecules thus determined.

The first and second subpixel electrodes 191a and 191b and the common electrode 270 form liquid crystal capacitors Clc_H and Clc_L to maintain the applied voltage even after the thin film transistor is turned off. At this time, the sides of the minute branch 194 distort the electric field to create a horizontal component perpendicular to the side of the minute branch 194, and the inclination direction of the liquid crystal molecules is determined in a direction determined by the horizontal component. Therefore, the liquid crystal molecules are initially inclined in a direction perpendicular to the sides of the minute branch 194. However, since the direction of the horizontal component of the electric field due to the sides of the neighboring minute branches 194 is opposite and the interval between the minute branches 194 is narrow, the liquid crystal molecules to be inclined in opposite directions together are minute branches 194. Inclined in a direction parallel to the longitudinal direction.

In one embodiment of the present invention, since the length directions in which the minute branches 194 of one pixel extend are all four directions, the directions in which the liquid crystal molecules are inclined are also four directions. When the direction in which the liquid crystal molecules are tilted is varied in this way, the reference viewing angle of the liquid crystal display device is increased.

Hereinafter, a liquid crystal display according to another exemplary embodiment of the present invention will be described with reference to FIGS. 6 and 7.

FIG. 6 is a schematic view of a liquid crystal display according to another exemplary embodiment. FIG. 7 is a layout view of one pixel of the liquid crystal display of FIG. 6.

6 and 7, the liquid crystal display according to the present exemplary embodiment is similar to the structure of the liquid crystal display according to the exemplary embodiment illustrated in FIGS. 2 to 5. Description of similar parts is omitted.

In the liquid crystal display according to the present exemplary embodiment, unlike the liquid crystal display according to the exemplary embodiment illustrated in FIGS. 2 to 5, the auxiliary voltage line 137 is a quarter point of the interval D between the two reference voltage bars 135. , 1/2 and 3/4. That is, three auxiliary voltage lines 137 are formed in the liquid crystal display of FIG. 6. Each auxiliary voltage line 137 is connected to an auxiliary voltage pad 550 to which an auxiliary voltage is applied through an auxiliary voltage applying line 560. The auxiliary voltage pad 550 is formed on the printed circuit board 420.

Each auxiliary voltage line 137 is positioned on the data line 171 and receives an auxiliary voltage from the auxiliary voltage pad 550. The magnitude of the reference voltage applied to each reference voltage line 131 is greater than 1V and less than 20V, and the magnitude of the auxiliary voltage applied to each auxiliary voltage line 137 is greater than that of the reference voltage applied to each reference voltage line 131. It is greater than or equal to and smaller than the reference voltage applied to each reference voltage line 131 plus 10V. Preferably, the magnitude of the reference voltage applied to each reference voltage line 131 is greater than 7V and less than 15V, and the magnitude of the auxiliary voltage applied to each auxiliary voltage line 137 is a reference applied to each reference voltage line 131. It is greater than or equal to the magnitude of the voltage and is less than the value obtained by adding 3V to the reference voltage applied to each reference voltage line 131.

As such, three auxiliary voltage lines 137 are formed, and auxiliary voltages greater than or equal to a reference voltage applied to the reference voltage bar 135 are applied to each of the auxiliary voltage lines 137 so that the variation of the reference voltage in the liquid crystal display device is reduced. It can be prevented from occurring.

On the other hand, when the variation of the reference voltage is not large in the liquid crystal display, the auxiliary voltage may not be applied.

In the present embodiment, the auxiliary voltage line 137 has the auxiliary voltage line 137 formed at one-fourth, one-half, and three-fourths of the interval D between both reference voltage bars 135. However, the auxiliary voltage line 137 may be located only at one half of the interval D between the two reference voltage bars 135. It may also be located in the data driver IC 540.

Hereinafter, a liquid crystal display according to still another exemplary embodiment of the present invention will be described with reference to FIGS. 8 to 10.

FIG. 8 is a schematic view of a liquid crystal display according to another exemplary embodiment of the present invention. FIG. 9 is a layout view of one pixel of the liquid crystal display of FIG. 8, and FIG. 10 is a cutaway line XX of FIG. 9. It is a cross-sectional view.

8 to 10, the liquid crystal display according to the present exemplary embodiment is similar to the structure of the liquid crystal display according to the exemplary embodiment illustrated in FIGS. 2 to 5. Description of similar parts is omitted.

In the liquid crystal display according to the present exemplary embodiment, unlike the liquid crystal display according to the exemplary embodiment illustrated in FIGS. 2 to 5, the reference voltage bar 135 has a trapezoidal shape, and the reference voltage line 137 is not formed. An auxiliary electrode 195 is formed to be connected to the third drain electrode 175c through the contact hole 185c.

The auxiliary electrode 195 is formed on the passivation layer 180 and is formed of the same material as the pixel electrode 191.

The width a of the side of the reference voltage bar 135 connected to the first signal line 510 is smaller than the width b of the side facing the side. The width a of the side of the reference voltage bar 135 connected to the first signal line 510 is larger than 10 μm and smaller than 1000 μm, and the width b of the opposite side is greater than the width a and the width a. Is less than 4 times of. Preferably, the width a of the side of the reference voltage bar 135 connected to the first signal line 510 is larger than 50 μm, smaller than 300 μm, and the width b of the opposite side is greater than the width a, Less than four times the width (a). The width of the reference voltage bar 135 gradually increases from the side connected to the first signal line 510 to the side facing the side.

In the side connected to the first signal line 510 of the reference voltage bar 135 toward the side facing the side, the resistance of the reference voltage line 131 increases. However, as described above, the width of the reference voltage bar 135 is gradually widened from the side connected to the first signal line 510 to the side facing the side, thereby reducing the resistance of the reference voltage line 131. have. Therefore, it is possible to prevent the variation of the reference voltage in the liquid crystal display device.

Hereinafter, a liquid crystal display according to still another exemplary embodiment of the present invention will be described with reference to FIG. 11.

FIG. 11 is a view schematically illustrating a liquid crystal display according to another exemplary embodiment of the present invention.

Referring to FIG. 11, the liquid crystal display according to the present exemplary embodiment is similar to the structure of the liquid crystal display according to the exemplary embodiment illustrated in FIGS. 2 to 5. Thus, description of similar parts will be omitted.

In the liquid crystal display according to the present exemplary embodiment, unlike the liquid crystal display according to the exemplary embodiment illustrated in FIGS. 2 to 5, the reference voltage line 137 is not formed, and two reference voltages are applied to the reference voltage bar 135. Is approved.

The first reference voltage pad 500 and the second reference voltage pad 600 are formed on the printed circuit board 420. The first reference voltage pad 500 is connected to the reference voltage bar 135 through the first signal line 510, and the second reference voltage pad 600 is connected to the reference voltage bar 135 through the second signal line 610. )

The side of the reference voltage bar 135 connected to the first signal line 510 and the side of the reference voltage bar 135 connected to the second signal line 610 face each other. The reference voltage bar 135 receives a first reference voltage through the first signal line 510 and receives a second reference voltage through the second signal line 610.

The magnitude of the first reference voltage is greater than 1V, less than 20V, and the magnitude of the second reference voltage is greater than the magnitude of the first reference voltage and less than 5V added to the first reference voltage. Preferably, the magnitude of the first reference voltage is greater than 7V, less than 15V, the magnitude of the second reference voltage is greater than the magnitude of the first reference voltage, and less than the value of 2V added to the first reference voltage.

In addition, the magnitude of the first reference voltage may be equal to the magnitude of the second reference voltage.

As such, by applying the second reference voltage equal to or greater than the first reference voltage and the first reference voltage to the other side of the reference voltage bar 135, it is possible to prevent the variation of the reference voltage in the liquid crystal display. have.

Meanwhile, the above-described embodiments can be combined, which will be described with reference to FIG. 12.

12 is a schematic view of a liquid crystal display according to another exemplary embodiment of the present invention.

Referring to FIG. 12, the liquid crystal display according to the present exemplary embodiment is a combination of the structures of the liquid crystal display of FIGS. 2, 8, and 11.

Since the auxiliary voltage lines 137 are formed on the data lines 171, the number of the auxiliary voltage lines 137 and the number of the data lines 171 are the same. Each auxiliary voltage line 137 is connected to the reference voltage line 131 to distribute the reference voltage.

The reference voltage bar 135 has a trapezoidal shape, and the width a of the side of the reference voltage bar 135 connected to the first signal line 510 is smaller than the width b of the side facing the side. The width of the reference voltage bar 135 gradually increases from the side connected to the first signal line 510 to the side facing the side.

The second reference voltage equal to or greater than the magnitude of the first reference voltage and the first reference voltage is applied to the reference voltage bar 135. The first reference voltage pad 500 and the second reference voltage pad 600 are formed on the printed circuit board 420. The first reference voltage pad 500 is connected to the reference voltage bar 135 through the first signal line 510, and the second reference voltage pad 600 is connected to the reference voltage bar 135 through the second signal line 610. )

The side of the reference voltage bar 135 connected to the first signal line 510 and the side of the reference voltage bar 135 connected to the second signal line 610 face each other. The reference voltage bar 135 receives a first reference voltage through the first signal line 510 and receives a second reference voltage through the second signal line 610.

As described above, it is possible to prevent variations in the reference voltage in the liquid crystal display by combining the configurations of the liquid crystal display according to FIGS. 2, 8, and 11.

In the present embodiment, the liquid crystal display device in which the configuration of the liquid crystal display device of FIGS. 2, 8 and 11 is combined has been described, but the configuration of the liquid crystal display device according to another embodiment may be combined.

Accordingly, there is only a liquid crystal display device combining the configuration of the liquid crystal display device according to FIGS. 2 and 6 with reference to Tables 1 and 2 and a reference voltage line connecting the reference voltage bar and the reference voltage bar to a conventional structure, that is, a rectangular shape. The liquid crystal display device to which one reference voltage is applied to the voltage bar will be described.

Table 1 shows the data on the transmittance distribution of the structure of the conventional structure and the structure of the liquid crystal display according to FIGS. 2 and 6.

Standard deviation of transmittance of 9 points was applied to the panels according to Sample 1, Sample 2 and Sample 3 of the combination structure of Sample 1, Sample 2 and Sample 3 of the conventional structure and the structure of the liquid crystal display device according to FIGS. Indicated.

In the case of combining the configuration of the liquid crystal display device according to FIGS. 2 and 6, the average dispersion of the transmittances of the samples is 0.07%, and in the conventional structure, the average dispersion of the transmittances of the samples is 0.19%, according to FIGS. 2 and 6. It can be seen that the combination of the configuration of the liquid crystal display device is higher in transmission than in the conventional structure.

Conventional structure Combining the configuration of the liquid crystal display according to FIGS. 2 and 6 Sample 1 0.18% Sample 1 0.09% Sample 2 0.21% Sample 2 0.05% Sample 3 0.17% Sample 3 0.07%

Table 2 shows data on the amount of drop in the reference voltage of the conventional structure and the structure of the liquid crystal display according to FIGS. 2 and 6. The drop amount of the reference voltage was measured by dividing it into the horizontal direction and the vertical direction. The horizontal direction measured the upper left and middle upper parts of each panel, and the vertical direction measured the upper left and lower left parts of each panel.

In the case of combining the configuration of the liquid crystal display device according to FIGS. 2 and 6, the reference voltage drop in the horizontal direction of the panel and the vertical direction of the panel was 0.6 V. In the conventional structure, the reference voltage in the horizontal direction of the panel The drop was 3V and the panel's longitudinal reference drop was 0.8V.

That is, it can be seen that the combination of the configurations of the liquid crystal display of FIGS. 2 and 6 has a smaller reference voltage drop than the conventional structure.

Voltage drop Conventional structure According to FIGS. 2 and 6
Combination configuration of liquid crystal display The horizontal orientation of the panel 3 V 0.6 V Panel orientation 0.8 V 0.6 V

Although the preferred embodiments of the present invention have been described in detail above, the scope of the present invention is not limited thereto, and various modifications and improvements of those skilled in the art using the basic concepts of the present invention defined in the following claims are also provided. It belongs to the scope of rights.

121: gate line 131: reference voltage line
135: reference voltage bar 137: auxiliary voltage line
171: data line 191: pixel electrode

Claims (36)

A first substrate including a display area and a peripheral area surrounding the display area,
Two reference voltage bars respectively positioned in the peripheral regions of both sides of the display region;
A plurality of gate lines positioned on the first substrate,
A plurality of reference voltage lines positioned on the first substrate and connected to the two reference voltage bars;
A plurality of data lines positioned on the first substrate and crossing each of the gate lines;
A plurality of pixels connected to the plurality of gate lines and the plurality of data lines, and
An auxiliary voltage line electrically connected to the reference voltage line;
Each pixel is
A first thin film transistor and a second thin film transistor connected to the gate line and the data line,
A third thin film transistor connected to the gate line, the second thin film transistor, and the reference voltage line, and
And a pixel electrode having a first subpixel electrode connected to the first thin film transistor and a second subpixel electrode connected to the second thin film transistor. In claim 1,
And a plurality of auxiliary voltage lines, and connected to each of the reference voltage lines through the third thin film transistor in each pixel. In claim 2,
And each of the auxiliary voltage lines is positioned above each of the data lines. 4. The method of claim 3,
A signal line positioned in the peripheral region and configured to apply a reference voltage to the reference voltage bar;
And a width of the reference voltage bar increases from a side connected to the signal line to a side facing the side connected to the signal line. 5. The method of claim 4,
And a second reference voltage equal to or greater than a magnitude of a first reference voltage and the first reference voltage. 4. The method of claim 3,
And a second reference voltage equal to or greater than a magnitude of a first reference voltage and the first reference voltage. In claim 1,
And a plurality of auxiliary voltage lines, each of which is located only at one quarter, one half, and three quarters of the interval between the two reference voltage bars. In claim 1,
And the auxiliary voltage line is positioned only at one half of a distance between the two reference voltage bars. In claim 7 or 8,
The auxiliary voltage line is positioned on the data line. In the ninth,
And a voltage equal to or greater than a voltage applied to the auxiliary voltage line. 11. The method of claim 10,
A signal line positioned in the peripheral region and configured to apply a reference voltage to the reference voltage bar;
And a width of the reference voltage bar increases from a side connected to the signal line to a side facing the side connected to the signal line. 12. The method of claim 11,
And a second reference voltage equal to or greater than a magnitude of a first reference voltage and the first reference voltage. 11. The method of claim 10,
And a second reference voltage equal to or greater than a magnitude of a first reference voltage and the first reference voltage. In claim 1,
The reference voltage line includes a protrusion overlapping with one terminal of the third thin film transistor,
The auxiliary voltage line includes a connection member extending toward the protrusion of the reference voltage line. In claim 13,
And the connection member is connected to one terminal of the third thin film transistor. The method of claim 14,
The auxiliary voltage line is on the same layer as the first subpixel electrode and the second subpixel electrode. In claim 1,
And an output terminal of the second thin film transistor is connected to an input terminal of the second subpixel electrode and the third thin film transistor. The method of claim 17,
The voltage applied to the second subpixel electrode is lower than the voltage applied to the first subpixel electrode. The method of claim 18,
The area of the second subpixel electrode is equal to or larger than the area of the first subpixel electrode. 20. The method of claim 19,
The first subpixel electrode and the second subpixel electrode may have a cross stem portion formed of a horizontal stem portion and a vertical stem portion crossing the same.
And a plurality of minute branches extending from the cross stem. In claim 1,
The gate line transfers a gate signal, and a gate signal applied to a control terminal of each of the first thin film transistor, the second thin film transistor, and the third thin film transistor is simultaneously transmitted. A first substrate including a display area and a peripheral area surrounding the display area,
Two reference voltage bars respectively positioned in the peripheral regions of both sides of the display region;
A gate line positioned on the first substrate,
A reference voltage line positioned on the first substrate and connected to the two reference voltage bars;
A data line positioned on the first substrate and crossing the gate line;
A first thin film transistor and a second thin film transistor connected to the gate line and the data line,
A third thin film transistor connected to the gate line, the second thin film transistor, and the reference voltage line,
A pixel electrode having a first subpixel electrode connected to the first thin film transistor and a second subpixel electrode connected to the second thin film transistor, and
A signal line positioned in the peripheral region and configured to apply a reference voltage to the reference voltage bar;
And a width of the reference voltage bar increases from a side connected to the signal line to a side facing the side connected to the signal line. The method of claim 22,
And an output terminal of the second thin film transistor is connected to an input terminal of the second subpixel electrode and the third thin film transistor. The method of claim 23,
The voltage applied to the second subpixel electrode is lower than the voltage applied to the first subpixel electrode. 25. The method of claim 24,
The area of the second subpixel electrode is equal to or larger than the area of the first subpixel electrode. 26. The method of claim 25,
The first subpixel electrode and the second subpixel electrode may have a cross stem portion formed of a horizontal stem portion and a vertical stem portion crossing the same.
And a plurality of minute branches extending from the cross stem. The method of claim 22,
The gate line transfers a gate signal, and a gate signal applied to a control terminal of each of the first thin film transistor, the second thin film transistor, and the third thin film transistor is simultaneously transmitted. A first substrate including a display area and a peripheral area surrounding the display area,
Two reference voltage bars respectively positioned in the peripheral regions of both sides of the display region;
A gate line positioned on the first substrate,
A reference voltage line positioned on the first substrate and connected to the two reference voltage bars;
A data line positioned on the first substrate and crossing the gate line;
A first thin film transistor and a second thin film transistor connected to the gate line and the data line,
A third thin film transistor connected to the gate line, the second thin film transistor, and the reference voltage line, and
A pixel electrode having a first subpixel electrode connected to the first thin film transistor and a second subpixel electrode connected to the second thin film transistor;
And a first reference voltage and a second reference voltage are applied to the reference voltage bar. 29. The method of claim 28,
The second reference voltage has a magnitude equal to or greater than that of the first reference voltage. The method of claim 29,
A first signal line applying the first reference voltage to the reference voltage bar;
And a second signal line for applying the second reference voltage to the reference voltage bar. 32. The method of claim 30,
The reference voltage bar includes a pair of sides facing each other,
And a side of the reference voltage bar connected to the first signal line and a side of the reference voltage bar connected to the second signal line face each other. 29. The method of claim 28,
And an output terminal of the second thin film transistor is connected to an input terminal of the second subpixel electrode and the third thin film transistor. 32. The method of claim 32,
The voltage applied to the second subpixel electrode is lower than the voltage applied to the first subpixel electrode. The method of claim 33,
The area of the second subpixel electrode is equal to or larger than the area of the first subpixel electrode. 35. The method of claim 34,
The first subpixel electrode and the second subpixel electrode may have a cross stem portion formed of a horizontal stem portion and a vertical stem portion crossing the same.
And a plurality of minute branches extending from the cross stem. 29. The method of claim 28,
The gate line transfers a gate signal, and a gate signal applied to a control terminal of each of the first thin film transistor, the second thin film transistor, and the third thin film transistor is simultaneously transmitted.
KR1020110106424A 2011-10-14 2011-10-18 Liquid crystal display KR20130042242A (en)

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Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9753345B2 (en) 2012-08-22 2017-09-05 Samsung Display Co., Ltd. Mother substrate for display device, method for manufacturing the same, and method for manufacturing display device
KR20170114034A (en) * 2016-03-31 2017-10-13 삼성디스플레이 주식회사 Display devcie
US9817272B2 (en) 2015-05-20 2017-11-14 Samsung Display Co., Ltd. Liquid crystal display device
US10074324B2 (en) 2015-07-20 2018-09-11 Samsung Display Co., Ltd. Liquid crystal display panel and liquid crystal display device

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9753345B2 (en) 2012-08-22 2017-09-05 Samsung Display Co., Ltd. Mother substrate for display device, method for manufacturing the same, and method for manufacturing display device
US9817272B2 (en) 2015-05-20 2017-11-14 Samsung Display Co., Ltd. Liquid crystal display device
US10074324B2 (en) 2015-07-20 2018-09-11 Samsung Display Co., Ltd. Liquid crystal display panel and liquid crystal display device
KR20170114034A (en) * 2016-03-31 2017-10-13 삼성디스플레이 주식회사 Display devcie

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