KR20060062908A - Liquid crystal display panel - Google Patents

Abstract

The present invention relates to a liquid crystal display panel. The liquid crystal display panel of the present invention includes a thin film transistor substrate, an insulating substrate facing the thin film transistor substrate, a liquid crystal layer positioned between the thin film transistor substrate and the insulating substrate, wherein the thin film transistor substrate includes a gate wiring, A data line intersecting a gate line to form a pixel, a first thin film transistor and a second thin film transistor positioned in the pixel and receiving the same gate voltage and source voltage and applying different drain currents to the liquid crystal layer; And a pixel electrode layer connected to the first thin film transistor and the second thin film transistor and having a pixel electrode cutting pattern formed thereon. Thereby, visibility can be improved in the liquid crystal display panel of PVA mode.

Description

Liquid crystal display panel {LIQUID CRYSTAL DISPLAY PANEL}

1 is a layout view of a thin film transistor substrate according to a first embodiment of the present invention,

FIG. 2 is a cross-sectional view of the liquid crystal display panel according to II-II of FIG. 1.

3 is a cross-sectional view of a thin film transistor substrate according to III-III of FIG.

4 is an equivalent circuit diagram of a liquid crystal display panel according to a first embodiment of the present invention;

5 is a graph showing the drain current according to the gate voltage of the thin film transistors according to the first embodiment of the present invention,

6A to 6C are layout views of a thin film transistor substrate according to the second to fourth embodiments of the present invention, respectively.

Explanation of Signs of Major Parts of Drawings

121: gate line 122: gate electrode 141: data line 142a, 142b: source electrode

143a and 143b: drain electrode 151a: first domain

151b: Second domain 152: Cutting pattern

153: pixel electrode incision pattern

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a liquid crystal display panel. More particularly, in a PVA mode, a pair of thin film transistors for applying different drain currents to a liquid crystal layer by applying the same gate voltage and source voltage to a pixel may be used to provide visibility. It is related with the improved liquid crystal display panel.

The liquid crystal display device includes a thin film transistor substrate on which a thin film transistor is formed, a color filter substrate on which a color filter layer is formed, and a liquid crystal display panel on which a liquid crystal layer is positioned. Since the liquid crystal display panel is a non-light emitting device, a backlight unit for irradiating light may be disposed on the rear surface of the thin film transistor substrate. Light transmitted from the backlight unit is controlled according to the arrangement of the liquid crystal layer.

Liquid crystal display panels are advantageous for thin, small, and low power consumption, but have disadvantages such as large size, full color, contrast enhancement, and wide viewing angle.

In order to compensate for the wide viewing angle, which is a disadvantage of the liquid crystal display panel, many researches such as multi-domain technology, phase compensation technology, IPS mode, VA mode, and optical path control technology have been applied. Furthermore, the patterned vertical alignment combines the partial etching slit of pixel electrode and other techniques (e.g., cholesteric dopant, alignment control electrode, orientation method such as protrusion and rubbing) among VA mode in VA mode. ), Surround electrode (SE), ridge fringe field multidomain homeotropic (REFMH), and lateral field induced VA (LFIVA).                         

The patterned vertically aligned (PVA) mode refers to the formation of cutout patterns in the pixel electrode layer and the common electrode layer in the VA mode. It is a method of widening the viewing angle by controlling the direction in which the liquid crystal molecules lie down using a fringe field formed by these incision patterns.

In the PVA mode, the liquid crystal behaves vertically, so the liquid crystal retardation change is large when viewed from the front and side. As a result, the amount of gamma distortion due to the liquid crystal director distortion at the side is increased, and the brightness of the low gray scale is rapidly increased at the side, which causes a problem of deterioration of visibility accompanied by a decrease in contrast ratio.

Accordingly, an object of the present invention is to provide a PVA mode liquid crystal display panel with improved side visibility.

The above object is a liquid crystal display panel comprising a thin film transistor substrate, an insulating substrate facing the thin film transistor substrate, a liquid crystal layer positioned between the thin film transistor substrate and the insulating substrate, wherein the thin film transistor substrate is a gate wiring; A first thin film transistor and a second thin film disposed in the pixel to intersect the gate line, the first thin film transistor and a second thin film positioned in the pixel to receive the same gate voltage and source voltage and to apply different drain currents to the liquid crystal layer. It may be achieved by including a transistor, a pixel electrode layer connected to the first thin film transistor and the second thin film transistor and having a pixel electrode cutting pattern formed thereon.                     

The pixel electrode layer may include a first domain connected to the first thin film transistor, and a second domain connected to the second thin film transistor and separated from the first domain.

Preferably, the area of the first domain and the second domain is substantially the same.

Preferably, the first thin film transistor and the second thin film transistor have different widths of channel portions.

Preferably, the first thin film transistor and the second thin film transistor have different channel lengths.

The liquid crystal layer is preferably in a vertically aligned (VA) mode.

It is preferable that a common electrode layer having a common electrode cutting pattern formed thereon is formed on the insulating substrate.

Hereinafter, the present invention will be described in more detail with reference to the accompanying drawings. In the following, a film is formed (located) on top of another film, not only when two films are in contact with each other but also when another film is between two layers. It also includes the case where it exists.

1 is a layout view of a thin film transistor substrate 100 according to a first embodiment of the present invention, FIG. 2 is a cross-sectional view of the liquid crystal display panel 10 according to II-II of FIG. 1, and FIG. 3 is III-III of FIG. 1. A cross-sectional view of the thin film transistor substrate 100 along.

The liquid crystal display panel 10 according to an exemplary embodiment of the present invention includes a thin film transistor substrate 100, a color filter substrate 200 facing the thin film transistor substrate, and a liquid crystal layer 300 positioned therebetween.

First, the thin film transistor substrate 100 will be described.

Gate wirings 121, 122, and 123 are formed on the first insulating substrate 111. The gate wirings 121, 122, and 123 may be a metal single layer or multiple layers. The gate lines 121, 122, and 123 may include the gate line 121 and the pixel electrode layer 151 of the thin film transistors TR1 and TR2 connected to the gate line 121 and the gate line 121 extending in the horizontal direction. The common electrode line 123 overlaps with each other to form a storage capacitor.

On the first insulating substrate 111, a gate insulating layer 131 made of silicon nitride (SiNx) or the like covers the gate lines 121, 122, and 123.

A semiconductor layer 132 made of a semiconductor such as amorphous silicon is formed on the gate insulating layer 131 of the gate electrode 122, and n + is doped with silicide or n-type impurities at a high concentration on the semiconductor layer 132. An ohmic contact layer 133 made of a material such as hydrogenated amorphous silicon is formed. The ohmic contact layer 133 is divided into two parts around the gate electrode 122.

Data lines 141, 142a, 142b, 143a, and 143b are formed on the ohmic contact layer 133 and the gate insulating layer 131. The data lines 141, 142a, 142b, 143a, and 143b may also be a single layer or multiple layers of a metal layer. The data wires 141, 142a, 142b, 143a, and 143b are branches of the data line 141 and the data line 141 which are formed in the vertical direction and intersect the gate line 121 to form pixels, and are ohmic contacts 133. Is separated from the source electrodes 142a and 142b and the source electrodes 142a and 142b extending up to the upper portion of the panel), and the ohmic contact layer 133 opposite to the source electrodes 142a and 142b around the gate electrode 122. And drain electrodes 143a and 143b formed thereon.

   In this way, a pair of thin film transistors TR1 and TR2 connected to the same gate electrode 122 are provided in one pixel. Here, the channel lengths L1 and L2 and the channel widths W1 and W2 of the channel portions 144a and 144b of the thin film transistors TR1 and TR2 are different from each other. Specifically, the channel length L1 and the channel width W1 of the channel portion 144a of the first thin film transistor TR1 are larger and smaller than the second thin film transistor TR2. Therefore, the first thin film transistor TR1 has a smaller channel width / channel length (W / L) value for determining the characteristics of the thin film transistor than the second thin film transistor TR2.

On the data wirings 141, 142a, 142b, 143a, and 143b and the semiconductor layer 132 which is not covered by these, silicon nitride, an a-Si: C: O film or a-Si: O: F film deposited by PECVD method And a protective film 134 made of an acrylic organic insulating film or the like. In the passivation layer 134, contact holes 161a and 161b exposing the drain electrode 143 are formed.

The pixel electrode layers 151a and 151b are formed on the passivation layer 134. The pixel electrode layers 151a and 151b are usually made of a transparent conductive material such as indium tin oxide (ITO) or indium zinc oxide (IZO).

A cutting pattern 152 and a pixel electrode cutting pattern 153 are formed in the pixel electrode layers 151a and 151b. The pixel electrode cutting pattern 153 is formed to divide the liquid crystal layer 300 into a plurality of domains together with the common electrode cutting pattern 252 described later. The cut pattern 152 separates the pixel electrode layers 151a and 151b into a first domain 151a and a second domain 151b. The area of the first domain 151a and the second domain 151b is preferably the same. The first domain 151a is connected to the drain electrode 143a of the first thin film transistor TR1 through the contact hole 161a, and the second domain 151b is connected to the second thin film through the contact hole 161b. It is connected to the drain electrode 143b of the transistor TR2.

Next, the color filter substrate 200 will be described.

The black matrix 221 is formed on the second insulating substrate 211. The black matrix 221 generally distinguishes between red, green, and blue filters, and serves to block direct light irradiation to the thin film transistor positioned on the thin film transistor substrate 100. The black matrix 221 is usually made of a photosensitive organic material to which black pigment is added. As the black pigment, carbon black or titanium oxide is used.

The color filter layer 231 is formed by repeating the red, green, and blue filters on the black matrix 221. The color filter layer 231 serves to impart color to light emitted from the backlight unit (not shown) and passed through the liquid crystal layer 300. The color filter layer 231 is usually made of a photosensitive organic material.

An overcoat layer 241 is formed on the black matrix 221 which is not covered by the color filter layer 231 and the color filter layer 231. The overcoat layer 241 serves to protect the color filter layer 231 while planarizing the color filter layer 231, and an acrylic epoxy material is generally used.

The common electrode layer 251 is formed on the overcoat layer 241. The common electrode layer 251 is made of a transparent conductive material such as indium tin oxide (ITO) or indium zinc oxide (IZO). The common electrode layer 251 directly applies a voltage to the liquid crystal layer 300 along with the pixel electrode layers 151a and 151b of the thin film transistor substrate. The common electrode cutout pattern 252 is formed on the common electrode layer 251. The common electrode cutout pattern 252 divides the liquid crystal layer 300 into a plurality of domains along with the pixel electrode cutout patterns 153 of the pixel electrode layers 151a and 151b.

The pixel electrode cut pattern 153 and the common electrode cut pattern 252 may be formed in various shapes. For example, both the pixel electrode cutting pattern 153 and the common electrode cutting pattern 252 may be formed diagonally and orthogonally to each other.

The liquid crystal layer 300 is positioned between the thin film transistor substrate 100 and the color filter substrate 200. The liquid crystal layer 300 is a VA (vertically aligned) mode, and the liquid crystal molecules are vertical in the length direction when no voltage is applied. When voltage is applied, the liquid crystal molecules lie perpendicular to the electric field because the dielectric anisotropy is negative. However, when the pixel electrode incision pattern 153 and the common electrode incision pattern 252 are not formed, the liquid crystal molecules are randomly arranged in various directions because the azimuth of the lying down is not determined, and the foreground line is disposed at different boundary surfaces. ) The pixel electrode incision pattern 153 and the common electrode incision pattern 252 form a fringe field when a voltage is applied to the liquid crystal layer 300 to determine an azimuth angle of the liquid crystal alignment. In addition, the liquid crystal layer 300 is divided into multiple regions according to the arrangement of the pixel electrode cutting pattern 153 and the common electrode cutting pattern 252.

Hereinafter, the first thin film transistor TR1 and the second thin film transistor TR2 of the first embodiment, and the first domain 151a and the second domain 151b connected thereto, respectively, improve visibility of the liquid crystal display panel 10. It will be described with reference to Figures 4 and 5 how it works.

FIG. 4 is an equivalent circuit diagram of the liquid crystal display panel 10 according to the first embodiment of the present invention, and FIG. 5 shows drain currents according to gate voltages of the thin film transistors TR1 and TR2 according to the first embodiment of the present invention. The graph shown.

As shown in FIG. 4, the thin film transistors TR1 and TR2 are all connected to the same gate line GL to receive the same gate voltage. It is also connected to the same data line DL and receives the same source voltage (data signal). However, the channel characteristics of both thin film transistors TR1 and TR2 are different.

The drain current I _on according to the gate voltage Vg, that is, the voltage applied to the pixel electrode layers 151a and 152b is as follows.

   Equation 1

Where Ci is the capacitance of the channel per unit area, μ is the mobility, Vg is the gate voltage, Vsd is the voltage across the source and gate, and Vth is the threshold voltage.

As in Equation 1, the drain current is proportional to the channel width / channel length (W / L). In the first embodiment, the value of W / L of the first thin film transistor TR1 is smaller than that of the second thin film transistor TR2. Accordingly, even when the same gate voltage Vg and the source voltage Vsd are applied as shown in FIG. 5, the drain current of the first thin film transistor TR1 is smaller than the drain current of the second thin film transistor TR2, and the first domain The current applied to 151a is smaller than the current applied to second domain 151b. Therefore, the liquid crystal layer 300 on the first domain 151a is less laid down than the liquid crystal layer 300 on the second domain 151b. As described above, two regions in which the liquid crystal layer 300 is laid down, that is, the transmittances are different in one pixel, may improve visibility.

The liquid crystal layer 300 connected to the first thin film transistor TR1 forms a common electrode layer 251, a first liquid crystal capacitor Clc1, and a first storage capacitor Cst1 with the common electrode line 123. On the other hand, the liquid crystal layer 300 connected to the second thin film transistor TR2 forms a common electrode layer 251, a second liquid crystal capacitor Clc2, and a second storage capacitor Cst2 with the common electrode line 123.

As described above, according to the first exemplary embodiment of the present invention, visibility is improved by dividing a pixel into two domains having different angles at which liquid crystals lie down. While the visibility is improved, the number of gate lines is the same, so that the aperture ratio can be maintained high. In addition, the transmittance does not decrease.

6A to 6C are layout views of thin film transistor substrates according to the second to fourth embodiments of the present invention, respectively, and show only the thin film transistor portion.

In the second to fourth embodiments, two thin film transistors TR1 and TR2 are formed in the pixel, and both are applied with the same gate voltage and source voltage.                     

In the second embodiment, the thin film transistors TR1 and TR2 have the same channel length L3 but different channel widths W4 and W5.

In the third embodiment, the thin film transistors TR1 and TR2 have the same channel width W6 but different channel lengths L4 and L5.

Therefore, in both the second embodiment and the third embodiment, different drain currents can be obtained through the thin film transistors TR1 and TR2 having different W / L in one pixel, thereby improving visibility.

The fourth embodiment is for the J-type thin film transistors TR1 and TR2, and also improves visibility.

As described above, according to the present invention, a PVA liquid crystal display panel with improved side visibility is provided.

Claims (7)

A liquid crystal display panel comprising a thin film transistor substrate, an insulating substrate facing the thin film transistor substrate, and a liquid crystal layer positioned between the thin film transistor substrate and the insulating substrate. The thin film transistor substrate, Gate wiring; A data line crossing the gate line to form a pixel; A first thin film transistor and a second thin film transistor positioned in the pixel and configured to receive the same gate voltage and source voltage and apply different drain currents to the liquid crystal layer; And a pixel electrode layer connected to the first thin film transistor and the second thin film transistor and having a pixel electrode cutting pattern formed thereon. The method of claim 1, The pixel electrode layer, A first domain connected to the first thin film transistor; And a second domain connected to the second thin film transistor and separated from the first domain. The method of claim 1, The area of the first domain and the second domain is substantially the same. The method of claim 1, The first thin film transistor and the second thin film transistor, the width of the channel portion is characterized in that the liquid crystal display panel.       The method of claim 1, The first thin film transistor and the second thin film transistor, the length of the channel portion is characterized in that the liquid crystal display panel.       The method of claim 1, And the liquid crystal layer is in a vertically aligned (VA) mode. The method of claim 1, And a common electrode layer having a common electrode cutting pattern formed thereon.

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