KR20080076196A - Liquid crystal display device - Google Patents

Liquid crystal display device Download PDF

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Publication number
KR20080076196A
KR20080076196A KR1020070015821A KR20070015821A KR20080076196A KR 20080076196 A KR20080076196 A KR 20080076196A KR 1020070015821 A KR1020070015821 A KR 1020070015821A KR 20070015821 A KR20070015821 A KR 20070015821A KR 20080076196 A KR20080076196 A KR 20080076196A
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KR
South Korea
Prior art keywords
gate
substrate
pixel electrode
main line
liquid crystal
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Application number
KR1020070015821A
Other languages
Korean (ko)
Inventor
김경욱
이경진
Original Assignee
삼성전자주식회사
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Publication date
Application filed by 삼성전자주식회사 filed Critical 삼성전자주식회사
Priority to KR1020070015821A priority Critical patent/KR20080076196A/en
Priority to JP2007179002A priority patent/JP5727120B2/en
Priority to US11/843,980 priority patent/US8089598B2/en
Priority to EP07016646A priority patent/EP1892697B1/en
Priority to CN2007101475633A priority patent/CN101131491B/en
Publication of KR20080076196A publication Critical patent/KR20080076196A/en

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    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1345—Conductors connecting electrodes to cell terminals
    • G02F1/13452—Conductors connecting driver circuitry and terminals of panels
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136286—Wiring, e.g. gate line, drain line
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F2201/00—Constructional arrangements not provided for in groups G02F1/00 - G02F7/00
    • G02F2201/12—Constructional arrangements not provided for in groups G02F1/00 - G02F7/00 electrode
    • G02F2201/123—Constructional arrangements not provided for in groups G02F1/00 - G02F7/00 electrode pixel
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F2202/00—Materials and properties
    • G02F2202/22—Antistatic materials or arrangements

Abstract

The present invention relates to a liquid crystal display device. A liquid crystal display according to the present invention includes a first substrate having a display area, a second substrate facing the first substrate, and a liquid crystal layer positioned between the first substrate and the second substrate. The first substrate includes a gate main line positioned in the display area; A gate outer portion positioned outside the display area and including a gate pad and a gate fan out portion; A resistance part electrically connecting the gate main line and the gate outer part and made of a material having a higher resistance than the gate main line and the gate outer part; An electrostatic bar crossing the gate outer portion; And an electrostatic diode electrically connected to the gate outer portion and the electrostatic bar. As a result, a liquid crystal display device having reduced luminance unevenness due to a gate signal delay difference is provided.

Description

Liquid crystal display {LIQUID CRYSTAL DISPLAY DEVICE}

1 is a layout view of a first substrate in a liquid crystal display according to an exemplary embodiment of the present invention.

FIG. 2 is an enlarged view of portion A of FIG. 1,

3 is a cross-sectional view taken along line III-III of FIG. 2,

4 is a diagram illustrating transmittance according to pixel voltage in a liquid crystal display according to an exemplary embodiment of the present invention.

5 is an equivalent circuit diagram of a pixel in a liquid crystal display according to an exemplary embodiment of the present invention.

6A to 6C are diagrams for describing luminance unevenness according to a gate signal delay.

FIG. 7 is a circuit diagram of part B of FIG. 1;

FIG. 8 is a layout view of part C of FIG. 7;

9 is a layout view of a portion B of FIG. 1,

10 is a cross-sectional view taken along the line VIII-VIII in FIG. 9,

FIG. 11 is a view for explaining luminance unevenness improvement in the liquid crystal display according to the exemplary embodiment of the present invention.

12 is a diagram illustrating a relationship between a gate signal delay and luminance,

13 is a view showing a change between parasitic capacitance and luminance,

14 is a diagram illustrating a gate signal delay according to a resistance value of a resistor unit;

15 is a diagram illustrating pixel voltages according to resistance values of a resistor unit.

Explanation of Signs of Major Parts of Drawings

121: gate line 122: gate electrode

123: fan-out 124: gate pad

131: gate insulating film 151: protective film

161: pixel electrode 166: pixel electrode incision pattern

163: resistor 200: second substrate

251: common electrode 252: common electrode incision pattern

300: sealant

The present invention relates to a liquid crystal display device, and more particularly, to a liquid crystal display device having improved luminance uniformity by reducing a gate signal delay difference.

The liquid crystal display device includes a first substrate on which a thin film transistor is formed, a second substrate disposed opposite to the first substrate, and a liquid crystal layer disposed therebetween.

The gate line and the data line provided on the thin film transistor substrate cross each other to form a pixel, and each pixel is connected to the thin film transistor. When the gate signal (gate on voltage Von) is applied to the gate line and the thin film transistor is turned on, the data voltage Vd applied through the data line is charged in the pixel.

The arrangement state of the liquid crystal layer is determined according to the electric field formed between the pixel voltage Vp charged in the pixel and the common voltage Vcom formed on the common electrode of the second substrate. The data voltage Vd is applied with different polarities for each frame.

The data voltage Vd applied to the pixel is dropped by the parasitic capacitance Cp between the gate electrode and the source electrode (drain electrode) to form the pixel voltage Vp. The voltage difference between the data voltage Vd and the pixel voltage Vp is called a kickback voltage Vkb.

The gate line receives a gate signal through a gate pad connected to an end of the gate line. A gate signal having a low delay is applied to a pixel adjacent to the gate pad, and a gate signal having a large delay due to the resistance of the gate line is applied to a pixel far from the gate pad.

However, the magnitude of the kickback voltage varies according to the delay level of the gate signal, and the luminance of the screen becomes uneven due to the change of the pixel voltage due to the change of the kickback voltage.

Accordingly, an object of the present invention is to provide a liquid crystal display device in which luminance unevenness due to a difference in gate signal delay is reduced.

An object of the present invention is to provide a liquid crystal display device comprising a first substrate having a display area, a second substrate facing the first substrate, and a liquid crystal layer positioned between the first substrate and the second substrate. The first substrate may include a gate main line positioned in the display area; A gate outer portion positioned outside the display area and including a gate pad and a gate fan out portion; A resistance part electrically connecting the gate main line and the gate outer part and made of a material having a higher resistance than the gate main line and the gate outer part; An electrostatic bar crossing the gate outer portion; And a capacitive diode electrically connected to the gate periphery and the electrostatic bar.

The first substrate may include a thin film transistor connected to the gate main line; The pixel electrode may further include a pixel electrode electrically connected to the thin film transistor, and the resistor unit may be made of the same material as the pixel electrode.

The resistance unit preferably includes indium tin oxide (ITO) or indium zinc oxide (IZO).

Preferably, the resistance unit is provided with a smaller resistance value as the distance between the gate main line connecting the gate pad and the gate pad is increased.

Preferably, the gate main line and the gate outer portion are formed of the same layer.

The first substrate may include: a storage electrode line positioned in the display area and extending in parallel with the gate main line; The display device may further include a common voltage line positioned outside the display area and crossing the gate outer portion to supply a common voltage to the sustain electrode line, wherein the electrostatic bar includes the common voltage line.

The electrostatic diode includes: a first electrostatic diode having the gate outer portion as a control terminal and an input terminal and the electrostatic bar as an output terminal; Preferably, the gate outer portion includes an output terminal and a second electrostatic diode including the electrostatic bar as a control terminal and an input terminal.

It is preferable to further include a sealant which is formed on the fan-out part and which couples the first substrate and the second substrate.

At least a part of the resistance portion is preferably formed in a zigzag.

The liquid crystal layer is preferably in VA (vertical alignment) mode.

The pixel electrode may include a pixel electrode cutting pattern, and the second substrate may include a common electrode on which a common electrode cutting pattern is formed.

The pixel electrode includes a first pixel electrode and a second pixel electrode which are separated from each other, and different pixel voltages are applied to the first pixel electrode and the second pixel electrode.

The thin film transistor includes a drain electrode, and the drain electrode includes a first drain electrode applying a data voltage directly to the first pixel electrode and a second pixel electrode forming a coupling capacitance with the second pixel electrode. desirable.

The thin film transistor may include a first thin film transistor connected to the first pixel electrode and a second thin film transistor connected to the second pixel electrode.

The total resistance of the resistor unit is preferably 10% to 50% of the total resistance of the gate main line.

The change in the gate signal delay of the gate main line is preferably within 100%.

Hereinafter, the present invention will be described in more detail with reference to the accompanying drawings. Hereinafter, a film is formed (located) on top of another film, not only when two films are in contact with each other but also when another film is between two layers. It also includes cases that exist.

A liquid crystal display according to the present invention will be described with reference to FIGS. 1 to 3.

The liquid crystal display device 1 is positioned between the first substrate 100 on which the thin film transistor T is formed, the second substrate 200 facing the first substrate 100, and both substrates 100 and 200. And a sealant 400 for bonding the liquid crystal layer 300 and both substrates 100 and 200.

The first substrate 100 is divided into a display area and a non-display area surrounding the display area. The gate line 121 of the display area is connected to the gate pad 124 through the fan-out part 123 of the non-display area.

First, the first substrate 100 will be described.

Gate wiring is formed on the first insulating substrate 111. The gate wiring can be a metal single layer or multiple layers. The gate wiring is located in the display area and extends in the horizontal direction to the gate main line 121, the gate electrode 122 connected to the gate main line 121, and the fan-out extending from the gate main line 121 to the non-display area. A gate pad 124 connected to the end of the unit 123 and the fan-out unit 123 and a storage electrode line (storage electrode line 125) extending in parallel with the gate line 121 are included.

The gate pad 124 is connected to a gate driver (not shown) to receive a gate signal. The gate pad 124 is larger in width than the gate main line 121.

On the first insulating substrate 111, a gate insulating layer 131 made of silicon nitride (SiNx) or the like covers the gate wiring.

A semiconductor layer 132 made of a semiconductor such as amorphous silicon is formed on the gate insulating layer 131 of the gate electrode 122, and n + is doped with silicide or n-type impurities at a high concentration on the semiconductor layer 132. An ohmic contact layer 133 made of a material such as hydrogenated amorphous silicon is formed. The ohmic contact layer 133 is removed from the channel portion between the source electrode 142 and the drain electrode 143.

The data line is formed on the ohmic contact layer 133 and the gate insulating layer 131. The data line may also be a single layer or multiple layers of a metal layer. The data line is a branch of the data line 141 and the data line 141 which are formed in the vertical direction and intersect the gate line 121 to form a pixel, and extends to the upper portion of the ohmic contact layer 133. And a fan-out separated from the source electrode 142 and extending from the data line 141 to the non-display area of the drain electrode 143 and the data line 141 formed on the opposing contact layer 133 opposite to the source electrode 142. A data pad 145 connected to the end of the unit 144 and the fan-out unit 144, and a common voltage line 146 parallel to the data line 141 and crossing the gate outer portion 146 (see FIG. 7). do.

As illustrated in FIG. 7, the gate outer part includes a gate pad 124 and a fan out part 123 located at the outer side of the resistor unit 163. The common voltage line 146 receives a common voltage through the common voltage pad formed adjacent to the data pad 145 and supplies the common voltage to the sustain electrode line 125.

The common voltage applied to the sustain electrode line 125 may be the same as or different from the common voltage applied to the common electrode 251. The storage electrode line 125 is electrically connected to the storage electrode line 125 through a bridge (not shown) made of a transparent conductive material.

The data pad 145 is connected to a data driver (not shown) and receives a data driving signal. The data pad 145 is larger in width than the data main line 141.

The passivation layer 151 is formed on the data line and the semiconductor layer 132 that does not cover the data line. A contact hole 152 exposing the drain electrode 143 is formed in the passivation layer 151. 7 and 8, contact holes 153, 154, and 155 are further formed in the passivation layer 151, and the gate insulating layer 131 is also removed therein.

The pixel electrode 161 is formed on the passivation layer 151. The pixel electrode 161 is usually made of a transparent conductive material such as indium tin oxide (ITO) or indium zinc oxide (IZO). The pixel electrode 161 is connected to the drain electrode 143 through the contact hole 152. The pixel electrode cut pattern 166 is formed on the pixel electrode 161.

The pixel electrode cutout pattern 166 of the pixel electrode 161 divides the liquid crystal layer 300 into a plurality of regions together with the common electrode cutout pattern 252 described later.

Next, the second substrate 200 will be described.

The black matrix 221 is formed on the second insulating substrate 211. The black matrix 221 generally distinguishes between red, green, and blue filters, and serves to block direct light irradiation to the thin film transistor positioned on the first substrate 100. The black matrix 221 is usually made of a photosensitive organic material to which black pigment is added. As the black pigment, carbon black or titanium oxide is used.

The color filter 231 is formed by repeating the red, green, and blue filters with the black matrix 221 as the boundary. The color filter 231 serves to impart color to light emitted from the backlight unit (not shown) and passed through the liquid crystal layer 300. The color filter 231 is usually made of a photosensitive organic material.

An overcoat layer 241 is formed on the black matrix 221 not covered by the color filter 231 and the color filter 231. The overcoat layer 241 serves to protect the color filter 231 while planarizing the color filter 231. The overcoat layer 241 may be a photosensitive acrylic resin.

The common electrode 251 is formed on the overcoat layer 241. The common electrode 251 is made of a transparent conductive material such as indium tin oxide (ITO) or indium zinc oxide (IZO). The common electrode 251 directly applies a voltage to the liquid crystal layer 300 together with the pixel electrode 161 of the thin film transistor substrate.

The common electrode cutting pattern 252 is formed on the common electrode 251. The common electrode cutout pattern 252 divides the liquid crystal layer 300 into a plurality of regions together with the pixel electrode cutout pattern 166 of the pixel electrode 161.

The pixel electrode cut pattern 166 and the common electrode cut pattern 252 may be formed in various shapes without being limited to the exemplary embodiments. In another embodiment, a protrusion may be provided instead of the cutting patterns 166 and 252 to divide the liquid crystal layer 300 into a plurality of regions.

The liquid crystal layer 300 is positioned between the first substrate 100 and the second substrate 200. The liquid crystal layer 300 is a VA (vertically aligned) mode, and the liquid crystal molecules are vertical in the length direction when no voltage is applied. When voltage is applied, the liquid crystal molecules lie perpendicular to the electric field because the dielectric anisotropy is negative.

However, when the incision patterns 166 and 252 are not formed, the liquid crystal molecules are arranged in a random order in various directions because the azimuth angles of the lying are not determined, and a foreground line is formed at the boundary planes having different alignment directions. The cutting patterns 166 and 252 form a fringe field when a voltage is applied to the liquid crystal layer 300 to determine the azimuth angle of the liquid crystal alignment. In addition, the liquid crystal layer 300 is divided into multiple regions according to the arrangement of the cutting patterns 166 and 252.

The liquid crystal display device 1 according to the first embodiment is a normally black mode, and the transmittance according to the pixel voltage is shown in FIG. 4. The change in transmittance at low gradation shown in part C of FIG. 4 is about three times faster than that of TN (twisted nematic) liquid crystal.

In the liquid crystal display device 1 described above, the gate main line 121 receives a gate signal through a gate pad 124 connected to an end thereof. The gate signal having a low delay is applied to the thin film transistor T adjacent to the gate pad 124 by the resistance of the gate main line 121, that is, the thin film transistor T on the left side. On the other hand, a gate signal with a large delay is applied to the thin film transistor T far from the gate pad 123, that is, the thin film transistor T on the right side.

The change in the screen brightness according to the difference in the gate signal delay will be described with reference to FIGS. 5 to 6C.

The kickback voltage Vkb is expressed by Equation 1 as follows.

Equation 1

Vkb = (Von-Voff) * Cp / (Clc + Cst + Cp)

3 and 5, Cp is the parasitic capacitance (Cgs) between the gate electrode and the source electrode + parasitic capacitance (Cgd) between the gate electrode and the drain electrode, Clc is the liquid crystal capacitance, Cst is the storage capacitance, Von is the gate-on voltage , Voff represents the gate off voltage.

If the gate signal delay is large, the gate-on voltage is poorly applied and the kickback voltage is decreased, and the kickback voltage is larger when the negative pixel voltage is applied than when the positive pixel voltage is applied.

6A and 6B illustrate kickback voltages for pixels on the left of the display area having a small delay of the gate signal and pixels on the right of the display area having a large delay of the gate signal, respectively.

In the case of the left pixel illustrated in FIG. 6A, the kickback voltage is 1V when the positive pixel voltage is applied, and the kickback voltage is 1.2V when the negative pixel voltage is applied. In the case of the right pixel shown in Fig. 8B, the kickback voltage is 0.8V both when the positive pixel voltage is applied and when the negative pixel voltage is applied.

Accordingly, the root mean square pixel voltage at which the left pixel is finally left in the pixel becomes larger, and the screen corresponding to the left pixel is more brightly recognized.

Referring to FIG. 6C, the closer to the gate pad 124, the smaller the gate signal delay and the larger the kickback voltage Vkb. On the other hand, the further away from the gate pad 124, the greater the gate signal delay and the smaller the kickback voltage Vkb. Therefore, the left pixel is brighter because the root mean square pixel voltage is larger than that of the right pixel.

As described above, the brightness of the left and right sides of the screen is changed, and thus a horizontal line is recognized. This problem is further exacerbated in a large liquid crystal display device in which the gate main line 121 is long and a large gate signal delay occurs.

In the first embodiment of the present invention, the problem caused by the gate delay difference is solved by forming the resistor unit 163 between the gate main line 121 and the gate pad 124.

The resistor unit 163 will be described with reference to FIGS. 7 to 11. In FIG. 9, the electrostatic diode 170 is not shown.

The resistor unit 163 is positioned between the gate outer portion and the gate main line 121 in the non-display area. The resistor unit 163 is formed of the same layer as the pixel electrode 161, and includes a first portion 163a connected to the gate outer portion, a second portion 163b and a first portion connected to the gate main line 121. And a third portion 163c positioned between 163a and second portion 163b.

The first portion 163a contacts the fan-out portion 123 through the contact hole 154, and the second portion 163b contacts the gate main line 121 through the contact hole 155.

The gate pad 124 exposed by the contact hole 153 is covered by a contact member 162 made of the same layer as the pixel electrode 161.

The resistor unit 163 is made of ITO, IZO, or the like, and these materials have a higher resistance than the metal materials forming the gate main line 121. Due to the resistor 163 having a large resistance, a delay is already generated as shown in FIG. 11 before the gate signal enters the display area.

Therefore, the delay variation of the gate signal and the variation of the kickback voltage Vkb decrease. In addition, the luminance difference on the left and right of the display area is also reduced.

The total resistance of the gate main line 121 is typically 4000 Ω to 7000 Ω, and the total resistance of the resistor unit 163 may be 10% to 50% of the total resistance of the gate main line 121. The resistance value of the resistor unit 163 may be changed by adjusting the thickness, width, and length of the resistor unit 163.

The resistance value of the resistor unit 163 is preferably determined so that the change in the gate delay is within 100%, that is, the gate delay value of the rightmost pixel of the display area is less than twice the gate delay value of the leftmost pixel of the display area. Do.

On the other hand, the distance between the gate main line 121 and the gate pad 124 varies, which causes a problem in that the luminance is changed due to a change in resistance between the gate main line 121 and the gate pad 124.

The length of the third portion 163c of the resistor unit 163 is provided in inverse proportion to the distance between the corresponding gate main line 121 and the gate pad 124. As a result, unevenness in luminance due to the difference in distance between the gate main line 121 and the gate pad 124 is reduced.

The sealant 400 is located on the fan-out part 123, and the resistor part 163 is located in the sealant 400. Since the resistor unit 163 is not exposed to the outside, the problem of corrosion of the resistor unit 163 does not occur.

In the manufacturing process, the static electricity flowing from the outside may cause a problem of damaging the thin film transistor (T). According to the first embodiment, the static electricity introduced through the gate pad 124 may be dissipated to some extent in the resistor 163 having a large resistance, thereby reducing the problem caused by static electricity.

In another embodiment, the resistor unit 163 may be formed of another material having a higher resistance than the gate main line 121, separately from the pixel electrode 161. In another embodiment, the shape of the resistor unit 163 is the same, and the distance difference between the gate main line 121 and the gate pad 124 may be solved by changing the shape of other parts such as the fan-out unit 123. have.

7, the electrostatic diode 170 is formed on the outer side of the resistor unit 163 and is electrically connected to the gate outer side and the common voltage line 146. If static electricity flows through the gate pad 124 during the manufacturing process, the resistance unit 163 having a large resistance may be damaged, and disconnection may occur. The electrostatic diode 170 disperses the static electricity flowing therein to prevent breakage of the resistor unit 163.

The electrostatic diode 170 has a form of a thin film transistor and includes a first capacitive diode 171 and a second capacitive diode 172. The first capacitive diode 171 is provided such that current flows only from the gate outer portion to the common voltage line 146, and the second capacitive diode 172 is provided so that current flows only from the common voltage line 146 to the gate outer portion. .

Referring to the function of the electrostatic diode 170, the static electricity introduced from the outside flows to the common voltage line 146 through the first electrostatic diode 171, and the static electricity introduced to the common voltage line 146 again passes through the second electrostatic diode 172. Flow outside the gate. While repeating this process, static electricity is dispersed to prevent breakage of the resistor unit 163.

Referring to Figure 8 will be described in detail the configuration of the electrostatic diode 170. In the electrostatic diode 170, the common voltage line 146 serves as an electrostatic bar.

In the first diode 171, the control terminal 1711 and the input terminal 1712 are connected to a gate outer portion, and the output terminal 1713 is connected to the common voltage line 146. The bridge 1714 connects the input terminal 1712 and the gate outer portion. When static electricity is input to the outer portion of the gate, the control terminal 1711 connected to the gate outer portion is turned on and the static electricity flows to the common voltage line 146 connected to the output terminal 1713.

The second diode 172 is connected to the control terminal 1721 and the input terminal 1722 to the common voltage line 146, the output terminal 1713 is connected to the gate outer portion. The bridge 1724 connects the common voltage line 146 and the control terminal 1721, and the bridge 1725 connects the output terminal 1723 with the gate outer portion. When static electricity is input to the gate outer portion, the control terminal 1721 connected to the gate outer portion through the bridge 1724 is turned on, and the static electricity flows back to the gate outer portion through the bridge 1725 connected to the output terminal 1723.

In another embodiment, the electrostatic diode 170 may be formed of only the first electrostatic diode 171 without the second electrostatic diode 172. In this case, the static electricity input through the gate outer portion is distributed to the common voltage line 146.

Hereinafter, the reason why the gate signal delay is adjusted to adjust the luminance nonuniformity will be described.

12 illustrates luminance according to a gate signal delay value in a non-display area. Luminance represents the deviation ratio between the luminance on the left side of the display area and the luminance on the right side of the display area relative to the luminance in the center portion. A larger value indicates a smaller luminance difference.

12, when the gate signal delay increases by about 43% (2.55 GHz to 3.67 GHz), the luminance deviation increases by about 64% (30.6% to 50.3%).

FIG. 13 shows luminance according to Cp / (Clc + Cst + Cp) proportional to the kickback voltage. Luminance represents the deviation ratio between the luminance on the left side of the display area and the luminance on the right side of the display area relative to the luminance in the center portion. A larger value indicates a smaller luminance difference.

Referring to FIG. 13, when Cp / (Clc + Cst + Cp) increases by 24% (0.037 to 0.046), the luminance deviation increases by about 26.4% (35.6% to 45%).

12 and 13, it is understood that it is effective to increase the gate signal delay value in the non-display area in order to improve the luminance nonuniformity.

The gate signal delay and the pixel voltage are changed by the resistance in the non-display area, that is, the resistance from the gate pad to the main line, which will be described with reference to FIGS. 14 and 15. 14 and 15, the resistance in the non-display area has four values of 1/6 kΩ, 1/3 kΩ, 1/2 kΩ, and 2/3 kΩ. The data indicated by 0 kΩ is a case where no resistance portion exists and the gate main line and the gate pad are integrally formed.

14, it can be seen that as the resistance of the non-display area increases, the gate signal delay value increases as a whole. On the other hand, as the non-display area resistance increases, the right gate signal delay value / left gate signal delay value decreases. That is, in the case of 0 kΩ, the right gate signal delay value / left gate signal delay value is 6.53 (4.18 / 0.64), whereas in the case of 2/3 kΩ, the right gate signal delay value / left gate signal delay value is 1.77 (8.12 / 4.57).

15, it can be seen that as the non-display area resistance increases, the pixel voltage becomes smaller as a whole. On the other hand, as the resistance of the resistor increases, the left pixel voltage / right pixel voltage decreases. That is, in the case of 0 kΩ, the left pixel voltage / right pixel voltage is 1.028 (3.3 / 3.21), whereas in the case of 2/3 kΩ, the left pixel voltage / right pixel voltage is 1.012 (3.19 / 3.15).

It can be seen from FIG. 14 and FIG. 15 that the gate signal delay and the pixel voltage can be made constant by increasing the non-display area resistance. However, since the gate signal transmission becomes difficult when the non-display area resistance increases, the non-display area resistance should be determined in consideration of the total resistance of the gate main line 121 and the like.

Although embodiments of the present invention have been shown and described, it will be apparent to those skilled in the art that the present embodiments may be modified without departing from the spirit or principles of the present invention. It is intended that the scope of the invention be defined by the claims appended hereto and their equivalents.

As described above, according to the present invention, there is provided a liquid crystal display device in which luminance unevenness due to a gate signal delay difference is reduced.

Claims (16)

A liquid crystal display device comprising a first substrate having a display area, a second substrate facing the first substrate, and a liquid crystal layer positioned between the first substrate and the second substrate. The first substrate, A gate main line positioned in the display area; A gate outer portion positioned outside the display area and including a gate pad and a gate fan out portion; A resistance part electrically connecting the gate main line and the gate outer part and made of a material having a higher resistance than the gate main line and the gate outer part; An electrostatic bar crossing the gate outer portion; And a capacitive diode electrically connected to the gate outer portion and the electrostatic bar. The method of claim 1, The first substrate, A thin film transistor connected to the gate main line; Further comprising a pixel electrode electrically connected to the thin film transistor, And the resistor unit is made of the same material as the pixel electrode. The method of claim 2, The resistor unit includes indium tin oxide (ITO) or indium zinc oxide (IZO). The method according to any one of claims 1 to 3, And the resistance is smaller as the distance between the gate main line and the gate pad connecting the resistor unit increases. The method according to any one of claims 1 to 3, And the gate main line and the gate outer portion are formed of the same layer. The method of claim 5, The first substrate, A storage electrode line positioned in the display area and extending in parallel with the gate main line; A common voltage line positioned outside the display area and crossing the gate outer portion and supplying a common voltage to the sustain electrode line; And the electrostatic bar includes the common voltage line. The method of claim 5, The electrostatic diode, A first capacitive diode having the gate outer portion as a control terminal and an input terminal and the electrostatic bar as an output terminal; And a second capacitive diode having the gate outer portion as an output terminal and the electrostatic bar as a control terminal and an input terminal. The method of claim 5, And a sealant formed on the fan-out part, the sealant coupling the first substrate and the second substrate. The method according to any one of claims 1 to 3, At least a portion of the resistor unit is formed in a zigzag. The method according to any one of claims 1 to 3, And said liquid crystal layer is in VA (vertical alignment) mode. The method of claim 10, The pixel electrode has a pixel electrode incision pattern formed thereon, And the second substrate includes a common electrode having a common electrode cutting pattern formed thereon. The method of claim 11, The pixel electrode includes a first pixel electrode and a second pixel electrode which are separated from each other, and different pixel voltages are applied to the first pixel electrode and the second pixel electrode. The method of claim 12, The thin film transistor includes a drain electrode, And the drain electrode includes a first drain electrode applying a data voltage directly to the first pixel electrode and a second pixel electrode forming a coupling capacitance with the second pixel electrode. The method of claim 12, The thin film transistor includes a first thin film transistor connected to the first pixel electrode and a second thin film transistor connected to the second pixel electrode. The method according to any one of claims 1 to 3, Wherein the total resistance of the resistor unit is 10% to 50% of the total resistance of the gate main line. The method according to any one of claims 1 to 3, Liquid crystal display device characterized in that the change in the gate signal delay of the gate main line is within 100%
KR1020070015821A 2006-08-25 2007-02-15 Liquid crystal display device KR20080076196A (en)

Priority Applications (5)

Application Number Priority Date Filing Date Title
KR1020070015821A KR20080076196A (en) 2007-02-15 2007-02-15 Liquid crystal display device
JP2007179002A JP5727120B2 (en) 2006-08-25 2007-07-06 Liquid crystal display
US11/843,980 US8089598B2 (en) 2006-08-25 2007-08-23 Liquid crystal display device having delay compensation
EP07016646A EP1892697B1 (en) 2006-08-25 2007-08-24 Liquid crystal display device having delay compensation
CN2007101475633A CN101131491B (en) 2006-08-25 2007-08-27 Liquid crystal display device having delay compensation

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR101490485B1 (en) * 2008-10-30 2015-02-05 삼성디스플레이 주식회사 Liquid crystal display and method of manufacturing the same

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR101490485B1 (en) * 2008-10-30 2015-02-05 삼성디스플레이 주식회사 Liquid crystal display and method of manufacturing the same

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