JP2012226156A - Liquid crystal display device and mother board - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a liquid crystal display device with excellent appearance.SOLUTION: A liquid crystal display device includes: an array substrate 20; a counter substrate 10 facing the array substrate 20; a liquid crystal layer LQ held between the array substrate 20 and the counter substrate 10; a display portion DYP including a plurality of display pixels PX arranged in matrix; and a frame portion FRM surrounding the display portion DYP. The array substrate 20 includes: a first wire COM disposed in the frame portion FRM and including a lightning conductor pattern 24 extending in a direction away from the display portion DYP; connection pads 26A and 26B; tester pads PDC and PDV; and tester wires WC, WV, and Wcom disposed on a side opposite to the tester pads PDC and PDV with respect to the display portion DYP. The lightning conductor pattern 24 overlaps with at least a part of the tester wires WC, WV, and Wcom via an insulation layer L1.

Description

  Embodiments described herein relate generally to a liquid crystal display device and a mother substrate.

  The liquid crystal display device includes a display unit including display pixels arranged in a matrix, an array substrate, a counter substrate disposed to face the array substrate, and a liquid crystal sandwiched between the array substrate and the counter substrate. And a layer.

  In the liquid crystal display device, after aligning and bonding a first mother substrate serving as a plurality of array substrates and a second mother substrate serving as a plurality of counter substrates, a pair of opposing array substrates and counter substrates are cut out. Formed.

  In the region to be the array substrate of the first mother substrate, a plurality of pixel electrodes arranged in a matrix, a plurality of scanning lines arranged along the row direction in which the pixel electrodes are arranged, and a column in which the pixel electrodes are arranged A plurality of signal lines arranged along the direction, and a pixel switch that switches electrical connection between the signal line and the pixel electrode by a signal applied from the scanning line are arranged.

  In a region to be an array substrate, a driving circuit that drives display pixels via a plurality of scanning lines and a plurality of signal lines, and a video signal and a control signal are input around a display portion where a plurality of pixel electrodes are arranged. Various wirings are arranged.

  A tester pad for inputting a test signal to the display pixel, the drive circuit, and various wirings is further disposed on the first mother substrate.

JP 2003-29296 A

  In order to cut out more array substrates from one first mother substrate, adjacent array substrates may be arranged without a gap. In this case, since it becomes impossible to arrange the tester pad between the regions to be the array substrate, the tester pad is arranged in the region around the display unit, and the inspection switch is arranged in the region around the display unit of the adjacent array substrate. Alternatively, the array tester wiring extending from the tester pad may be routed and arranged.

  If static electricity is generated in the array tester wiring placed on the adjacent array substrate after the liquid crystal display device manufacturing process, module assembly process, or module completion, the light shielding layer pattern placed around the display part is partially due to electrostatic energy. It disappeared and pinholes were generated. A plurality of pinholes are generated at random locations, which are visually recognized as bright spots, which may cause poor appearance.

  In particular, when the light shielding layer is disposed on the array substrate side, the electrostatic energy generated between the array tester wires is likely to be transmitted to the light shielding layer, which often results in poor appearance.

  The present invention has been made in view of the above circumstances, and an object thereof is to provide a liquid crystal display device having good appearance and a mother substrate thereof.

  According to the embodiment, an array substrate, a counter substrate arranged to face the array substrate, a liquid crystal layer sandwiched between the array substrate and the counter substrate, and a plurality of arranged in a matrix A display portion including a display pixel; and a frame portion surrounding the display portion, wherein the array substrate is disposed on the frame portion and has a lightning rod pattern extending in a direction away from the display portion; A connection pad electrically connectable to a signal source; a tester pad to which a test signal is input; and a tester wiring disposed at a position facing the tester pad with respect to the display unit. There is provided a liquid crystal display device overlapping with at least a part of the tester wiring via an insulating layer.

It is a figure for demonstrating the example of 1 structure of the liquid crystal display device of embodiment. It is a figure for demonstrating one structural example of the pixel switch of the liquid crystal display device of embodiment. It is a figure for demonstrating one structural example before cutting out an array board | substrate from a 1st mother board | substrate. FIG. 2 is a diagram for explaining a configuration example of a tester wiring and a common wiring of the liquid crystal display device shown in FIG. 1. It is a figure which shows an example of the cross section of the array board | substrate in line IV-IV shown in FIG.

Hereinafter, embodiments will be described with reference to the drawings.
FIG. 1 shows a configuration example of a liquid crystal display device according to this embodiment. The liquid crystal display device according to the present embodiment is disposed so as to face the display unit DYP including the display pixels PX arranged in a matrix, the frame portion FRM surrounding the display unit DYP, the array substrate 20, and the array substrate 20. And the liquid crystal layer LQ sandwiched between the array substrate 20 and the counter substrate 10.

  The array substrate 20 includes an insulating substrate 200 (shown in FIG. 2), scanning lines Y (Y1, Y2,...) Extending along a row arranged on the insulating substrate 200 and arranged with the display pixels PX, and a display A signal line X (X1, X2,...) Extending along a column in which the pixels PX are arranged, a pixel electrode PE disposed in each display pixel PX, a pixel switch SW, and a scanning line driving circuit that drives the scanning line Y. YD, a signal line driving circuit XD for driving the signal line X, OLB (Outer Lead Bonding) pads 26A and 26B, a tester pad, a common wiring COM surrounding the display unit DYP, and a video signal to the signal line driving circuit XD And various wirings including a wiring for supplying a control signal and a wiring for supplying a control signal to the scanning line driving circuit YD.

  The pixel electrode PE is formed of a transparent electrode material, for example, ITO (Indium Tin Oxide), IZO (indium zinc oxide), or the like.

  The pixel switch SW is disposed in the vicinity of the position where the scanning line Y and the signal line X intersect, and switches the electrical connection between the signal line X and the pixel electrode PE based on a signal applied from the scanning line Y. The pixel switch SW includes a thin film transistor including a semiconductor layer 210 (shown in FIG. 2) made of, for example, polysilicon or amorphous silicon.

FIG. 2 shows a configuration example of the pixel switch SW of the liquid crystal display device of the present embodiment.
The gate electrode GE of the pixel switch SW is disposed on the insulating substrate 200 together with the scanning line Y and the like. The gate electrode GE is covered with a gate insulating film (insulating layer L1). The gate insulating film L1 is made of, for example, silicon nitride (Si ₃ N ₄ ).

The semiconductor layer 210 of the pixel switch SW is disposed on the gate insulating film L1. The source electrode SE and the drain electrode DE of the pixel switch SW are in contact with the semiconductor layer 210. These source electrode SE and drain electrode DE are covered with a passivation film L2. The passivation film L2 is formed of, for example, silicon nitride (Si ₃ N ₄ ).

  The gate electrode GE of the pixel switch SW is electrically connected to the corresponding scanning line Y. The source electrode SE of the pixel switch SW is electrically connected to the corresponding signal line X. The drain electrode DE of the pixel switch SW is electrically connected to the corresponding pixel electrode PE in a contact hole provided in the passivation film L2.

  The scanning line driving circuit YD includes a first scanning line driving circuit YDR and a second scanning line driving circuit YDL disposed on both sides of the display unit DYP in the direction in which the scanning line Y extends. The first scanning line driving circuit YDR and the second scanning line driving circuit YDL supply scanning signals from both ends of the plurality of scanning lines Y.

  The signal line X is electrically connected to the signal line drive circuit XD. The signal line drive circuit XD outputs a video signal supplied from an external signal source (not shown) to the corresponding signal line X.

  OLB (Outer Lead Bonding) pads 26A and 26B are, for example, connection pads that are electrically connected to one end of a connection member such as a flexible wiring board and electrically connected to an external signal source such as a timing controller via the connection member. It is. Common wiring COM and various other wirings are electrically connected to the OLB pads 26A and 26B. Signals supplied from an external signal source are applied to various wirings via OLB pads 26A and 26B. In the present embodiment, two OLB pads 26 </ b> A and 26 </ b> B are arranged on the frame portion FRM of the array substrate 20.

  FIG. 3 shows a configuration example of a mother substrate that becomes a plurality of array substrates 20. In FIG. 3, configurations other than the OLB pads 26A and 26B, the tester pads PDV and PDC, the tester wirings WV, WC, Wcom, and the common wiring COM are omitted.

  The plurality of array substrates 20 are formed such that there are no gaps between adjacent substrates. The array substrate 20 includes a first region 20A in which a plurality of pixel electrodes PE are arranged in a matrix, and a second region 20B surrounding the first region 20A. By bonding the array substrate 20 and the counter substrate 10 to face each other, the first region 20A forms the display portion DYP, and the second region 20B forms the frame portion FRM.

The tester pad includes a plurality of video pads PDV for inputting test signals to the OLB pads 26A and 26B, and a plurality of control pads PDC.
A test video signal is input to the video pad PDV when the probe of the test apparatus comes into contact therewith. The video pad PDV may include a plurality of pads. Before the array substrate 20 is cut out, the tester wiring WV is electrically connected between the video pad PDV (or each of a plurality of pads) and the OLB pads 26A and 26B.

  The control pad PDC is contacted by a probe of a test apparatus, and a test control signal and a test common voltage are input. In a state before the array substrate 20 is cut out, the tester wiring WC and the tester wiring Wcom are electrically connected between the control pad PDC and the OLB pads 26A and 26B. The control pad PDC may include a plurality of pads to which a plurality of tester wirings WC are connected and a pad to which tester wirings Wcom are connected. A test control signal is input to the tester wiring WC, and a test common voltage is input to the tester wiring Wcom.

  The number of video pads PDV and control pads PDC is not limited to the illustrated number, and the number of video pads PDV and control pads PDC may be adjusted according to the number of types of signals input to the OLB pads 26A and 26B.

  All of the tester wirings WV, WC, and Wcom extend from the tester pads PDV and PDC to the OLB pads 26A and 26B through the second region of the adjacent array substrate. The video pad PDV and the OLB pads 26A and 26B may be switchable in electrical connection by a test switch (not shown) provided on the tester wiring WV. The control pad PDC and the OLB pads 26A and 26B may be switchable in electrical connection by a test switch (not shown) provided in the tester wirings WC and Wcom. A signal for switching the test switch is supplied from the control pad PDC or the video pad PDV.

  In FIG. 1 and FIG. 3, the tester wirings WV and WC are drawn by one line, but each has a plurality of wirings.

  In the frame portion FRM, a black matrix BM (shown in FIG. 5) is arranged so as to surround the display portion DYP above the common wiring COM and various wirings of the array substrate 20.

  The counter substrate 10 includes a counter electrode CE arranged to face a plurality of pixel electrodes PE. The counter electrode CE is formed of a transparent electrode material, for example, ITO (Indium Tin Oxide), IZO (indium zinc oxide), or the like. A common voltage is applied to the counter electrode CE from the common wiring COM of the array substrate 20 via a conductive member such as a conductive paste (not shown).

  In the case of a color display type liquid crystal display device, the plurality of display pixels PX have a plurality of types of color display pixels, for example, a red pixel that displays red, a green pixel that displays green, and a blue pixel that displays blue. That is, the red pixel includes a red color filter (not shown) that transmits light having a red main wavelength. The green pixel includes a green color filter that transmits light having a green dominant wavelength. The blue pixel includes a blue color filter that transmits light having a blue main wavelength. These color filters are arranged on the main surface of the array substrate 20 or the counter substrate 10.

  A pair of alignment films (not shown) facing each other are disposed on the plurality of pixel electrodes PE and the counter electrode CE. The surfaces of the pair of alignment films are rubbed in a predetermined direction in order to define the alignment state of the liquid crystal molecules contained in the liquid crystal layer LQ.

  The array substrate 20 and the counter substrate 10 are fixed with a predetermined gap by a seal member SL. The seal member SL is disposed so as to surround the display unit DYP, and is partially opened to form an injection port. The inlet is sealed with a sealant after the liquid crystal material is injected.

  Here, when static electricity is generated in the tester wirings WV, WC, and Wcom after the manufacturing process, the module assembly process, and the module of the liquid crystal display device, the black matrix BM disposed around the display unit DYP is partially caused by the electrostatic energy. It disappeared and pinholes were generated. A plurality of pinholes are generated at random locations, which are visually recognized as bright spots, which may cause poor appearance.

  Therefore, in the present embodiment, the common wiring COM includes the lightning rod pattern 24. The lightning rod pattern 24 extends from the common line COM in a direction away from the display unit DYP. The tester wiring WC and the lightning rod pattern 24 are arranged so as to overlap with each other through the insulating layer L1.

FIG. 4 shows an example of the positional relationship between the lightning rod pattern 24 and the tester wiring WC in the vicinity of the lightning rod pattern 24.
FIG. 5 shows an example of a cross section taken along line IV-IV shown in FIG.

  The common wiring COM includes two lightning rod patterns 24. In the present embodiment, the lightning rod pattern 24 is provided in the lower layer of the inlet provided in the seal member SL. The common wiring COM includes a ground pattern 25 serving as a ground for the injection port, and the two lightning rod patterns 24 extend from the ground pattern 25 in a direction substantially orthogonal to the direction in which the common wiring COM extends.

The common wiring COM is disposed in the same layer as the scanning line Y. The insulating layer L1 disposed on the common wiring COM is an inorganic layer such as silicon nitride (Si ₃ N ₄ ) and has a thickness of 0.3 to 0.8 μm. A plurality of insulating layers may be disposed between the lightning rod pattern 24 and the tester wiring WC. The tester wiring WC is arranged in the same layer as the signal line X. A black matrix BM is arranged on the tester wiring WC. The black matrix BM is a light shielding layer formed of, for example, a resin colored black.

  As described above, when the common wiring COM includes the lightning rod pattern 24, the tester wiring WC and the lightning rod pattern 24 overlap even if static electricity accumulates in the tester wiring WC after completion of the manufacturing process, the module assembly process, and the module. A pinhole of the black matrix BM is likely to be generated due to electrostatic energy only in the upper layer of the portion. Therefore, conventionally, a plurality of randomly generated pinholes are generated only in the vicinity of the position where the lightning rod pattern 24 and the tester wiring WC overlap.

  In the present embodiment, the lightning rod pattern 24 extends in a direction away from the first region 20A included in the display unit DYP and overlaps the tester wiring WC, so that the pinhole generated in the black matrix BM is in the vicinity of the display unit DYP. No bright spots due to pinholes are seen.

  It should be noted that the position where the lightning rod pattern 24 and the tester wiring WC overlap is preferably separated from the display unit DYP. On the other hand, it is desirable that the lightning rod pattern 24 overlaps at least one of the tester wirings WV, Wcom, and WC that is disposed in the vicinity of the first region 20A. Therefore, in the present embodiment, the tester wiring WC is routed outward from the first region 20A side and overlaps the lightning rod pattern 24 at a position away from the first region 20A.

  3 to 5, only the lightning rod pattern 24 that overlaps with the tester wiring WC is shown, but a lightning rod pattern that overlaps with each of the tester wirings WV and Wcom may be further provided.

  In the manufacturing process of the liquid crystal display device, when testing a drive circuit and various wirings, a test signal is input from the probe of the test device to the tester pads PDV and PDC before cutting out the plurality of array substrates 20 from the mother substrate. Then, a test signal is inputted from the tester wirings WV, WC, Wcom to the OLB pads 26A, 26B, and the driving circuit, the pixel circuit, various wirings, etc. are tested.

  At this time, the lightning rod pattern 24 overlapping the tester wiring of the array substrate under test is provided in the common wiring COM disposed in the second region of the adjacent array substrate. Therefore, since no signal is input to the lightning rod pattern 24 during the test, no signal is input to the lightning rod pattern even if the tester wiring to which the test signal is input and the opposing lightning rod pattern are short-circuited due to electrostatic energy. Therefore, it does not affect the test.

  Note that by reducing the area (effective lightning rod area) facing the lightning rod pattern and the tester wiring as much as possible, a potential difference between the tester wiring and the lightning rod pattern is likely to occur. Therefore, the smaller the effective lightning rod area, the easier it is to form a pinhole in the vicinity of the lightning rod pattern, so that the effect as a lightning rod can be exhibited.

  Further, if possible, the lightning rod pattern 24 may be arranged in a region where the black matrix BM is not arranged. In that case, it is possible to avoid the formation of pinholes in the black matrix BM.

  Further, it is desirable that the lightning rod pattern 24 be provided in an area that is further shielded from light by a bezel or the like after the liquid crystal display device is assembled.

  In the above embodiment, the black matrix BM is disposed on the array substrate 20 side. However, even when the black matrix BM is disposed on the counter substrate 10 side, the black matrix BM is located near the position facing the lightning rod pattern 24. Only the pinholes of the black matrix BM are formed, and it can be avoided that the bright spots are visually recognized.

  That is, according to the liquid crystal display device and the mother substrate according to the present embodiment, it is possible to provide a liquid crystal display device with good appearance and the mother substrate.

  Furthermore, by forming the lightning rod pattern 24 in the common wiring COM having a large capacity as described above, an increase in potential due to jumping charges can be suppressed. In addition, since the switching element is not connected to the common wiring line COM, there is no problem with the switching element due to jumping charges. In the above embodiment, the lightning rod pattern 24 is provided on the common wiring COM, but the lightning rod pattern may be provided on a wiring other than the common wiring COM. It is desirable that the lightning rod pattern 24 be provided on a wiring having a relatively large capacity and not connected to a switching element or the like.

  In the above embodiment, the lightning rod pattern 24 extends from the base pattern 25 of the injection port. However, if it is arranged so as to extend away from the display unit DYP, it is formed at a position other than the base pattern 25 of the injection port. May be. Even in such a case, by providing the lightning rod pattern 24 so as to extend in a direction away from the display unit DYP, it is possible to prevent a pinhole from occurring in the vicinity of the display unit DYP.

  Further, in the above embodiment, since the tester wiring WC connected to the OLB pad 26A and the tester wiring WC connected to the OLB pad 26B are electrically connected, disconnection occurs in a part of the tester wiring WC. Even in this case, a test signal can be input from the control pad PDC of either the OLB pads 26A and 26B.

  Although several embodiments of the present invention have been described, these embodiments are presented by way of example and are not intended to limit the scope of the invention. These novel embodiments can be implemented in various other forms, and various omissions, replacements, and changes can be made without departing from the scope of the invention. These embodiments and modifications thereof are included in the scope and gist of the invention, and are included in the invention described in the claims and the equivalents thereof.

  PX ... display pixel, DYP ... display unit, FRM ... frame portion, LQ ... liquid crystal layer, Y ... scanning line, X ... signal line, PE ... pixel electrode, SW ... pixel switch, YD ... scanning line drive circuit, XD ... signal Line drive circuit, PDV, PDC ... Tester pad, COM ... Common wiring (first wiring), GE ... Gate electrode, L1 ... Gate insulating film (insulating layer), SE ... Source electrode, DE ... Drain electrode, L2 ... Passivation film , YDR ... scanning line driving circuit, YDL ... scanning line driving circuit, PDV ... video pad, PDC ... control pad, WV, WC, Wcom ... tester wiring, BM ... black matrix (light shielding layer), CE ... counter electrode, SL ... Seal member, 10 ... counter substrate, 20 ... array substrate, 20A ... area, 20B ... area, 24 ... lightning rod pattern, 25 ... ground pattern, 26A, 26B ... OLB pattern De, 200: insulating substrate, 210 ... semiconductor layer.

Claims (5)

An array substrate;
A counter substrate disposed to face the array substrate;
A liquid crystal layer sandwiched between the array substrate and the counter substrate;
A display unit including a plurality of display pixels arranged in a matrix;
A frame portion surrounding the display portion,
The array substrate is disposed at the frame portion and has a lightning rod pattern extending in a direction away from the display portion, a connection pad electrically connectable to an external signal source, and a tester pad to which a test signal is input And tester wiring,
The tester pad and the tester wiring are arranged across the display unit,
The lightning rod pattern overlaps at least a part of the tester wiring with an insulating layer interposed therebetween. The array substrate includes a pixel electrode disposed in each display pixel,
The counter substrate includes a counter electrode arranged to face a plurality of pixel electrodes,
The liquid crystal display device according to claim 1, wherein the first wiring is electrically connected to the counter electrode through a conductive member.   The liquid crystal display device according to claim 1, wherein the array substrate further includes a light shielding layer disposed on an upper layer of the tester wiring.   The liquid crystal display device according to claim 1, wherein the first wiring is a common wiring. A mother substrate including a plurality of array regions each including a first region including a plurality of pixel electrodes arranged in a matrix and a second region surrounding the first region,
A connection pad disposed in the second region and connectable to an external signal source;
A test pad for supplying a test signal to the connection pad;
A tester wiring extending between the test pad and the connection pad over a plurality of second regions;
A first wiring provided with a lightning rod pattern disposed in the two regions and extending in a direction away from the first region;
The lightning rod pattern is a mother board that overlaps at least a part of the tester wiring via an insulating layer.

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