KR20170081074A - Organic light emitting diode display device - Google Patents

Abstract

The organic light emitting diode display according to the present invention has an organic light emitting diode electrically connected to a thin film transistor, and includes an anode electrode (ANO), an organic light emitting layer, and a cathode electrode. The organic light emitting diode display according to the present invention includes a low potential power supply line, auxiliary cathode electrodes, and a first link pattern. The low potential power supply line supplies a low potential power supply voltage to the cathode electrode. The auxiliary cathode electrodes are connected to the cathode electrode at the first contact point. The first link pattern is connected to one end of the auxiliary cathode electrodes at the second contact point. At this time, the first link pattern is connected to the low potential power supply line, and electrically connects the auxiliary cathode electrodes to the low potential power supply line.

Description

TECHNICAL FIELD [0001] The present invention relates to an organic light emitting diode (OLED) display device,

The present invention relates to an organic light emitting diode display.

2. Description of the Related Art In recent years, various flat panel display devices capable of reducing weight and volume, which are disadvantages of CRT (Cathode Ray Tube), have been developed. Examples of such flat panel display devices include a liquid crystal display (LCD), a field emission display (FED), a plasma display panel (PDP), and an organic light emitting diode (OLED) : Organic Light Emitting Display).

Of these flat panel display devices, an organic light emitting diode display device is a self-luminous display device that excites an organic compound to emit light, and it does not require a backlight used in an LCD, so that it is lightweight and thin and can simplify a process . Further, the organic light emitting display device is widely used because it can be manufactured at low temperature, has a response speed of 1 ms or less and has a high response speed as well as low power consumption, wide viewing angle, and high contrast have.

Hereinafter, a conventional organic light emitting diode display device will be described with reference to FIGS. 1 and 2. FIG. 1 is a plan view showing a structure of a conventional organic light emitting diode display device. FIG. 2 is a cross-sectional view cut along a perforated line I-I 'in FIG. 1, illustrating a structure of a conventional organic light emitting diode display device.

1 and 2, an organic light emitting diode (OLED) display device includes an organic light emitting diode (OLED) connected to a thin film transistor (hereinafter, referred to as TFT) ST and a thin film transistor DT, Film transistor substrate.

The thin film transistor substrate includes a switching TFT ST, a driving TFT DT connected to the switching TFT ST, and an organic light emitting diode OLE connected to the driving TFT DT. The switching TFT ST is formed on a portion of the substrate SUB where the gate line GL and the data line DL cross each other. The switching TFT ST functions to select a pixel. The switching TFT ST includes a gate electrode SG, a semiconductor layer SA, a source electrode SS, and a drain electrode SD which branch off from the gate line GL.

The driving TFT DT serves to drive the organic light emitting diode OLE of the pixel selected by the switching TFT ST. The driving TFT DT includes a gate electrode DG connected to the drain electrode SD of the switching TFT ST, a semiconductor layer DA, a source electrode DS connected to the high potential power supply line VDL, DD). The drain electrode DD of the driving TFT DT is connected to the anode electrode ANO of the organic light emitting diode OLE. A cathode electrode (CAT) covering the majority of the substrate is disposed on the anode electrode (ANO), and an organic light emitting layer is interposed between the anode electrode (ANO) and the cathode electrode (CAT).

A gate pad GP formed at one end of the gate line GL, a data pad DP formed at one end of the data line DL and a data pad DP formed at one end of the data line DL and a low potential power line VDL, And a high potential power supply pad (VDP) formed at one end of the power supply pad.

2, semiconductor layers SA and DA are formed on a substrate SUB. Gate electrodes SG and DG are formed on the semiconductor layers SA and DA with the gate insulating film GI therebetween. The gate electrodes SG and DG are superimposed on the central portions of the semiconductor layers SA and DA and the center portion of the semiconductor layers SA and DA overlapped with the gate electrodes SG and DG can be defined as a channel region. A gate pad GP may be formed on the gate insulating film GI.

One side of the semiconductor layers SA and DA is connected to the source electrodes SS and DS through the contact holes and the other side is connected to the drain electrodes SD and DD. The source electrodes SS and DS and the drain electrodes SD and DD are formed on the insulating film IN covering the gate electrodes SG and DG. A data pad DP and a high potential power supply pad VDP may be formed on the insulating layer IN.

A protective film PAS is formed on the substrate SUB on which the switching TFT ST and the driving TFT DT are formed. A planarizing film PL is formed on the substrate SUB on which the protective film PAS is formed.

An anode electrode ANO is formed on the planarizing film PL in contact with the drain electrode DD of the driving TFT DT through the contact hole. A gate pad terminal (not shown) connected to the gate pad GP, the data pad DP, and the high potential power supply pad VDP is formed through the contact holes passing through the insulating film, GPT), a data pad terminal (DPT), and a high potential power supply terminal (VDPT). On the substrate SUB on which the anode electrode ANO is formed, a bank BA is formed. The bank BA exposes most of the anode electrode ANO. The organic light emitting layer OL is formed on the exposed anode electrode ANO. A cathode electrode (CAT) is formed on the substrate on which the organic light emitting layer (OL) is formed. Thereby, an organic light emitting diode (OLE) including the anode electrode ANO, the organic light emitting layer OL, and the cathode electrode CAT is completed.

The cathode electrode (CAT) to which the low potential power supply voltage is applied is formed over most of the entire surface of the substrate (SUB). There is no serious problem when the cathode electrode (CAT) is formed of a metal material having a low specific resistance value. However, when it is necessary to secure the transmittance of the cathode electrode (CAT) located in the upper layer like the top emission display, the cathode electrode (CAT) may be formed of a transparent conductive material such as ITO (Indium Tin Oxide) It needs to be formed of a material. In the case where the cathode electrode (CAT) is formed of a transparent conductive material such as ITO, the surface resistance may become large, which may cause image quality problems.

That is, when the cathode electrode (CAT) including a material having a high resistivity is used, the surface resistance becomes large. In this case, a problem occurs that the low potential power supply voltage applied to the cathode electrode CAT does not have a constant voltage value over the entire area of the cathode electrode CAT. Particularly, in the case of a large-area display device, a voltage deviation according to the position will occur with a large voltage deviation according to the distance from the lead-in portion to which the low-potential power supply voltage is applied. Therefore, It can become an important problem.

SUMMARY OF THE INVENTION It is an object of the present invention to provide an organic light emitting diode (OLED) display device in which a low potential power source voltage deviation of a cathode electrode is minimized according to a position.

The organic light emitting diode display according to the present invention has an organic light emitting diode electrically connected to a thin film transistor, and includes an anode electrode (ANO), an organic light emitting layer, and a cathode electrode. The organic light emitting diode display according to the present invention includes a low potential power supply line, auxiliary cathode electrodes, and a first link pattern. The low potential power supply line supplies a low potential power supply voltage to the cathode electrode. The auxiliary cathode electrodes are connected to the cathode electrode at the first contact point. The first link pattern is connected to one end of the auxiliary cathode electrodes at the second contact point. At this time, the first link pattern is connected to the low potential power supply line, and electrically connects the auxiliary cathode electrodes to the low potential power supply line.

The organic light emitting diode display according to the present invention may further include a second link pattern connected to the other end of the auxiliary cathode electrodes.

The organic light emitting diode display according to the present invention may further include a first link pattern and a third link pattern connected to the second link pattern.

The organic light emitting diode display according to the present invention further includes pixels partitioned by gate lines and data lines intersecting with each other. The auxiliary cathode electrode may be disposed in parallel with the data line between neighboring pixels. The first link pattern may be arranged in parallel with the gate line.

The auxiliary cathode electrode has a lower resistance value than the cathode electrode.

The first link pattern has a lower resistance value than the cathode electrode.

The first contact point is located at least on each of the auxiliary cathode electrodes.

The distance between neighboring first contact points may be inversely proportional to the distance from the first link pattern.

The density of the first contact point can be increased as the distance from the first link pattern is increased.

The present invention can reduce the surface resistance of the cathode electrode by connecting the auxiliary cathode electrode formed of a conductive material having a low resistivity to the cathode electrode, thereby reducing the luminance unevenness defect caused by the in-plane resistance variation of the cathode electrode.

In addition, by providing a plurality of low potential power supply paths for transmitting the low potential power supply voltage to the cathode electrode, it is possible to minimize the variation of the IR rising position generated at the cathode electrode. That is, according to the present invention, by ensuring a sufficient low-potential power supply path, a structure in which only the auxiliary cathode electrode is connected to the cathode electrode to which the low-potential power supply voltage is applied is compared with the structure in which the luminance non- Can be minimized.

1 is a plan view showing a structure of a conventional organic light emitting diode display device.
FIG. 2 is a cross-sectional view cut along a perforated line I-I 'in FIG. 1, illustrating a structure of a conventional organic light emitting diode display device.
3 is a schematic view illustrating an organic light emitting diode display device according to the present invention.
FIG. 4 is a schematic diagram showing the pixel shown in FIG. 3. FIG.
5 is a plan view schematically showing an organic light emitting diode display device according to the present invention.
6 is a view schematically showing an example of arrangement of link patterns according to the present invention.
7 is a plan view schematically showing an organic light emitting diode display according to a preferred embodiment of the present invention.
FIG. 8 is a cross-sectional view taken along the cutting line II-II 'in FIG.
9 is a cross-sectional view taken along the perforated line III-III 'in FIG.
FIGS. 10 to 12 are views for explaining a position pattern of the first contact point where the cathode electrode and the auxiliary cathode electrode are connected.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Reference will now be made in detail to the preferred embodiments of the present invention, examples of which are illustrated in the accompanying drawings. Like reference numerals throughout the specification denote substantially identical components. In the following description, a detailed description of known functions and configurations incorporated herein will be omitted when it may make the subject matter of the present invention rather unclear. In addition, the component names used in the following description may be selected in consideration of easiness of specification, and may be different from the parts names of actual products.

Terms including ordinals, such as first, second, etc., may be used to describe various elements, but the elements are not limited to these terms. The terms are used only for the purpose of distinguishing one component from another.

It is to be understood that when an element is referred to as being "connected" or "connected" to another element, it may be directly connected or connected to the other element, . On the other hand, when an element is referred to as being "directly connected" or "directly connected" to another element, it should be understood that there are no other elements in between.

The singular expressions include plural expressions unless the context clearly dictates otherwise.

3 is a schematic view illustrating an organic light emitting diode display device according to the present invention. FIG. 4 is a schematic diagram showing the pixel shown in FIG. 3. FIG.

Referring to FIG. 3, the organic light emitting diode display 10 according to the present invention includes a display driving circuit and a display panel DIS.

The display driving circuit includes a data driving circuit 12, a gate driving circuit 14 and a timing controller 16, and writes the video data voltage of the input image to the pixels of the display panel DIS. The data driving circuit 12 converts the digital video data RGB input from the timing controller 16 into an analog gamma compensation voltage to generate a data voltage. The data voltage output from the data driving circuit 12 is supplied to the data lines D1 to Dm. The gate driving circuit 14 sequentially supplies gate pulses synchronized with the data voltages to the gate lines G1 to Gn to select the pixels of the display panel DIS to which the data voltages are written.

The timing controller 16 inputs timing signals such as a vertical synchronization signal Vsync, a horizontal synchronization signal Hsync, a data enable signal DE and a main clock MCLK input from the host system 19 And synchronizes the operation timings of the data driving circuit 12 and the gate driving circuit 14 with each other. The data timing control signal for controlling the data driving circuit 12 includes a source sampling clock (SSC), a source output enable (SOE) signal, and the like. The gate timing control signal for controlling the gate driving circuit 14 includes a gate start pulse GSP, a gate shift clock GSC, a gate output enable signal GOE .

The host system 19 may be implemented as any one of a television system, a set-top box, a navigation system, a DVD player, a Blu-ray player, a personal computer (PC), a home theater system, and a phone system. The host system 19 includes a system on chip (SoC) with a built-in scaler to convert the digital video data RGB of the input image into a format suitable for display on the display panel DIS. The host system 19 transmits timing signals (Vsync, Hsync, DE, MCLK) to the timing controller 16 together with the digital video data.

The pixel array of the display panel DIS includes pixels defined by the data lines (D1 to Dm, m is a positive integer) and the gate lines (G1 to Gn, n is a positive integer). Each of the pixels includes an organic light emitting diode (OLED), which is a self-luminous element.

4, a plurality of data lines D and a plurality of gate lines G are intersected with each other in a display panel DIS, and pixels are arranged in a matrix form in each of the intersection areas. Each of the pixels includes a driving thin film transistor (hereinafter referred to as TFT) DT for controlling the amount of current flowing through the OLED and the OLED, and a programming portion SC for setting the gate-source voltage of the driving TFT DT .

The programming portion SC may include at least one switch TFT and at least one storage capacitor. The switch TFT is turned on in response to a scan signal from the gate line G, thereby applying a data voltage from the data line D to one electrode of the storage capacitor. The driving TFT DT controls the amount of current supplied to the OLED according to the magnitude of the voltage charged in the storage capacitor to control the amount of light emitted from the OLED. The amount of light emission of the OLED is proportional to the amount of current supplied from the driving TFT DT. These pixels are connected to a high potential power source voltage source (EVDD) and a low potential power source voltage source (EVSS), respectively, and are supplied with a high potential power source voltage and a low potential power source voltage from a power source not shown. The TFTs constituting the pixel may be implemented as a p-type or an n-type. Further, the semiconductor layer of the TFTs constituting the pixel may include amorphous silicon, polysilicon, or an oxide. The OLED includes an anode electrode ANO, a cathode electrode CAT, and an organic light emitting layer interposed between the anode electrode ANO and the cathode electrode CAT. The anode electrode ANO is connected to the driving TFT DT. The organic emission layer includes an emission layer (EML) and includes a hole injection layer (HIL), a hole transport layer (HTL), an electron transport layer (ETL), and an electron injection layer injection layer, EIL).

Hereinafter, a characteristic configuration of an organic light emitting diode display device according to the present invention will be described with reference to FIGS. 5 and 6. FIG. 5 is a plan view schematically showing an organic light emitting diode display device according to the present invention. 6 is a view schematically showing an example of arrangement of link patterns according to the present invention.

Referring to FIG. 5, the organic light emitting diode display device according to the present invention includes a display panel (DIS) to which various driving signals and a power voltage are supplied from the above-described circuit portion. The display panel DIS includes a low potential power supply line VSL, a cathode electrode CAT, an auxiliary cathode electrode ACAT, and a first link pattern LP1.

A low potential power supply voltage is applied to the low potential power supply line (VSL). For example, the low potential power supply line (VSL) may be connected to a pad to which a low potential power supply voltage is supplied among the pads provided in the pad portion PA. At this time, the pad portion PA can be connected to a flexible film such as COF (Chip On Film), and the low potential power supply voltage outputted from the power generation portion is connected to the pad portion PA of the display panel DIS And can be input to the low potential power supply line (VSL) of the display panel DIS via the film.

The cathode electrode CAT is directly connected to the low-potential power supply line (VSL) to receive the low-potential power supply voltage. The cathode electrode (CAT) is formed of a transparent conductive material such as indium tin oxide (ITO) or indium zinc oxide (ITO). That is, in the case of the top emission type, the cathode electrode (CAT) located in the upper layer is formed of a transparent conductive material since light must transmit through it.

Transparent conductive materials have higher resistivity than metallic materials. When the cathode electrode (CAT) including a material having a high resistivity is used, the problem that the low potential power supply voltage applied to the cathode electrode (CAT) does not have a constant voltage value over the entire area of the cathode electrode (CAT) Occurs. For example, when the deviation between the low-potential power supply voltage value at the lead-in portion to which the low-potential power supply voltage is applied and the low-potential power supply voltage value at the position apart from the lead-in portion becomes large and the brightness is not constant have.

To prevent this, the present invention further includes an auxiliary cathode electrode (ACAT) formed of a low resistivity conductive material. That is, the auxiliary cathode electrode ACAT includes a material having lower resistance than the cathode electrode CAT. The auxiliary cathode electrode ACAT is disposed in a different layer with the cathode electrode CAT interposed therebetween.

The auxiliary cathode electrode ACAT and the cathode electrode CAT are disposed in different layers with one or more insulating films therebetween and are in contact with each other at the first contact point CP1. For example, the cathode electrode CAT and the auxiliary cathode electrode ACAT may be electrically connected through a laser process at the first contact point CP1 or may be electrically connected through the contact hole. Accordingly, the present invention can reduce the surface resistance of the cathode electrode (CAT), thereby reducing the luminance unevenness defect due to the in-plane resistance variation of the cathode electrode (CAT).

The first link pattern LP1 is directly connected to the low-potential power supply line VSL and is supplied with the low-potential power supply voltage. The first link pattern LP1 is connected to one end of the auxiliary cathode electrodes ACAT to electrically connect each of the auxiliary cathode electrodes ACAT. The first link pattern LP1 and the auxiliary cathode electrode ACAT are disposed on different layers with one or more insulating films interposed therebetween and are in contact with each other at a second contact point CP2. For example, one end of the first link pattern LP1 and the auxiliary cathode electrode ACAT may be electrically connected through a laser process at the second contact point CP2, or may be electrically connected through the contact hole. The low potential power supply voltage applied to the low potential power supply line (VSL) is transmitted to each of the auxiliary cathode electrodes (ACAT) through the first link pattern (LP1).

The first link pattern LP1 includes a material having lower resistance than the cathode electrode CAT. The first link pattern LP1 may have a bar shape extending in a direction crossing the auxiliary cathode electrode ACAT.

The first link pattern LP1 may be in contact with the cathode electrode CAT at the entrance of the low potential power supply voltage connected to the low potential power supply line VSL. Also, the first link pattern LP1 and the cathode electrode CAT may be in contact with each other at the third contact point CP3 outside the lead-in portion. For example, the first link pattern LP1 and the cathode electrode CAT are disposed on different layers with at least one insulating film interposed therebetween, and are electrically connected through a laser process at the third contact point CP3, As shown in FIG. In the preferred embodiment of the present invention, by forming a plurality of third contact points CP3, the resistance of the cathode electrode CAT can be further reduced.

In the present invention, the cathode electrode CAT receives a low-potential power supply voltage generated from a power generating unit (not shown) directly through a low-potential power supply line (VSL). The cathode electrode CAT receives the low potential power supply voltage generated from the power generating unit through the auxiliary cathode electrode ACAT connected to the low potential power supply line VSL. Accordingly, the present invention can include a plurality of low potential power supply paths for transferring the low potential power supply voltage to the cathode electrode (CAT).

That is, the low potential power supply path includes a first supply path and a second supply path. The first supply path includes a low potential power supply line (VSL) connected to the cathode electrode (CAT), and a low potential power supply voltage source for generating a low potential power supply voltage and supplying it to the low potential power supply line (VSL). The second supply path includes an auxiliary cathode electrode ACAT connected to the cathode electrode CAT, a first link pattern LP1 connected to the auxiliary cathode electrode ACAT, a low potential power supply line VSL connected to the first link pattern LP1, ), And a low-potential power supply voltage source for generating a low-potential power supply voltage and supplying it to the low-potential power supply line (VSL). The present invention further includes a second supply path in addition to the first supply path, thereby minimizing the variation of the IR rising position generated in the cathode electrode (CAT).

Unlike the case of supplying the low potential power supply voltage to the cathode electrode CAT only through the first supply path, the present invention further supplies the low potential power supply voltage to the cathode electrode CAT through one or more of the auxiliary cathode electrodes ACAT So that a plurality of low potential power supply paths can be additionally secured. The present invention provides a structure in which only the auxiliary cathode electrode (ACAT) is connected to the cathode electrode (CAT) to which a low potential power supply voltage is applied by securing a sufficient low potential power supply path, It is possible to minimize the nonuniformity in luminance due to the deviation.

When the low-potential power supply voltage is supplied to the cathode electrode CAT only through the first supply path, the resistance of the cathode electrode CAT can be reduced to some extent by connecting the auxiliary cathode electrode ACAT to the cathode electrode CAT . However, in this case, since the low-potential power supply voltage is basically transmitted through the high-resistance cathode electrode (CAT), it is difficult to reduce the deviation of the position of the IR rising generated by the cathode electrode CAT as much as required. The present invention further provides a second supply path through which a low potential voltage is supplied through the first link pattern LP1 and the auxiliary cathode electrode ACAT having a low resistance so that an IR rising generated in the cathode electrode CAT is generated, Can be minimized.

Referring to FIG. 6, the organic light emitting diode display according to the present invention may further include a second link pattern LP2 and / or a third link pattern LP3.

The second link pattern LP2 is connected to the other end of the auxiliary cathode electrodes ACAT. The second link pattern LP2 is formed of a low resistance material and may be formed of the same material as the first link pattern LP1. The other end of the second link pattern LP2 and the auxiliary cathode electrode ACAT are in contact with each other at the second contact point CP2. For example, the other end of the second link pattern LP2 and the auxiliary cathode electrode ACAT may be electrically connected through a laser process at the second contact point CP2, or may be electrically connected through a contact hole. The second link pattern LP2 may have a bar shape extending in a direction crossing the auxiliary cathode electrode ACAT.

The third link pattern LP3 is connected to the first link pattern LP1 and the third link pattern LP3 to electrically connect the first link pattern LP1 and the third link pattern LP3. The third link pattern LP3 is formed of a low resistance material and may be formed of the same material as the first link pattern LP1 and / or the second link pattern LP2. The first link pattern LP1, the second link pattern LP2, and the third link pattern LP3 may be formed as one body on the same layer. At least one of the first link pattern LP1, the second link pattern LP2, and the third link pattern LP3 may be disposed on a different layer than the other one, Holes can be connected to each other. The third link pattern LP3 may have a bar shape extending in a direction parallel to the auxiliary cathode electrode ACAT.

The more the second link pattern LP2 and the third link pattern LP3 including the low-resistance material are provided, the more advantageous is the formation of the equipotential at the front surface of the cathode electrode CAT. Therefore, the preferred embodiment of the present invention further includes the second link pattern LP2 and the third link pattern LP3, thereby minimizing the reduction in the potential difference between the anode electrode ANO and the cathode electrode CAT can do.

Hereinafter, an OLED display according to a preferred embodiment of the present invention will be described with reference to FIGS. 7 to 9. FIG. 7 is a plan view schematically showing an organic light emitting diode display according to a preferred embodiment of the present invention. FIG. 8 is a cross-sectional view taken along the cutting line II-II 'in FIG. 9 is a cross-sectional view taken along the perforated line III-III 'in FIG.

Referring to FIG. 7, the organic light emitting diode display according to the preferred embodiment of the present invention includes a display area AA for displaying image information, a non-display area AA for driving various elements for driving the display area AA NA) is defined. A plurality of pixels PA arranged in a matrix manner are defined in the display area AA. In Fig. 7, PAs are indicated by dotted lines.

For example, the pixels PA can be defined in a rectangular form of the NxM scheme. However, it is not necessarily limited to this method, but may be arranged in various ways. Each pixel may have the same size or different sizes. In addition, three sub-pixels representing RGB colors may be regularly arranged as one unit. In the simplest structure, the pixels PA may be defined as the intersection structure of the gate lines GL extending in the first direction and the plurality of data lines DL extending in the second direction.

A pad portion PA is provided on one side of the non-display region. The data line DL is electrically connected to the data pad of the pad unit PA to receive the data voltage. The high-potential power supply line VDL is electrically connected to the high-potential power supply pad of the pad unit PA and is supplied with the high-potential power supply voltage. The low potential power supply line VSL is electrically connected to the low potential power pad of the pad portion PA and is supplied with the low potential power supply voltage. The cathode electrode CAT is connected to the low potential power supply line (VSL) to receive the low potential power supply voltage. Thereby, a first supply path through which the low potential power supply voltage is supplied is formed.

The data lines DL are arranged between neighboring pixels PA in the first direction. The high potential power supply line VDL is disposed between neighboring pixels PA in the first direction. However, the high-potential power supply line VDL need not always be arranged between neighboring pixels PA in the first direction. In this case, any one of the high-potential power supply lines VDL running in the second direction may be electrically connected to at least two pixels PA neighboring in the first direction. That is, at least two pixels PA adjacent to each other in the first direction may share one high potential power supply line VDL.

The auxiliary cathode electrode ACAT is disposed between neighboring pixels PA in the first direction. The auxiliary cathode electrode ACAT may be disposed in parallel with the data line DL and the high potential power supply line VDL. The auxiliary cathode electrode ACAT need not necessarily be disposed between adjacent pixels PA in the first direction. At least one of the high potential power supply line (VDL) and the auxiliary cathode electrode (ACAT) may be disposed between the neighboring pixels (PA) along with the data line extending in the second direction. For example, both the high potential power supply line VDL and the auxiliary cathode electrode ACAT may be disposed between neighboring pixels PA, either of which may be arranged. The high-potential power supply line VDL and the auxiliary cathode electrode ACAT may be alternately arranged. For example, one or more high power supply lines VDL may be disposed between neighboring auxiliary cathode electrodes ACAT. Also, one or more of the auxiliary cathode electrodes ACAT may be disposed between neighboring high-potential power supply lines VDL.

Thin film transistors for driving the organic light emitting diodes are disposed in each pixel PA. The thin film transistors may be formed in the thin film transistor region TA defined at one side of the pixel PA. The organic light emitting diode includes an anode electrode ANO and a cathode electrode CAT and an organic light emitting layer interposed between the two electrodes ANO and CAT. The region in which light is actually emitted can be determined by the area of the organic light emitting layer overlapping with the anode electrode ANO.

The anode electrode ANO is formed to occupy a part of the pixel PA and is electrically connected to the thin film transistor formed in the thin film transistor region TA. An anode electrode ANO is formed for each pixel PA. The anode electrode ANO is spaced apart from the anode electrode ANO of the neighboring pixel PA so as not to be in contact with the anode electrode ANO. An organic light emitting layer is formed on the anode electrode ANO. The cathode electrode CAT is formed so as to cover the entire area of the display area AA where at least the pixels PA are arranged above the organic light emitting layer. The cathode electrode CAT is electrically connected to the auxiliary cathode electrode ACAT at the first contact point CP1.

The first link pattern LP1 is connected to one end of the auxiliary cathode electrodes ACAT. The first link pattern LP1 is electrically connected to the auxiliary cathode electrode ACAT at the second contact point CP2. If necessary, the first link pattern LP1 may be electrically connected to the cathode electrode CAT at the third contact point CP3. The first link pattern LP1 is connected to the low potential power supply line VSL and transfers the low potential power supply voltage supplied from the low potential power supply line VSL to the auxiliary cathode electrodes ACAT. Thereby, a second supply path through which the low potential power supply voltage is supplied is formed.

The first link pattern LP1 may be disposed in parallel with the gate line GL in the non-display area NA. The first link pattern LP1 intersects the data line and the high-potential power supply line VDL. The first link pattern LP1 is disposed in a different layer with at least one insulating film interposed therebetween so as not to be short-circuited with the data line and the high-potential power supply line VDL.

8 and 9, a non-display area NA and a display area AA are defined on the substrate. In the non-display area NA, a low-potential power supply line VSL is disposed. In the display area AA, a switching thin film transistor ST, a driving thin film transistor DT and an organic light emitting diode OLE are arranged.

The switching thin film transistor ST formed in the display region AA includes a gate electrode SG, a gate insulating film GI, a channel layer SA, a source electrode SS and a drain electrode SD. The driving thin film transistor DT includes a gate electrode DG connected to the drain electrode SD of the switching thin film transistor ST, a gate insulating film GI, a channel layer DA, a source electrode DS and a drain electrode DD). The structure of the TFTs (ST, DT) is not limited thereto. The structure of the thin film transistor (ST, DT) may include any structure that can drive an organic light emitting diode display device such as a top gate structure, a bottom gate structure, and a double gate structure.

A protective film PAS and a planarizing film PL are sequentially formed on the thin film transistors ST and DT. An anode electrode ANO is formed on the planarizing film PL. The anode electrode ANO is connected to the driving drain electrode DD of the driving thin film transistor DT through the protective film PAS and the contact hole passing through the planarizing film PL.

A bank BA is formed on the anode electrode ANO and the first link pattern LP1. The bank BA exposes most of the anode electrode ANO. The organic light emitting layer OL is formed on the anode electrode ANO exposed by the bank BA pattern. On the bank BA, a cathode electrode (CAT) including a transparent conductive material is formed. Thereby, an organic light emitting diode (OLE) including the anode electrode ANO, the organic light emitting layer OL, and the cathode electrode CAT is formed.

The low potential power supply line VSL may be formed in the same layer with the same material as the source electrodes SS and DS and the drain electrodes SD and DD. However, the present invention is not limited thereto, and the low potential power supply line VSL may be formed on the same layer with the same material as the gate electrodes SG and DG. The low potential power supply line (VSL) is in contact with and electrically connected to the cathode electrode (CAT).

The auxiliary cathode electrode ACAT may be formed on the same layer with the same material as the source electrodes SS and DS and the drain electrodes SD and DD. However, the present invention is not limited thereto. For example, in the case of a top gate type thin film transistor, the organic light emitting diode display may further include a light blocking layer below the semiconductor layer in order to block light that may be incident on the semiconductor layer. At this time, the auxiliary cathode electrode ACAT may be formed on the same layer with the same material as the light blocking layer.

The auxiliary cathode electrode ACAT is connected to the cathode electrode CAT at the first contact point CP1. The auxiliary cathode electrode ACAT may be connected to the cathode electrode CAT through a contact hole passing through the bank BA, the planarizing film PL, and the passivation film PAS.

The first link pattern LP1 is connected to the auxiliary cathode electrode ACAT at the second contact point CP2. As shown in the figure, the first link pattern LP1 may be connected to the auxiliary cathode electrode ACAT through the contact hole passing through the planarizing film PL and the protective film PAS. Also, the first link pattern LP1 may be connected to the cathode electrode CAT at the third contact point CP3. As shown in the figure, the first link pattern LP1 may be connected to the cathode electrode CAT through a contact hole passing through the bank BA.

The first link pattern LP1 is formed of a low resistance material. For example, the first link pattern LP1 may be formed of a single layer including Mo, Cu, Ag, Cr, Al, or MoTi, or a multilayer in which the layers are stacked. However, the present invention is not limited thereto. The first link pattern LP1 may be disposed on the same layer with the same material as the anode electrode ANO. In the case of the top emission type, in order to improve the luminous efficiency of the display device, the anode electrode ANO can be formed of a material having high reflectance. In consideration of the resistance and the reflectance, it may be preferable that the first link pattern LP1 and the anode electrode ANO include Ag.

The first link pattern LP1 is spaced apart from the high potential power supply line VDL by a predetermined distance G with the planarizing film PL and the protective film PAS interposed therebetween. That is, according to the present invention, the first link pattern LP1 to which a low-potential power supply voltage is applied is disposed apart from the high-potential power supply line VDL with one or more insulating films interposed therebetween, It is possible to prevent a short circuit of the line VDL. This can prevent burnt defects such as deterioration of the organic light emitting diode due to a short circuit between the first link pattern LP1 and the high-potential power supply line VDL.

Hereinafter, the positional pattern of the first contact point to which the cathode electrode and the auxiliary cathode electrode are connected will be described with reference to FIGS. 10 to 12. FIG. FIGS. 10 to 12 are views for explaining a position pattern of the first contact point where the cathode electrode and the auxiliary cathode electrode are connected.

The organic light emitting diode display according to the present invention includes a first link pattern LP1 arranged in a first direction and a plurality of auxiliary cathode electrodes ACAT arranged in parallel in a second direction intersecting the first direction. One end of the auxiliary cathode electrodes ACAT is connected to the first link pattern LP1. The auxiliary cathode electrodes ACAT are electrically connected to the cathode electrode CAT at the first contact point CP1.

As described above, the auxiliary cathode electrode ACAT and the cathode electrode CAT may be electrically connected through a laser process at the first contact point CP1 or may be electrically connected through the contact hole. In order to effectively reduce the surface resistance of the cathode electrode CAT, the larger the number of the first contact points CP1, the better. However, if it is too much, it may be disadvantageous due to an increase in contact resistance, and a malfunction due to a process failure may occur. Therefore, it is preferable that the number of the first contact points CP1 is appropriately selected in consideration thereof.

An embodiment of the present invention can reduce the IR lifting caused in the cathode electrode (CAT) by locating at least one or more first contact points (CP1) in each of the auxiliary cathode electrodes (ACAT).

10, the auxiliary cathode electrode ACAT may include a first auxiliary cathode electrode ACAT1 and a second cathode electrode CAT. A first contact point CP1 is located on the first auxiliary cathode electrode ACAT1. The first contact point CP1 is not located on the second auxiliary cathode electrode ACAT2. At least one second auxiliary cathode electrode ACAT2 may be disposed between adjacent first auxiliary cathode electrodes ACAT1. In this case, IR rising occurs between adjacent first auxiliary cathode electrodes ACAT1. That is, a local luminance variation due to IR rising may occur between adjacent first auxiliary cathode electrodes ACAT1.

In order to solve this problem, an embodiment of the present invention places the first contact point CP1 for each of the auxiliary cathode electrodes ACAT. 11, at least one first contact point CP1 is located on all the auxiliary cathode electrodes ACAT. The position pattern of the first contact point CP1 may vary as shown. By varying the position pattern of the first contact point CP1, it is possible to minimize the occurrence of a local brightness variation depending on the position.

In one embodiment of the present invention, the position of the first contact point CP1 may be different according to the distance from the inlet portion to which the low potential power supply voltage is applied. Due to the high resistance of the cathode electrode (CAT), a voltage deviation corresponding to the position, for example, a voltage deviation according to the distance from the lead-in portion to which the low-potential power supply voltage is applied, is large. That is, the IR distance increases as the distance from the inlet portion increases. In the present invention, the distances between the neighboring first contact points CP1 are different, corresponding to the distance from the first link pattern LP1.

12, the distance a, b, c between the neighboring first contact points CP1 is inversely proportional to the distance D from the first link pattern LP1. For example, the distance (a, b, c) between the neighboring first contact points CP1 may gradually become narrower as the distance from the first link pattern LP1 becomes longer (a> b> c)

The density of the first contact point CP1 can be gradually increased as the distance from the first link pattern LP1 is increased. The density of the first contact point CP1 in the regions DD1 and DD2 having the area is assumed to be related to the distance D from the first link pattern LP1, Lt; RTI ID = 0.0 > LP1. ≪ / RTI > That is, as the distance from the first link pattern LP1 increases, the first contact point CP1 is densely arranged.

In the drawing, the interval between the first contact points CP1 adjacent to each other in the second direction is shown as an example, but the present invention is not limited thereto. It is needless to say that the interval of the neighboring first contact point CP1 in the first direction can be adjusted according to the distance from the first link pattern LP1.

According to an embodiment of the present invention, the positional pattern of the first contact point CP1 may be configured differently depending on the distance, so that the pull-in efficiency of the low potential power supply voltage can be increased. In other words, even if the first contact point CP1 includes a relatively small number of first contact points CP1 by varying the position pattern of the first contact point CP1, the desired brightness uniformity can be ensured. Therefore, one embodiment of the present invention can reduce the number of the first contact points CP1, thereby reducing the process cost, the process time, and the like for forming the first contact point CP1.

According to an embodiment of the present invention, a voltage deviation according to the distance from the lead-in portion can be reduced, so that the defective luminance unevenness of the display device can be minimized.

It will be apparent to those skilled in the art that various modifications and variations can be made in the present invention without departing from the spirit or scope of the invention. Therefore, the technical scope of the present invention should not be limited to the contents described in the detailed description of the specification, but should be defined by the claims.

OLE: organic light emitting diode ANO: anode electrode
OL: organic light emitting layer CAT: cathode electrode
VSL: low potential power line ACAT: auxiliary cathode electrode
LP1: first link pattern LP2: second link pattern
LP3: third link pattern CP1: first contact point
CP2: second contact point CP3: third contact point

Claims (10)

An organic light emitting diode display device having an organic light emitting diode electrically connected to a thin film transistor and configured by an anode electrode, an organic light emitting layer, and a cathode electrode,
A low potential power supply line for supplying a low potential power supply voltage to the cathode electrode;
At least one auxiliary cathode electrode connected to the cathode electrode at a first contact point; And
And a first link pattern connected to one end of the auxiliary cathode electrodes at a second contact point,
Wherein the first link pattern comprises:
And an organic light emitting diode (OLED) display connected to the low potential power line, the plurality of auxiliary cathode electrodes being electrically connected to the low potential power line. The method according to claim 1,
And a second link pattern connected to the other end of the auxiliary cathode electrodes. 3. The method of claim 2,
And a third link pattern connected to the first link pattern and the second link pattern. The method according to claim 1,
Further comprising pixels partitioned by a gate line and a data line intersecting each other,
The auxiliary cathode electrode
And arranged adjacent to the data line between the neighboring pixels
Wherein the first link pattern comprises:
And an organic light emitting diode (OLED) display device arranged in parallel with the gate line. The method according to claim 1,
The auxiliary cathode electrode
And has a resistance value lower than that of the cathode electrode. The method according to claim 1,
Wherein the first link pattern comprises:
And has a resistance value lower than that of the cathode electrode. The method according to claim 1,
Wherein the first link pattern comprises:
And at the third contact point, is connected to the cathode electrode. The method according to claim 1,
Wherein the first contact point
And at least one or more organic light emitting diode (OLED) display devices are disposed on each of the auxiliary cathode electrodes. 9. The method of claim 8,
The distance between the neighboring first contact points is determined by the distance
And the distance from the first link pattern is inversely proportional to the distance from the first link pattern. 9. The method of claim 8,
Wherein the density of the first contact point
And the distance from the first link pattern is higher.

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