KR102568932B1 - Electroluminescence display - Google Patents

Abstract

The present invention relates to an electroluminescent display device. An electroluminescent display device includes a display panel in which a display area and a non-display area outside the display area are defined. The display area of the display panel includes a plurality of pixels and auxiliary power lines. The pixel includes a thin film transistor, an anode connected to the thin film transistor, a light emitting layer disposed on the anode, and a cathode disposed on the light emitting layer. The cathode is disposed on the auxiliary power wire with at least one insulating layer interposed therebetween, and is connected to the auxiliary power wire through a contact hole penetrating the at least one insulating layer disposed between the cathode and the auxiliary power wire.

Description

Electroluminescence display {ELECTROLUMINESCENCE DISPLAY}

The present invention relates to an electroluminescent display device.

Various display devices capable of reducing the weight and volume, which are disadvantages of the cathode ray tube, are being developed. These display devices will be implemented as Liquid Crystal Displays (LCDs), Field Emission Displays (FEDs), Plasma Display Panels (PDPs), and Electroluminescence Displays. can

Among these display devices, the electroluminescent display device is roughly divided into an inorganic light emitting display device and an organic light emitting display device according to the material of the light emitting layer. An organic light emitting display device is a self-emitting display device that excites organic compounds to emit light. It does not require a backlight used in an LCD, so it is lightweight and thin, and has the advantage of simplifying the process. In addition, the organic light emitting display device is widely used in that it can be manufactured at a low temperature, has a high response speed with a response speed of 1 ms or less, and has characteristics such as low power consumption, wide viewing angle, and high contrast. .

An organic light emitting display includes an organic light emitting diode (OLED) that converts electrical energy into light energy. An organic light emitting diode includes an anode, a cathode, and an organic light emitting layer disposed therebetween. In an organic light emitting display device, holes and electrons respectively injected from an anode and a cathode are combined inside the light emitting layer to form excitons, which are excitons, from an excited state to a ground state. As it falls down, it emits light to display an image.

Despite the above advantages, when the organic light emitting display device is implemented in a large area, uniform luminance may not be maintained on the entire surface of the active area where an input image is displayed, and luminance deviation may occur depending on the position. In more detail, the cathode constituting the organic light emitting diode is formed wide to cover most of the substrate in which the active region is defined, but a power supply voltage applied to the cathode does not have a uniform voltage value over the entire surface. For example, as a difference between a voltage value at a lead-in portion to which power supply voltage is applied due to a resistance of a cathode and a voltage value at a position spaced apart from the lead-in portion increases, the luminance deviation according to the position increases.

This problem is more problematic in a top emission display device. That is, in the top emission type display device, since it is necessary to secure the transmittance of the cathode located in the upper layer of the organic light emitting diode, the cathode is formed of a transparent conductive material such as ITO (Indium Tin Oxide) or is opaque with a very thin thickness. made of conductive material. In this case, since the sheet resistance increases, the luminance deviation according to the position also significantly increases correspondingly.

An object of the present invention is to provide an electroluminescent display device that solves the luminance non-uniformity problem by minimizing the low potential voltage deviation according to the position.

The present invention relates to an electroluminescent display device. An electroluminescent display device includes a display panel in which a display area and a non-display area outside the display area are defined. The display area of the display panel includes a plurality of pixels and auxiliary power lines. The pixel includes a thin film transistor, an anode connected to the thin film transistor, a light emitting layer disposed on the anode, and a cathode disposed on the light emitting layer. The cathode is disposed on the auxiliary power wire with at least one insulating layer interposed therebetween, and is connected to the auxiliary power wire through a contact hole penetrating the at least one insulating layer disposed between the cathode and the auxiliary power wire.

According to the present invention, by connecting an auxiliary power wire including a low-resistance conductive material to a cathode, it is possible to effectively reduce a low potential voltage deviation according to a position. Accordingly, the present invention can minimize non-uniformity in luminance and provide an electroluminescent display device with improved display quality.

In a preferred embodiment of the present invention, an auxiliary power line may be used as a repair line in order to darken a defective pixel. Accordingly, the preferred embodiment of the present invention can easily repair defective pixels, thereby increasing the manufacturing yield of the display device and reducing manufacturing cost.

1 is a block diagram schematically illustrating an organic light emitting display device.
FIG. 2 is a schematic configuration diagram of a pixel shown in FIG. 1 .
3 is a plan view illustrating an organic light emitting display device according to a first embodiment of the present invention.
4 is a diagram illustrating an arrangement example of auxiliary power lines.
5 is a cross-sectional view illustrating an organic light emitting display device according to a first embodiment of the present invention.
6 and 7 are cross-sectional views illustrating arrangement examples of auxiliary power lines.
8 and 9 are cross-sectional views illustrating an example of a connection structure between a cathode and an auxiliary power line.
10 is a schematic configuration diagram of pixels of an organic light emitting display device according to a second embodiment.
11 is a cross-sectional view schematically illustrating an example of a repaired defective pixel.

Hereinafter, preferred embodiments of the present invention will be described with reference to the accompanying drawings. Like reference numbers throughout the specification indicate substantially the same elements. In the following description, if it is determined that a detailed description of a known technology or configuration related to the present invention may unnecessarily obscure the subject matter of the present invention, the detailed description will be omitted. In describing various embodiments, the same components are representatively described at the beginning and may be omitted in other embodiments.

Terms including ordinal numbers, such as first and second, may be used to describe various components, but the components are not limited by the terms. These terms are only used for the purpose of distinguishing one component from another.

Hereinafter, for convenience of explanation, a case in which the electroluminescent display device is implemented as an organic light emitting display device including an organic light emitting material will be described as an example. The technical idea of the present invention is not limited to an organic light emitting display device and may be applied to an inorganic light emitting display device including an inorganic light emitting material.

1 is a block diagram schematically illustrating an organic light emitting display device. FIG. 2 is a schematic configuration diagram of a pixel shown in FIG. 1 .

Referring to FIG. 1 , an organic light emitting display device according to the present invention includes a display driving circuit and a display panel 10 .

The display driving circuit includes a data driving circuit 12 , a gate driving circuit 14 and a timing controller 16 to write video data voltages of an input image to pixels of the display panel 10 . The data driving circuit 12 converts the digital video data RGB input from the timing controller 16 into an analog gamma compensation voltage to generate a data voltage. The data voltage output from the data driving circuit 12 is supplied to the data lines D1 to Dm. The gate driving circuit 14 sequentially supplies a gate signal synchronized with the data voltage to the gate lines G1 to Gn to select pixels of the display panel 10 to which the data voltage is written.

The timing controller 16 inputs timing signals such as a vertical synchronization signal (Vsync), a horizontal synchronization signal (Hsync), a data enable signal (Data Enable, DE), and a main clock (MCLK) input from the host system 19. and the operation timings of the data driving circuit 12 and the gate driving circuit 14 are synchronized. The data timing control signal for controlling the data driving circuit 12 includes a source sampling clock (SSC), a source output enable signal (SOE), and the like. Gate timing control signals for controlling the gate driving circuit 14 include a gate start pulse (GSP), a gate shift clock (GSC), a gate output enable signal (Gate Output Enable (GOE)), and the like. includes

The host system 19 may be implemented as any one of a television system, a set-top box, a navigation system, a DVD player, a Blu-ray player, a personal computer (PC), a home theater system, and a phone system. The host system 19 includes a system on chip (SoC) with a built-in scaler to convert digital video data (RGB) of an input image into a format suitable for display on the display panel 10 . The host system 19 transmits timing signals Vsync, Hsync, DE, and MCLK to the timing controller 16 along with the digital video data.

The display panel 10 includes a pixel array. The pixel array includes pixels defined by data wires (D1 to Dm, where m is a positive integer) and gate wires (G1 to Gn, where n is a positive integer). Each of the pixels includes an organic light emitting diode (OLED), which is a self-light emitting element.

Further referring to FIG. 2 , in the display panel 10, a plurality of data lines DL and a plurality of gate lines GL cross each other, and pixels are disposed in each intersection area. Each pixel has an organic light emitting diode, a driving thin film transistor (hereinafter referred to as TFT) (DT) controlling the amount of current flowing through the organic light emitting diode, and a programming unit for setting the voltage between the gate and source of the driving TFT (DT). (SC).

The programming unit SC may include at least one switch TFT and at least one storage capacitor. The switch TFT is turned on in response to a gate signal from the gate line GL, thereby applying a data voltage from the data line DL to one electrode of the storage capacitor. The driving TFT (DT) controls the amount of light emitted by the organic light emitting diode by controlling the amount of current supplied to the OLED according to the level of the voltage charged in the storage capacitor. The amount of light emitted from the organic light emitting diode is proportional to the amount of current supplied from the driving TFT (DT). These pixels are connected to a high-potential voltage source (EVDD) and a low-potential voltage source (EVSS), and receive a high-potential power supply voltage and a low-potential power supply voltage, respectively, from a power generator (not shown). The TFTs constituting the pixel may be implemented as p-type or as n-type. In addition, the semiconductor layer of the TFTs constituting the pixel may include amorphous silicon, polysilicon, or oxide. Hereinafter, a case in which the semiconductor layer includes an oxide will be described as an example. The organic light emitting diode includes an anode (ANO), a cathode (CAT), and an organic compound layer interposed between the anode (ANO) and the cathode (CAT). The anode ANO is connected to the driving TFT DT.

One pixel can basically be composed of a 2T (transistor) 1C (capacitor) structure including a switching TFT, a driving TFT (DT), a storage capacitor, and an organic light emitting diode, and when a compensation circuit is added, 3T1C, 4T2C, 5T2C , 6T2C, 7T2C, etc. may be variously configured.

<First Embodiment>

3 is a plan view illustrating an organic light emitting display device according to a first embodiment of the present invention. 4 is a diagram illustrating an arrangement example of auxiliary power lines. 5 is a cross-sectional view illustrating an organic light emitting display device according to a first embodiment of the present invention. 6 and 7 are cross-sectional views illustrating arrangement examples of auxiliary power lines. 8 and 9 are cross-sectional views illustrating an example of a connection structure between a cathode and an auxiliary power line.

Referring to FIG. 3 , the organic light emitting display device according to the first embodiment of the present invention includes a display panel driver and a display panel 10 .

The display panel driver writes input image data on the display panel 10 . The display panel driver includes a source drive IC (SIC) and a source PCB (Printed Circuit Board, SPC). The source drive IC (SIC) may be mounted on a bendable flexible circuit board, for example, a chip on film (COF). In the case of a large screen display device, a plurality of source PCBs (SPCs) may be separated. One end and the other end of the COF (CO) may be respectively adhered to the display panel 10 and the source PCB (SPC) through an anisotropic conductive film (ACF).

A power supply unit (not shown) may be mounted on a source PCB (SPC). The power supply unit is driven by an input voltage supplied from the host system 19 (FIG. 1) to generate voltages required to drive the display panel driver and the display panel 10.

In the display panel 10, a display area AA and a non-display area NA outside the display area AA are defined. The display area AA includes pixels and an auxiliary power line AVSL.

Pixels may be arranged in a matrix form. Each of the pixels may include a red sub-pixel, a green sub-pixel, and a blue sub-pixel to implement full color. If necessary, each of the pixels may further include a white sub-pixel.

Each of the pixels includes an organic light emitting diode and a TFT driving the organic light emitting diode. The first organic light emitting diode includes an anode (ANO), an organic compound layer (OL), and a cathode (CAT).

An anode ANO is assigned to a corresponding subpixel and is connected to a drain electrode of a driving TFT provided in the corresponding subpixel. A source electrode of the driving TFT is connected to a power supply unit through a high potential power supply line (not shown) to receive a high potential power supply voltage. Although not shown, the high-potential power lines may extend inside the display area AA and be connected to corresponding pixels.

The organic compound layer OL may include a white pigment and may be widely applied over the entire surface of the substrate. The white pigment can be widely applied to cover the pixels. In this case, the red, green, blue, and sub-pixels may further include corresponding red, green, and blue color filters. Alternatively, the organic compound layer OL may include red, green, and blue pigments and may be separately applied to corresponding red, green, blue, and sub-pixels, respectively.

The cathode CAT is formed wide to cover the pixels arranged in the display area AA. The cathode CAT is electrically connected to the power supply unit and the low potential power line VSL to receive a low potential power supply voltage. The low potential power line VSL may extend outside the display area AA along the circumference of the display area AA. As will be described later, the cathode CAT may be connected to the low-potential power line VSL through a connection line LL including a low-resistance conductive material ( FIG. 5 ). That is, the cathode CAT may receive a low potential power supply voltage from the power supply unit through a power path including the low potential power line VSL ( FIG. 5 ) and the connection line LL ( FIG. 5 ).

The auxiliary power line AVSL is disposed within the display area AA. The auxiliary power line AVSL includes first auxiliary power lines AVSL-V and second auxiliary power lines AVSL-H.

The first auxiliary power lines AVSL-V extend in a first direction (eg, a Y-axis direction). One first auxiliary power line AVSL-V may have a different length and/or a different width from at least one other first auxiliary power line AVSL-V. That is, according to the present invention, design freedom can be secured by setting the length and/or width of the first auxiliary power line AVSL-V differently according to positions.

In the drawing, the first auxiliary power line AVSL-V is illustrated as being disposed between neighboring pixels in a second direction (eg, an X-axis direction) crossing the first direction, but is not limited thereto. no. In the drawing, the first auxiliary power line AVSL-V is illustrated as having a straight line shape, but is not limited thereto, and may be curved or may have a combination of straight and curved lines.

The first auxiliary power supply line AVSL-V is disposed under the cathode CAT with at least one insulating film interposed therebetween. The first auxiliary power line AVSL-V includes a low-resistance conductive material. The first auxiliary power line AVSL-V is connected to the cathode CAT at at least one first connection point CNT-V. At the first connection point CNT-V, the first auxiliary power line AVSL-V may be connected to the cathode CAT through a contact hole penetrating the at least one insulating layer. In the display area AA, the density of the first connection point CNT-V may be different according to positions. Assuming a specific location where the cathode CAT receives a low potential power supply voltage from the low potential power line VSL (or connection line LL), the first connection point CNT-V is further away from the specific position. ) can be increased.

In the first embodiment of the present invention, the voltage deviation according to the position can be reduced by connecting the first auxiliary power line AVSL-V formed of a low-resistance conductive material to the cathode CAT in the display area AA. Therefore, it has an advantage of reducing the luminance non-uniformity defect.

The second auxiliary power line AVSL-H extends in the second direction. One second auxiliary power line AVSL-H may have a different length and/or a different width from at least one other second auxiliary power line AVSL-H. That is, according to the present invention, design freedom can be secured by differently setting the length and/or width of the second auxiliary power line AVSL-H according to positions.

In the drawing, the second auxiliary power line AVSL-H is shown as being disposed between pixels adjacent to each other in the first direction, but is not limited thereto. In the drawing, the second auxiliary power line AVSL-H is illustrated as having a straight line shape, but is not limited thereto, and may be curved or may have a combination of straight and curved lines.

The second auxiliary power supply line AVSL-H is disposed under the cathode CAT with at least one insulating film interposed therebetween. The second auxiliary power line AVSL-H includes a low-resistance conductive material. The second auxiliary power line AVSL-H is connected to the cathode CAT at at least one second connection point CNT-H. At the second connection point CNT-H, the second auxiliary power line AVSL-H may be connected to the cathode CAT through a contact hole penetrating the at least one insulating film. On the display area AA, the density of the second connection points CNT-H may be different according to positions. Assuming a specific location where the cathode CAT receives a low potential power supply voltage from the low potential power line VSL (or connection line LL), the second connection point CNT-H is further away from the specific position. ) can be increased.

In the first embodiment of the present invention, in addition to the first auxiliary power line AVSL-V, the second auxiliary power line AVSL-H formed of a low-resistance conductive material is connected to the cathode CAT in the display area AA. Since the voltage deviation according to the position can be more effectively reduced by connecting, the luminance non-uniformity defect can be remarkably reduced.

In addition, in the first embodiment of the present invention, design freedom is improved because connectable connection points (CNT-V, CNT-H) can be selected according to positions in consideration of the arrangement of other wires and electrodes. That is, in order to implement a high-resolution display device having a high pixel per inch (PPI), since it is necessary to integrate several elements within a limited space, the degree of freedom in design is relatively significantly reduced. The first embodiment of the present invention corresponds to the state (or condition) of the position by arranging a plurality of auxiliary power lines (AVSL) extending in different directions rather than simply extending in one direction. Since the auxiliary power line AVSL connectable to the cathode CAT can be easily selected, sufficient design freedom can be secured even in a high-resolution display device to achieve the object of the present invention.

The second auxiliary power line AVSL-H may cross at least one first auxiliary power line AVSL-V, but must be perpendicular to the first auxiliary power line AVSL-V as shown in the drawing. does not intersect with That is, when viewed from a plane, an angle between the first auxiliary power line AVSL-V and the second auxiliary power line AVSL-H may be a square (dutch angle or tilt angle).

The first auxiliary power line AVSL-V and the second auxiliary power line AVSL-H may be disposed on the same layer. In this case, the first auxiliary power line AVSL-V and the second auxiliary power line AVSL-H may be connected and formed as one body. As another example, the first auxiliary power line AVSL-V and the second auxiliary power line AVSL-H may be disposed on different layers with at least one insulating layer interposed therebetween. In this case, the first auxiliary power line AVSL-V and the second auxiliary power line AVSL-H may be connected through a contact hole penetrating the at least one insulating layer.

The first auxiliary power line AVSL-V and the second auxiliary power line AVSL-H intersect each other in at least a portion of the display area AA to form a mesh structure when viewed on a plane. can be arranged to have For example, the first auxiliary power line AVSL-V and the second auxiliary power line AVSL-H may have a crossing structure in the entire area of the display area AA.

As another example, referring to FIG. 4 , the first auxiliary power line AVSL-V and the second auxiliary power line AVSL-H may have a cross structure locally in the display area AA. The partial area PA may have a higher density than other areas in which the first connection points CNT-V and/or the second connection points CNT-H are disposed per unit area. The region PA having a high density of the first connection point CNT-V and/or the second connection point CNT-H includes a cathode CAT and a low-resistance conductive material, and the first auxiliary power line AVSL- V) and/or the second auxiliary power line AVSL-H means a larger area than other areas. The partial area PA is the most distant from the specific position, assuming a specific position where the cathode CAT receives the low potential power supply voltage from the low potential power line VSL (or connection line LL). area may be Accordingly, the preferred embodiment of the present invention has the advantage of being able to supply a uniform low-potential power supply voltage to the pixels of the display panel 10 by using a relatively small number of auxiliary power lines AVSL.

More specifically, the cathode CAT is connected to the low potential power line VSL (or connection line LL) through at least one connection part CNT-P. The connection part CNT-P is located in the non-display area NA and may be defined on at least one of upper, lower, left, and right sides of the display area AA. For example, one connection part CNT-P and another connection part CNT-P may be located on different low potential power lines VSL. In this case, since the cathode CAT can receive the low-potential power supply voltage from the plurality of low-potential power lines VSL, an open defect occurs in one low-potential power line VSL or one of the low-potential power lines VSL Even if a contact failure occurs between the low-potential power line VSL and the cathode CAT, the low-potential power supply voltage can be supplied through another low-potential power line VSL, thereby preventing driving failure.

The arrangement density of the first connection point CNT-V and/or the second connection point CNT-H per unit area within the display area AA is such that the cathode CAT is connected to the low potential power supply line VSL (or connection density). It is related to the position of the connection part (CNT-P) to which the low-potential power supply voltage is supplied from the wiring (LL). For example, when the connection part CNT-P is defined on the left and right sides of the display area AA, the first connection point CNT-V and/or the second connection point CNT-H are at the center of the display area AA. can be focused on As another example, when the connection part CNT-P is defined on the left (or right) side of the display area AA, the first connection point CNT-V and/or the second connection point CNT-H may be defined in the display area ( AA) can be centered on the right (or left) side. In this way, according to the present invention, the arrangement density of the first connection point (CNT-V) and/or the second connection point (CNT-H) per unit area is set differently in correspondence with the distance from the connection part (CNT-P), It has the advantage of being able to more effectively reduce the voltage deviation according to the position. In this case, since the voltage deviation according to the position can be minimized even when a relatively small number of first connection points (CNT-V) and/or second connection points (CNT-H) are formed, process defects, for example, the first It has an advantage of reducing process defects that may occur when forming the connection point CNT-V and the second connection point CNT-H. Referring to FIG. 5, the organic light emitting display according to the first embodiment of the present invention The device includes a substrate SUB on which a non-display area NA and a display area AA are defined. Although not shown, an encapsulation layer covering the thin film transistor T and the organic light emitting diode OLE may be further provided on the substrate SUB. The encapsulation layer may protect internal elements from moisture and oxygen that may be introduced from the outside.

The substrate SUB may be made of glass or plastic material. For example, the substrate SUB may be formed of a plastic material such as polyimide (PI), polyethylene terephthalate (PET), polyethylene naphthalate (PEN), or polycarbonate (PC), and may have flexible characteristics.

A low potential power line VSL is formed on the non-display area NA of the substrate SUB. As shown, the low potential power line VSL may be formed of the same material on the same layer as the source/drain electrodes S and D. However, it is not limited thereto. The low potential power voltage supplied from the power supply unit may be applied to the cathode CAT through the low potential power line VSL.

On the display area AA of the substrate SUB, a thin film transistor T and an organic light emitting diode OLE connected to the thin film transistor T are formed. A functional layer BSM and a buffer layer BUF may be formed between the substrate SUB and the thin film transistor T. The functional layer BSM may be disposed to overlap the semiconductor layer of the thin film transistor T, particularly the channel, and may function to protect the semiconductor device from external light. Alternatively, the functional layer (BSM) may function as one electrode of the storage capacitor. The buffer layer BUF may block ions or impurities from diffusing from the substrate SUB and may block penetration of external moisture.

The thin film transistor T includes a semiconductor layer A, a gate electrode G, and source/drain electrodes S and D. A gate insulating layer GI and a gate electrode G are disposed on the semiconductor layer A. The gate insulating layer GI insulates the gate electrode G, and may be made of a silicon oxide layer (SiOx), but is not limited thereto. The gate insulating layer GI may be formed to cover the entire surface of the substrate SUB. Although not shown, the gate insulating film GI and the gate electrode G may be patterned using the same mask, and in this case, the gate insulating film GI and the gate electrode G may have the same planar shape.

The gate electrode G is disposed to overlap the semiconductor layer A with the gate insulating film GI interposed therebetween. The gate electrode (G) is made of copper (Cu), molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), or tantalum (Ta). and tungsten (W), or a single layer or multiple layers of alloys thereof.

An interlayer insulating layer IN is disposed on the gate electrode G. The interlayer insulating film (IN) insulates the gate electrode (G) and the source/drain electrodes (S, D) from each other, and may be made of a silicon oxide film (SiOx), a silicon nitride film (SiNx), or a multilayer thereof, but is limited thereto It is not.

Source/drain electrodes S and D are disposed on the interlayer insulating film IN. The source electrode (S) and the drain electrode (D) are spaced apart from each other by a predetermined distance. The source electrode S contacts one side of the semiconductor layer A through a source contact hole penetrating the interlayer insulating film IN. The drain electrode D contacts the other side of the semiconductor layer A through the drain contact hole penetrating the interlayer insulating layer IN.

The source electrode (S) and the drain electrode (D) may be formed of a single layer or multiple layers, and in the case of a single layer, molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti, It may be made of any one selected from the group consisting of nickel (Ni), neodymium (Nd) and copper (Cu) or an alloy thereof. In addition, when the source electrode (S) and the drain electrode (D) are multi-layered, they are a double layer of molybdenum/aluminum-neodymium, molybdenum/aluminum, titanium/aluminum, or copper/motitanium, or molybdenum/aluminum-neodymium/molybdenum or molybdenum. /Aluminum/molybdenum, titanium/aluminum/titanium, or motitanium/copper/motitanium triple layers.

A passivation film (PAS) is positioned on the thin film transistor (T). The passivation film PAS protects the thin film transistor T and may be formed of silicon oxide (SiOx), silicon nitride (SiNx), or a multilayer thereof.

A planarization layer OC is positioned on the passivation layer PAS. The planarization film (OC) is to planarize the lower step, and may be made of an organic material such as photo acryl, polyimide, benzocyclobutene resin, or acrylate. there is. If necessary, either the passivation layer PAS or the planarization layer OC may be omitted.

An organic light emitting diode (OLE) is positioned on the planarization layer (OC). The organic light emitting diode (OLE) includes an anode (ANO), an organic compound layer (OL), and a cathode (CAT). More specifically, the anode ANO is positioned on the planarization layer OC. The anode ANO is connected to the drain electrode D of the thin film transistor T through a contact hole penetrating the passivation film PAS and the planarization film OC. The anode ANO may function as a reflective electrode by including a reflective layer. The reflective layer may be made of aluminum (Al), copper (Cu), silver (Ag), nickel (Ni), or alloys thereof, preferably made of APC (silver/palladium/copper alloy). The anode ANO may be formed of multiple layers including a reflective layer.

A bank layer BN partitioning sub-pixels is positioned on the substrate SUB on which the anode ANO is formed. The bank layer BN may be made of an organic material such as polyimide, benzocyclobutene series resin, or acrylate. A central portion of the anode ANO exposed by the bank layer BN may be defined as an emission area. The bank layer BN may be disposed to cover a side end of the anode ANO while exposing a central portion of the anode ANO.

An organic compound layer OL is positioned on the anode ANO exposed by the bank layer BN. The organic compound layer OL may be divided and disposed for each corresponding sub-pixel, or may be integrally formed widely over the entire surface of the substrate SUB. The organic compound layer (OL) is a layer that emits light by combining electrons and holes, and includes an emission layer (EML), a hole injection layer (HIL), a hole transport layer (HTL), an electron Any one or more of an electron transport layer (ETL) and an electron injection layer (EIL) may be further included.

A cathode CAT is positioned on the organic compound layer OL. The cathode CAT may be formed widely on the entire surface of the substrate SUB to cover the pixels. The cathode CAT may be formed of a transparent conductive material such as indium tin oxide (ITO) or indium zinc oxide (IZO), and may be formed of magnesium (Mg), calcium (Ca), It may be made of aluminum (Al), silver (Ag), or an alloy thereof.

The cathode CAT may directly contact the low-potential power line VSL to receive a low-potential power supply voltage. In this case, the cathode CAT may be connected to the low potential power line VSL through the passivation contact hole CH penetrating the passivation film PAS. Preferably, the cathode CAT is in direct contact with the connection line LL connected to the low potential power line VSL, and supplies a low potential power voltage through the connection line LL connected to the low potential power line VSL. can receive In this case, the connection wire LL may be connected to the low potential power supply wire VSL through the passivation contact hole CH passing through the passivation film PAS, and the cathode CAT may be connected to the bank contact hole passing through the bank. BH) may be connected to the connection wire LL. Alternatively, although not shown, the connection line LL may be connected to the low potential power line VSL through the passivation contact hole CH penetrating the passivation film PAS, and the cathode CAT may be connected to the connection line LL can come into direct contact with A material constituting the connection line LL has a lower specific resistance than a material constituting the cathode CAT.

In order for the cathode CAT to directly contact the low-potential power line VSL and receive the low-potential power supply voltage, the cathode CAT including a material having a high specific resistance must be formed relatively wide. Considering the object of the present invention to reduce the deviation of the low potential power supply voltage according to the position, the cathode (CAT) is formed to have a minimum area that can be designed without deteriorating the original function compared to the above-described connection structure, and the low potential It may be desirable to connect the power line VSL and the cathode CAT through a connection line LL including a low-resistance material. For example, the cathode CAT is provided in the display area AA to cover the pixels and is electrically connected to a low potential power line VSL disposed in the non-display area NA through the connection line LL. can

An auxiliary power line AVSL is formed on the display area AA of the substrate SUB. The auxiliary power supply line AVSL may be disposed under the cathode CAT with at least one insulating layer interposed therebetween. The auxiliary power line (AVSL) may be composed of a single layer or multiple layers, and in the case of a single layer, molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), It may be made of any one selected from the group consisting of neodymium (Nd) and copper (Cu) or an alloy thereof. In addition, when the auxiliary power line (AVSL) is multi-layered, it is a double layer of molybdenum/aluminum-neodymium, molybdenum/aluminum, titanium/aluminum, or copper/motitanium, or molybdenum/aluminum-neodymium/molybdenum, molybdenum/aluminum/molybdenum, It may be made of a triple layer of titanium/aluminum/titanium or motitanium/copper/motitanium.

As shown in FIG. 5 , the auxiliary power line AVSL is formed on the passivation film PAS and disposed below the cathode CAT with the planarization film OC and the bank layer BN interposed therebetween. can However, it is not limited thereto, and as shown in FIG. 6, the auxiliary power line AVSL may be formed of the same material on the same layer as the source/drain electrodes S and D (Fig. 6(a) )), may be formed of the same material on the same layer as the gate electrode G (FIG. 6(b)), and may be formed of the same material on the same layer as the functional layer BSM (FIG. 6(c) )). In this case, there is no need to separately perform an additional process for forming the auxiliary power line AVSL. Accordingly, it is possible to reduce the number of processes, thereby reducing manufacturing time and cost, and having an advantage of significantly improving product yield by reducing process defects.

Referring to FIG. 7 , as described above, the auxiliary power line AVSL may include a first auxiliary power line AVSL-V and a second auxiliary power line AVSL-H, and the first auxiliary power line AVSL-H. AVSL-V and the second auxiliary power line AVSL-H may be disposed on different layers with at least one insulating layer PAS interposed therebetween.

For example, the first auxiliary power line AVSL-V is disposed under the cathode CAT with at least one insulating film BN and OC interposed therebetween, and penetrates the at least one insulating film BN and OC. may be in contact with the cathode CAT through the auxiliary contact hole VH. The second auxiliary power line AVSL-H is disposed under the first auxiliary power line AVSL-V with at least one insulating film PAS interposed therebetween, and is connected to pass through the at least one insulating film PAS. It may be in contact with the first auxiliary power line AVSL-V through the contact hole PH. The second auxiliary power line AVSL-H may be electrically connected to the cathode CAT through the first auxiliary power line AVSL-V.

When the organic light emitting display device according to the present invention is implemented as a top emission type, it is necessary to secure a sufficient area of the anode ANO in order to relatively widen the aperture ratio. Therefore, when the organic light emitting display device according to the present invention is implemented as a top emission type, the anode ANO is formed to have the maximum designable area and the auxiliary power line ( AVSL) is preferably not formed on the same layer as the anode ANO.

When the cathode CAT and the auxiliary power line AVSL are disposed with two or more insulating films BN and OC interposed therebetween, as shown in FIG. 5, one through the two or more insulating films BN and OC The cathode CAT and the auxiliary power line AVSL may be directly contacted through the auxiliary contact hole VH.

As another example, when the cathode (CAT) and the auxiliary power line (AVSL) are disposed with two or more insulating films (BN, OC) interposed therebetween, as shown in FIG. 8, the cathode (CAT) and the auxiliary power line (AVSL) It may further include at least one auxiliary electrode LVSL disposed therebetween, and the cathode CAT and the auxiliary power line AVSL may be connected through the at least one auxiliary electrode LVSL. The auxiliary electrode LVSL is disposed below the cathode CAT with at least one insulating film BN interposed therebetween, and the cathode ( CAT). The auxiliary electrode LVSL is disposed on the auxiliary power line AVSL with at least one insulating film OC interposed therebetween, and is provided through a second auxiliary contact hole VH2 penetrating the at least one insulating film OC. It is in contact with the power line (AVSL).

In the case of forming the auxiliary contact hole VH as shown in FIG. 5 , the upper part of the contact hole is continuously exposed to the etchant during the process of penetrating two or more insulating layers, and thus the hole area may become excessively large. In contrast, when the auxiliary contact holes VH1 and VH2 are divided and formed as shown in FIG. 8 , the hole area of the contact hole can be controlled to a certain level or less.

The first auxiliary contact hole VH1 and the second auxiliary contact hole VH2 may be formed to overlap each other as shown in FIG. 8 or may be shifted at regular intervals as shown in FIG. 9 . On the premise that the auxiliary electrode LVSL is formed on the same layer as the anode ANO, when the first auxiliary contact hole VH1 and the second auxiliary contact hole VH2 are shifted and formed as shown in FIG. 9 , the anode The area occupied by (ANO) is reduced. When the organic light emitting display device is implemented as a top emission type, a decrease in the area occupied by the anode ANO causes a decrease in aperture ratio, so the structure shown in FIG. 8 may be preferable.

The first embodiment of the present invention has an advantage of minimizing the luminance non-uniformity defect by effectively reducing the low potential voltage deviation according to the position. Accordingly, the first embodiment of the present invention can provide an organic light emitting display device with improved display quality.

<Second Embodiment>

In the process of manufacturing a pixel circuit, a defect in which each pixel is not normally driven may occur due to deterioration of characteristics of the organic light emitting diode and thin film transistor and occurrence of a short circuit between electrodes and/or wires. For example, when the source electrode and drain electrode of the driving thin film transistor are short-circuited, the driving thin film transistor is not normally driven and the voltage applied to the source electrode may be directly applied to the drain electrode. In this case, since the driving thin film transistor is not turned off and maintained in an on state, a bright point defect in which the organic light emitting diode is continuously turned on may occur. Such bright spot defects have high visibility, so that a user can recognize them immediately. In contrast, dark spot defects are relatively low in visibility, and even if they occur in some pixels, they can be commercialized. Accordingly, the second embodiment of the present invention proposes a novel repair structure capable of turning a pixel having a bright point defect into a dark point, considering that the visibility of the dark point defect is relatively low compared to the bright point defect.

10 is a schematic configuration diagram of pixels of an organic light emitting display device according to a second embodiment. 11 is a cross-sectional view schematically illustrating an example of a repaired defective pixel.

Referring to FIGS. 10 and 11 , data lines DL, gate lines GL, and an auxiliary power supply line AVSL are disposed in the display panel according to the second embodiment of the present invention. A pixel may be defined by an intersection structure of a data line DL and a gate line GL. Each pixel includes an organic light emitting diode, a driving transistor DT for controlling the amount of current flowing through the organic light emitting diode, and a programming unit SC for setting a gate-source voltage of the driving transistor DT. A low-potential power supply voltage is applied to the auxiliary power line AVSL connected to the cathode CAT.

The second embodiment of the present invention determines whether a pixel has a driving defect and proceeds with an inspection process to repair it. The inspection process includes an inspection step of extracting coordinates where bright spot defects occur, and a repair step of darkening pixels corresponding to the extracted coordinates.

The repair step includes a process of connecting the drain electrode D of the driving transistor DT disposed in the pixel where the defect occurs to the auxiliary power line AVSL. The auxiliary power line (AVSL) can be used as a repair line during the inspection process. That is, by applying a low-potential power supply voltage to the drain electrode D of the driving transistor DT disposed in the pixel where the defect occurs, the corresponding pixel can be darkened.

The drain electrode D of the driving transistor DT and the auxiliary power line AVSL may be connected through a welding process. In the second embodiment of the present invention, since the auxiliary power line AVSL to which the low potential power supply voltage is applied is disposed in the display area, the drain electrode D of the driving transistor DT within the pixel determined to be defective is assisted. It can be easily connected to the power wiring (AVSL). In addition, since the auxiliary power line AVSL according to the second embodiment of the present invention is arranged in a mesh structure and can be arranged adjacent to all pixels, a connection point with the drain electrode D can be easily selected. . Accordingly, the second embodiment of the present invention has an advantage of increasing the manufacturing yield of the organic light emitting display device and reducing the manufacturing cost.

Through the above description, those skilled in the art will be able to make various changes and modifications without departing from the spirit of the present invention. Therefore, the technical scope of the present invention is not limited to the contents described in the detailed description of the specification, but should be defined by the claims.

10: display panel AA: display area
NA: Non-display area VSL: Low potential power wiring
AVSL: Auxiliary Power Wiring CAT: Cathode
CNT: connection point LL: connection wiring
LVSL: auxiliary electrode

Claims (27)

A display panel including a display area and a non-display area outside the display area;
A plurality of pixels are disposed in the display area;
At least one low potential power line to which a low potential voltage is applied is disposed in the non-display area;
Each of the plurality of pixels,
thin film transistor;
an anode electrically connected to the thin film transistor;
a light emitting layer formed on the anode; and
Including a cathode formed on the light emitting layer,
The display area includes a first auxiliary power line and a second auxiliary power line in a mesh shape contacting the cathode,
wherein the first auxiliary power line and the second auxiliary power line are connected through a contact hole penetrating at least one insulating layer. According to claim 1,
The display panel includes a connection wire including a conductive material having a lower specific resistance than a material constituting the cathode,
wherein the cathode and the low potential power line are electrically connected through the connection line.
According to claim 2,
The connection wire is made of the same material on the same layer as the anode. According to claim 2,
The connecting wire is
at least one insulating film disposed between the connection wire and the low potential power wire and connected to the low potential power wire through a first contact hole penetrating the at least one insulating film disposed between the connection wire and the low potential power wire; An electroluminescent display device connected to the cathode through a penetrating second contact hole.
According to claim 4,
The plurality of pixels include a bank covering an end of the anode,
and at least one insulating layer disposed between the connection wire and the cathode includes the bank.
According to claim 1,
The thin film transistor is a driving transistor including a semiconductor layer, a gate electrode, and a source/drain electrode,
wherein the plurality of pixels include a functional layer disposed overlapping the semiconductor layer with at least one insulating layer interposed therebetween.
According to claim 6,
The low potential power line is formed of the same material on the same layer as any one of the semiconductor layer, the gate electrode, and the source/drain electrode.
delete According to claim 1,
and a connection portion disposed on one side of the non-display area and electrically connecting the cathode and the low potential power line. According to claim 1,
The first auxiliary power wire is disposed in a first direction, and the second auxiliary power wire is disposed in a second direction crossing the first direction. According to claim 9,
An area in which the cathode and the first and second auxiliary power lines contact each other is disposed within the display area;
The electroluminescence display device of claim 1 , wherein a density of an area where the cathode contacts the first and second auxiliary power lines is not uniform within the display area. According to claim 10,
The display area is
an intersection area where the first and second auxiliary power lines cross each other;
a first connection point where the first auxiliary power line and the cathode are in contact;
a second connection point where the second auxiliary power line and the cathode are in contact; and
Including a partial region that is a region with a relatively high density in which at least one of the first and second connection points per unit area is disposed;
The partial area is an area most separated from the low potential power line.
According to claim 2,
The low-potential power wiring includes a first low-potential power wiring and a second low-potential power wiring formed to be spaced apart from the first low-potential power wiring;
The connection wire includes a first connection part and a second connection part formed spaced apart from the first connection part,
wherein the cathode is connected to the first low potential power line through the first connection part and connected to the second low potential power line through the second connection part. According to claim 13,
The first connection part is formed on the left edge of the display area, and the second connection part is disposed on the right edge of the display area.
and an area in which the cathode and the first and second auxiliary power lines contact each other is in a central portion of the display area. delete According to claim 10,
The display panel,
Further comprising an auxiliary electrode disposed between the cathode and the first and second auxiliary power lines,
The auxiliary electrode is
At least one insulating film disposed between the auxiliary electrode and the first and second auxiliary power lines and connected to the cathode through a first contact hole penetrating at least one insulating film disposed between the auxiliary electrode and the cathode. connected to the first and second auxiliary power lines through a second contact hole penetrating the .
According to claim 10,
The thin film transistor,
Including a semiconductor layer, a gate electrode and a source / drain electrode,
At least one of the first and second auxiliary power lines,
An electroluminescent display device comprising the same material on the same layer as any one of the gate electrode and the source/drain electrode. According to claim 6,
Wherein the semiconductor layer is polysilicon or oxide.
According to claim 18,
The plurality of pixels,
a programming unit connected to the driving transistor;
a data wire disposed in the same direction as the low potential power wire; and
Further comprising a gate wire crossing the data wire,
The programming department,
a switch transistor including a gate electrode connected to the gate line, one electrode connected to the data line, and another electrode; and
An electroluminescent display device comprising a storage capacitor connected to the other electrode.
According to claim 19,
The functional layer is an electrode of the storage capacitor, the electroluminescent display device.
According to claim 1,
The light emitting layer includes a white pigment and covers the plurality of pixels;
and red, green, and blue color filters corresponding to each of the plurality of pixels.
According to claim 1,
The light emitting layer includes red, green, and blue pigments, and is disposed to correspond to each of the plurality of pixels. According to claim 1,
The electroluminescent display device of claim 1 , wherein the low potential power wiring has a combination of a straight line and a curved line. According to claim 1 or 13,
The display panel includes a substrate on which the plurality of pixels are disposed;
Wherein the substrate is polyimide (PI), polyethylene terephthalate (PET), polyethylene naphthalate (PEN), polycarbonate (PC), or glass. According to claim 7,
The low potential power wiring is a single layer or a multi-layer made of any one selected from copper, molybdenum, aluminum, chromium, gold, titanium, nickel, neodymium, tantalum, and tungsten, or an alloy thereof. According to claim 1,
wherein the low potential power line is connected along a circumference of the display area outside the display area. 27. The method of claim 26,
wherein the cathode directly contacts the low potential power line.