KR20180008955A - Display device - Google Patents

Abstract

In the present invention, provided is a display device capable of reducing a step difference of an overcoat layer of a sub-pixel adjacent to a white sub-pixel. According to an embodiment of the present invention, the display device comprises a substrate, a buffer layer, a thin film transistor, a passivation film, a color filter, an overcoat layer, and an organic light emitting diode. The buffer layer is disposed on the substrate, the thin film transistor is disposed on the buffer layer, and the passivation film is disposed on the thin film transistor. The color filter is disposed on the passivation film, and is spaced apart from the thin film transistor. The overcoat layer is disposed on the color filter. The organic light emitting diode is positioned on the overcoat layer, and is connected to the thin film transistor. The buffer layer includes at least one hole, and the hole overlaps the color filter. A short between electrodes can be prevented.

Description

Display device {DISPLAY DEVICE}

BACKGROUND OF THE INVENTION 1. Field of the Invention [0001] The present invention relates to a display device, and more particularly, to a display device capable of preventing a short circuit between electrodes by reducing a stepped portion by a color filter.

As the information society develops, the demand for display devices for displaying images is increasing in various forms. The display field has rapidly changed to a thin, light, and large-area flat panel display device (FPD) that replaces bulky cathode ray tubes (CRTs). The flat panel display includes a liquid crystal display (LCD), a plasma display panel (PDP), an organic light emitting display (OLED), and an electrophoretic display device : ED).

Among these organic electroluminescent display devices, self-luminous elements emit self-luminous elements, which have the advantage of high response speed and high luminous efficiency, brightness and viewing angle. Particularly, the organic light emitting display device can be formed on a flexible plastic substrate, and can be driven at a lower voltage than a plasma display panel (PDP) or an inorganic electroluminescence (EL) display, It is relatively small and has an advantage of excellent color.

The organic light emitting display includes three subpixels of red (R), green (G), and blue (B) or four subpixels of red (R), green (G), blue (B), and white And a plurality of unit pixels including a plurality of unit pixels. When three subpixels are included as one unit pixel, the red, green, and blue light emission of each subpixel may be directly emitted to realize full color. If four subpixels are included as one unit pixel, A white color is emitted in the light emitting layer of the pixels, and red, green, and blue color filters are provided in each sub-pixel to realize full color. At this time, since the white subpixel emits white light in the light emitting layer, no color filter is provided.

FIG. 1 is a cross-sectional view of a conventional organic light emitting diode display, which is a cross-sectional view of a red subpixel with a color filter and a white subpixel without a color filter.

Referring to FIG. 1, a buffer layer BUF and an interlayer insulating film ILD are positioned on a substrate SUB, and a data line DL and a power source line VL are located on an interlayer insulating film ILD. At this time, the data line DL is located in the white subpixel WSP and the power supply line VL is located in the red subpixel RSP. The passivation film PAS is positioned on the data line DL and the power supply line VL and the red color filter R_CF is located on the red subpixel RSP. Since the white subpixel WSP emits white light, the color filter is not located. The overcoat layer OC is positioned on the substrate SUB on which the white subpixel WSP and the red subpixel RSP are formed and the first electrode ANO is positioned on the overcoat layer OC. Then, the bank layer BNK is positioned to partition the white subpixel WSP and the red subpixel RSP. The light emitting layer (EML) is located on the first electrode (ANO) and the second electrode (CAT) is located on the light emitting layer (EML).

As described above, the red subpixel (RSP) is provided with a red color filter (R_CF) for converting white light emitted from the light emitting layer to red, while the white subpixel (WSP) is not provided with a color filter. Therefore, a large step is formed between the red subpixel RSP with the red color filter R_CF and the white subpixels WSP without the color filter. The overcoat layer OC formed on the substrate SUB including the red color filter R_CF is coated by a solution process. Due to the step formed on the red subpixel RSP and the white subpixel WSP, (R_CF).

The first electrode ANO is laminated and patterned on the overcoat layer OC. When the first electrode ANO is stacked on the exposed red color filter R_CF, the first electrode ANO and the color filter The first electrode ANO is outwardly angled because the adhesive force is poor. The edge of the first electrode ANO is not covered with the bank layer BNK and the edge of the first electrode ANO is also exposed by the light emitting layer EML formed on the first electrode ANO, There is a problem that the one electrode ANO and the second electrode CAT are short-circuited.

An object of the present invention is to provide a display device capable of preventing a short circuit between electrodes by reducing a step generated by a color filter.

According to an aspect of the present invention, a display device includes a substrate, a buffer layer, a thin film transistor, a passivation layer, a color filter, an overcoat layer, and an organic light emitting diode. The buffer layer is located on the substrate, the thin film transistor is located on the buffer layer, and the passivation film is located on the thin film transistor. The color filter is located on the passivation film and is separated from the thin film transistor. The overcoat layer is located on the color filter. The organic light emitting diode is positioned on the overcoat layer and connected to the thin film transistor. The buffer layer includes at least one hole and the hole overlaps with the color filter.

The holes in the buffer layer surround the color filter in a plane.

The area of the hole of the buffer layer is larger than the area of the color filter.

Holes in the buffer layer overlap at least one edge of the color filter.

The at least one hole includes at least one buffer layer pattern therein.

The organic light emitting diode includes a light emitting portion to which the light blasts, and at least one buffer layer pattern overlaps the light emitting portion.

At least one of the buffer layer patterns is spaced apart from the edge of the color filter.

The buffer layer has a thickness of 10 to 1000 nm.

Organic light emitting diodes are backlit.

Also, a display device according to an embodiment of the present invention includes a substrate, a buffer layer, a thin film transistor, a passivation film, a color filter, an overcoat layer, and an organic light emitting diode. The substrate includes colored subpixels tangent to at least white subpixels and white subpixels. The buffer layer is located on the front side of the substrate, and the thin film transistor is located on the white subpixel and the colored subpixel, respectively. The passivation film is located on the thin film transistor. The color filter is located on the passivation film in the colored subpixel, and is spaced apart from the thin film transistor. The overcoat layer covers the color filter and is located on the front side of the substrate. The organic light emitting diode is located on the overcoat layer and is located in the white subpixel and the colored subpixel, respectively. In the colored subpixel, the buffer layer includes at least one hole, and the hole overlaps with the color filter.

The white subpixels do not include holes in the color filter and buffer layer.

The display device according to an embodiment of the present invention may reduce the distance from the substrate surface to the upper surface of the color filter by forming a hole in the buffer layer so as to overlap with the color filter. Thus, the step of the overcoat layer between the white subpixel without the color filter and the red subpixel and the green subpixel adjacent to the white subpixel is reduced, so that the red and green color filters are not exposed out of the overcoat layer. Therefore, the present invention can prevent a short between the first electrode and the second electrode, thereby preventing the defect of the dark spot of the sub pixel.

1 is a cross-sectional view of a conventional OLED display.
2 is a schematic block diagram of an organic light emitting display;
3 is a first exemplary view showing a circuit configuration of a subpixel.
4 is a second exemplary diagram showing a circuit configuration of a subpixel.
5 is a plan view of an OLED display according to a first embodiment of the present invention.
6 is a cross-sectional view taken along line I-I 'of FIG. 5;
FIG. 7 is a plan view schematically illustrating red, white, green, and blue subpixels according to the first embodiment of the present invention; FIG.
8 is a cross-sectional view showing a part of an organic light emitting diode display according to a first embodiment of the present invention.
9 is a sectional view of an OLED display according to a second embodiment of the present invention.
10 is a cross-sectional view illustrating a part of an organic light emitting diode display according to a second embodiment of the present invention.
11 is a plan view schematically illustrating red, white, green, and blue subpixels according to a second embodiment of the present invention.
12 is a sectional view of an OLED display according to a third embodiment of the present invention;
13 is a cross-sectional view of a part of an organic light emitting diode display according to a third embodiment of the present invention.
FIG. 14 is a plan view schematically illustrating red, white, green, and blue subpixels according to a third embodiment of the present invention; FIG.

Hereinafter, preferred embodiments of the present invention will be described with reference to the accompanying drawings. Like reference numerals throughout the specification denote substantially identical components. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS In the following description, a detailed description of known technologies or configurations related to the present invention will be omitted when it is determined that the gist of the present invention may be unnecessarily obscured. In addition, the component names used in the following description may be selected in consideration of easiness of specification, and may be different from the parts names of actual products.

A display device according to the present invention is a display device having a color filter, and may be an organic light emitting display, a liquid crystal display, an electrophoretic display, or the like. In the present invention, an organic light emitting display will be described as an example. The organic light emitting display includes a light emitting layer made of an organic material between a first electrode, which is an anode, and a second electrode, which is a cathode. Therefore, the holes supplied from the first electrode and the electrons supplied from the second electrode are combined in the light emitting layer to form excitons as a hole-electron pair, and the excitons emit light due to energy generated when the excitons return to the ground state Emitting display device.

The organic light emitting display includes a front emission type in which light is emitted upward and a bottom emission type in which light is emitted in a lower portion. However, the OLED display of the present invention is an example of a back emission type in which light is emitted downward. However, the present invention is not limited thereto.

Hereinafter, embodiments of the present invention will be described with reference to the accompanying drawings.

FIG. 2 is a schematic block diagram of an organic light emitting display device, FIG. 3 is a first exemplary view showing a circuit configuration of a subpixel, and FIG. 4 is a second exemplary view showing a circuit configuration of a subpixel.

2, the OLED display includes an image processing unit 10, a timing control unit 20, a data driving unit 30, a gate driving unit 40, and a display panel 50.

The image processing unit 10 outputs a data enable signal DE together with a data signal DATA supplied from the outside. The image processing unit 10 may output at least one of a vertical synchronization signal, a horizontal synchronization signal, and a clock signal in addition to the data enable signal DE, but these signals are omitted for convenience of explanation. The image processing unit 10 is formed on the system circuit board in the form of an IC (Integrated Circuit).

The timing controller 20 receives a data signal DATA from a video processor 10 in addition to a data enable signal DE or a driving signal including a vertical synchronizing signal, a horizontal synchronizing signal and a clock signal.

The timing control unit 20 generates a gate timing control signal GDC for controlling the operation timing of the gate driving unit 40 and a data timing control signal DDC for controlling the operation timing of the data driving unit 30 based on the driving signal. . The timing control unit 20 is formed on the control circuit board in the form of an IC.

The data driver 30 samples and latches the data signal DATA supplied from the timing controller 20 in response to the data timing control signal DDC supplied from the timing controller 20 and converts the sampled data signal into a gamma reference voltage . The data driver 30 outputs the data signal DATA through the data lines DL1 to DLn. The data driver 30 is formed on the data circuit board in the form of an IC.

The gate driving unit 40 outputs the gate signal while shifting the level of the gate voltage in response to the gate timing control signal GDC supplied from the timing control unit 20. [ The gate driver 40 outputs a gate signal through the gate lines GL1 to GLm. The gate driver 40 is formed on the gate circuit board in the form of an IC or is formed on the display panel 50 in a gate in panel manner.

The display panel 50 displays an image corresponding to the data signal DATA and the gate signal supplied from the data driver 30 and the gate driver 40. The display panel 50 includes subpixels SP for displaying an image.

Referring to FIG. 3, one sub-pixel includes a switching transistor SW, a driving transistor DR, a compensation circuit CC, and an organic light emitting diode (OLED). The organic light emitting diode OLED operates to emit light in accordance with the driving current generated by the driving transistor DR.

The switching transistor SW is operated so that the data signal supplied through the first data line DL1 is stored as a data voltage in the capacitor in response to the gate signal supplied through the first gate line GL1. The driving transistor DR operates so that a driving current flows between the high potential power supply line VDD and the low potential power supply line GND in accordance with the data voltage stored in the capacitor. The compensation circuit CC is a circuit for compensating the threshold voltage and the like of the driving transistor DR. Also, the capacitor connected to the switching transistor SW or the driving transistor DR may be located inside the compensation circuit CC.

The compensation circuit CC consists of one or more thin film transistors and a capacitor. The configuration of the compensation circuit CC varies greatly depending on the compensation method, and a detailed illustration and description thereof will be omitted.

In addition, as shown in FIG. 4, when the compensation circuit CC is included, the sub-pixel further includes a signal line and a power supply line for driving a compensating thin film transistor and supplying a specific signal or power. The added signal line may be defined as a 1-2 gate line GL1b for driving the compensating thin film transistor included in the subpixel. The added power supply line may be defined as an initialization power supply line (INIT) for initializing a specific node of the subpixel to a specific voltage. However, this is merely one example, but is not limited thereto.

In FIGS. 3 and 4, one compensator CC is included in one subpixel. However, the compensation circuit CC may be omitted when the subject of compensation is located outside the sub-pixel such as the data driver 30 or the like. That is, one subpixel is basically composed of a 2T (Transistor) 1C (Capacitor) structure including a switching transistor SW, a driving transistor DR, a capacitor and an organic light emitting diode (OLED) 3T1C, 4T2C, 5T2C, 6T2C, 7T2C, or the like may be used.

Although the compensation circuit CC is shown between the switching transistor SW and the driving transistor DR in FIGS. 3 and 4, the compensation circuit CC is located between the driving transistor DR and the organic light emitting diode OLED. It is possible. The position and structure of the compensation circuit CC are not limited to Fig. 3 and Fig.

Various structures of an organic light emitting display device having a color filter are described below.

≪ Embodiment 1 >

FIG. 5 is a plan view of an OLED display according to a first embodiment of the present invention, FIG. 6 is a cross-sectional view taken along line I-I 'of FIG. 5, Red, white, green, and blue subpixels. FIG. 8 is a cross-sectional view illustrating a portion of an organic light emitting diode display according to the first embodiment of the present invention. Referring to FIG.

The organic light emitting display according to the first embodiment of the present invention includes a plurality of sub-pixels arranged to emit light of red (R), white (W), green (G), and blue (B) ). Also, the plurality of subpixels may be provided as cyan, magenta, and yellow pixels, and any known pixel structure is applicable. Although a plurality of subpixels are shown in a stripe manner in which red (R), white (W), green (G) and blue (B) are arranged in order on one row, .

In this embodiment, red and white subpixels of red, white, green, and blue are described as an example.

5, the organic light emitting diode display according to the first embodiment of the present invention includes a gate line GL, a data line DL and a power line VL intersecting with the gate line GL, So that the red subpixel RSP and the white subpixel WSP are partitioned. The red subpixel RSP and the white subpixel WSP of the present invention mean an inner region partitioned by the intersection of the gate line GL, the data line DL and the power supply line VL. Although it is shown that the gate line GL is not disposed under the red subpixel RSP and the white subpixel WSP in the drawing, the red subpixel RSP and the white subpixel WSP Pixels WSP can be defined.

A switching thin film transistor S_TFT, a driving thin film transistor D_TFT and a capacitor Cst are arranged in each of the red subpixels RSP and the white subpixels WSP of the present invention and the driving thin film transistor D_TFT A light emitting diode (not shown) is disposed. The switching thin film transistor S_TFT functions to select a pixel. The switching thin film transistor S_TFT includes a semiconductor layer 121, a gate electrode 123 branched from the gate line GL, a source electrode 124 branched from the data line DL, and a drain electrode 126 . The capacitor Cst includes a capacitor lower electrode 127 connected to the drain electrode 126 of the switching thin film transistor S_TFT and a capacitor upper electrode 128 connected to the power source line VL. The driving thin film transistor D_TFT serves to drive the first electrode ANO of the pixel selected by the switching thin film transistor S_TFT. The driving thin film transistor D_TFT includes a semiconductor layer 120, a gate electrode 130 connected to the capacitor lower electrode 128, a source electrode 140 and a drain electrode 145 branched from the power source line VL. An organic light emitting diode (not shown) includes a first electrode ANO connected to the drain electrode 145 of the driving thin film transistor D_TFT, a light emitting layer (not shown) including a light emitting layer formed on the first electrode ANO, Electrode (not shown).

Hereinafter, description will be made with reference to FIG. 6 which is a cross-sectional view taken along the perforated line I-I 'in FIG.

Referring to FIG. 6, the organic light emitting display 100 according to the first embodiment of the present invention includes red subpixels RSP and white subpixels WSP on a substrate 110. The driving thin film transistor D_TFT and the organic light emitting diode OLED connected to the driving thin film transistor D_TFT are located in the red subpixel RSP and the white subpixel WSP, respectively.

In more detail, the substrate 110 is made of glass, plastic, metal, or the like. The first buffer layer 112 is located on the substrate 110. The first buffer layer 112 protects a thin film transistor element such as a driving thin film transistor (D_TFT) formed in a subsequent process from an impurity such as an alkali ion or the like flowing out from the substrate 110. The first buffer layer 112 may be silicon oxide (SiOx), silicon nitride (SiNx), or multiple layers thereof.

The light blocking layer 114 is located on the first buffer layer 112. The light shielding layer 114 serves to prevent light incident from the bottom of the substrate 110 from reaching the semiconductor layer. The light shielding layer 114 may be made of a material that absorbs or blocks light, such as a black pigment, carbon black, chromium (Cr), or the like. The second buffer layer 116 is located on the light-shielding layer 114. The second buffer layer 116 serves to protect the thin film transistor elements formed in the subsequent process from impurities such as alkali ions or the like, which flow out from the light shielding layer 114. The second buffer layer 116 may be silicon oxide (SiOx), silicon nitride (SiNx), or multiple layers thereof.

The semiconductor layer 120 is located on the second buffer layer 116. The semiconductor layer 120 may be formed of a silicon semiconductor or an oxide semiconductor. The silicon semiconductor may include amorphous silicon or crystallized polycrystalline silicon. The semiconductor layer 120 is doped with impurities to include a source region and a drain region and includes a channel region therebetween.

A gate insulating film 125 is disposed on the semiconductor layer 120. The gate insulating film 125 may be a silicon oxide (SiOx), a silicon nitride (SiNx), or a multilayer thereof. The gate electrode 130 is positioned on the gate insulating film 125 at a position corresponding to a certain region of the semiconductor layer 120, that is, a channel region. The gate electrode 130 may be formed of one selected from the group consisting of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), and copper Any one of them or an alloy thereof. The gate electrode 130 may be formed of one selected from the group consisting of Mo, Al, Cr, Au, Ti, Ni, Ne, Or an alloy of any one selected from the above. For example, the gate electrode 130 may be a double layer of molybdenum / aluminum-neodymium or molybdenum / aluminum.

An interlayer insulating film 135 is located on the gate electrode 130. The interlayer insulating film 135 may be a silicon oxide film (SiOx), a silicon nitride film (SiNx), or a multilayer thereof. A part of the interlayer insulating layer 135 and the gate insulating layer 125 are etched so that a part of the semiconductor layer 120, that is, contact holes 137 and 138 exposing the source region and the drain region, is located. A source electrode 140 and a drain electrode 145 electrically connected to the semiconductor layer 120 are disposed through the interlayer insulating layer 135 and the contact holes 137 and 138 passing through the gate insulating layer 125. When the source electrode 140 and the drain electrode 145 are formed as a single layer, the source electrode 140 and the drain electrode 145 may be formed of Mo, Al, And may be made of any one selected from the group consisting of chrome (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd) and copper (Cu) When the source electrode 140 and the drain electrode 145 are multilayered, a triple layer of molybdenum / aluminum-neodymium, titanium / aluminum / titanium, molybdenum / aluminum / molybdenum or molybdenum / aluminum- neodymium / ≪ / RTI > Therefore, a driving thin film transistor (D_TFT) including the semiconductor layer 120, the gate electrode 130, the source electrode 140, and the drain electrode 145 is formed.

A passivation film (PAS) for protecting the lower thin film transistor is disposed on the entire surface of the substrate 110 including the driving thin film transistor (D_TFT). The passivation film PAS may be a silicon oxide film (SiOx), a silicon nitride film (SiNx), or a multilayer thereof. A red color filter R_CF is disposed on the passivation film PAS so as to be spaced apart from the driving thin film transistor D_TFT. The red color filter (R_CF) converts the white light emitted from the light emitting layer to red. On the other hand, the white subpixel WSP does not include the color filter since the light emitted from the light emitting layer is white.

An overcoat layer OC is placed on the passivation film PAS and the red color filter R_CF. The overcoat layer OC may be a flattening film for alleviating the step of the substructure, for example, the step of the red color filter R_CF, and may be a polyimide, a benzocyclobutene series resin, (acrylate) or the like. Preferably, the overcoat layer OC may be a photoacryl. The overcoat layer OC includes a via hole 155 for exposing the drain electrode 145 of the driving thin film transistor D_TFT.

A first electrode (ANO) is located on the overcoat layer (OC). The first electrode ANO may be an anode and may be formed of a transparent conductive material such as indium tin oxide (ITO), indium zinc oxide (IZO), or zinc oxide (ZnO). The first electrode ANO has a very large via hole 155 and is connected to the drain electrode 145 of the driving thin film transistor D_TFT. When the organic light emitting display 100 is a front emission type in which light is emitted in the second electrode (CAT) direction, the first electrode ANO may further include a reflective layer, and may have a two-layer structure of ITO / Reflective layer / ITO. On the other hand, when the OLED display 100 is a backlight type in which light is emitted toward the first electrode ANO, the first electrode ANO may be formed of a transparent conductive material only.

A bank layer BNK is disposed on a substrate 110 including the first electrode ANO. The bank layer BNK may be a pixel defining film which defines a pixel by exposing a part of the first electrode ANO. The bank layer BNK is made of an organic material such as polyimide, benzocyclobutene series resin, or acrylate. The bank layer BNK is provided with an opening 167 for exposing the first electrode ANO.

The light emitting layer (EML) is located on the first electrode (ANO) exposed by the opening (167) of the bank layer (BNK). The light emitting layer (EML) may include a hole injecting layer or a hole transporting layer between the light emitting layer (EML) and the first electrode (ANO), and may include an electron transporting layer And an electron injection layer. A second electrode (CAT) is located on a substrate (110) on which a light emitting layer (EML) is formed. The second electrode (CAT) may be made of magnesium (Mg), calcium (Ca), aluminum (Al), silver (Ag) or an alloy thereof having a low work function as a cathode electrode. When the OLED display 100 of the present invention is a front emission type in which light is emitted toward the second electrode CAT, the second electrode CAT is thin enough to transmit light. On the other hand, when the organic light emitting diode display 100 of the present invention is a backlight type in which light is emitted toward the first electrode ANO, the second electrode CAT has a thickness thick enough to reflect light. Accordingly, an organic light emitting diode (OLED) including a first electrode ANO, a light emitting layer (EML), and a second electrode (CAT) is formed.

The organic light emitting diode display 100 according to the first embodiment of the present invention includes one hole BUH formed in the second buffer layer 116. [

Referring to FIG. 6, one hole BUH is located in the second buffer layer 116 in the red subpixel RSP adjacent to the white subpixel WSP. The hole BUH formed in the second buffer layer 116 is disposed to overlap with the red color filter R_CF in order to reduce the level difference of the overcoat layer OC with the adjacent white subpixel WSP.

The function of the hole (BUH) is to reduce the height of the structures located at the top by the depth of the hole (BUH). 6, when the red color filter R_CF overlaps the hole BUH, the distance from the surface of the substrate 110 to the upper surface of the red color filter R_CF is reduced by the depth of the hole BUH . The thickness of the second buffer layer 116 may be about 10 to 1000 nm so that the thickness of the second buffer layer 116 from the surface of the substrate 110 to the red color filter R_CF) can be reduced.

Referring to FIG. 7, the OLED display 100 includes a red subpixel RSP, a white subpixel WSP, a green subpixel GSP, and a blue subpixel BSP. Each of the subpixels includes a light emitting portion (LEP) located below the circuit portion (CIP) and the circuit portion (CIP). The color filters R_CF, G_CF, and B_CF have a larger area than the light emitting portion LEP.

In the present invention, the holes BUH of the second buffer layer 116 are formed on a plane so as to surround the edges of the red color filter R_CF and the green color filter G_CF. That is, it is seen that one edge of the red color filter R_CF and the green color filter G_CF are included in the inside of the hole BUH when viewed in plan view. This is because the edge of the red color filter R_CF adjacent to the white subpixel WSP is formed in a region where a step is generated by the overcoat layer OC and the red color filter R_CF and the green color filter G_CF are exposed This is true. Therefore, the hole BUH of the second buffer layer 116 is positioned to surround the edges of the red color filter R_CF and the green color filter G_CF. The hole BUH of the second buffer layer 116 may be positioned to surround the edge of the red color filter R_CF and the green color filter G_CF adjacent to at least the white subpixel WSP. Therefore, the hole BUH of the second buffer layer 116 is formed with an area larger than that of the red color filter R_CF and the green color filter G_CF.

As described above, the present invention forms a hole BUH of the second buffer layer 116 overlapping each color filter of the red subpixel RSP and the green subpixel GSP adjacent to the white subpixel WSP . Therefore, the holes BUH of the second buffer layer 116 can reduce the distance from the surface of the substrate 110 to the upper surface of each color filter.

8, the reason for reducing the distance from the surface of the substrate 110 to the upper surface of the red color filter R_CF is that a color filter is added to adjacent white subpixels WSP This is because a step is formed in the overcoat layer OC formed on the red subpixel RSP and the white subpixel WSP. When a step is formed in the overcoat layer OC, the edge of the red color filter R_CF is exposed as shown in Fig. 8 (a). After the formation of the overcoat layer OC, the first electrode ANO is laminated and patterned. When the first electrode ANO is laminated on the exposed red color filter R_CF, The first electrode ANO is outwardly angled because the adhesive force of the filter is poor. The edge of the first electrode ANO is not covered with the bank layer BNK and the edge of the first electrode ANO is also exposed by the light emitting layer EML formed on the first electrode ANO, A short circuit occurs between the first electrode ANO and the second electrode CAT.

8B, a hole BUH is formed in the second buffer layer 116 so as to overlap with the red color filter R_CF. The hole BUH is formed from the surface of the substrate 110 to the red color filter R_CF The distance to the surface can be reduced. Accordingly, the step of the overcoat layer OC with respect to the white sub-pixel WSP adjacent to the red subpixel RSP is reduced so that the red color filter R_CF is not exposed. Therefore, the present invention can prevent a short circuit between the first electrode ANO and the second electrode CAT, and can prevent the defect of the dark spot of the subpixel.

≪ Embodiment 2 >

FIG. 9 is a cross-sectional view of an OLED display according to a second embodiment of the present invention, FIG. 10 is a cross-sectional view illustrating a part of an OLED display device, and FIG. 11 is a schematic view of a red, white, FIG. In the following description, the same reference numerals are assigned to the same components as those of the first embodiment, and a description thereof will be simplified.

Referring to FIG. 9, an OLED display 100 according to a second exemplary embodiment of the present invention includes red subpixels RSP and white subpixels WSP on a substrate 110. Referring to FIG. The driving thin film transistor D_TFT and the organic light emitting diode OLED connected to the driving thin film transistor D_TFT are located in the red subpixel RSP and the white subpixel WSP, respectively.

More specifically, the first buffer layer 112 is located on the substrate 110, and the light-shielding layer 114 is located on the first buffer layer 112. The second buffer layer 116 is located on the light shielding layer 114 and the semiconductor layer 120 is located on the second buffer layer 116. A gate insulating film 125 is located on the semiconductor layer 120 and a gate electrode 130 is located on the gate insulating film 125. The interlayer insulating film 135 is located on the gate electrode 130 and the contact holes 137 and 138 are located in some regions of the interlayer insulating film 135 and the gate insulating film 125. A source electrode 140 and a drain electrode 145 are located on the interlayer insulating film 135. Therefore, a driving thin film transistor (D_TFT) including the semiconductor layer 120, the gate electrode 130, the source electrode 140, and the drain electrode 145 is formed.

A passivation film (PAS) for protecting the lower thin film transistor is disposed on the entire surface of the substrate 110 including the driving thin film transistor (D_TFT). The red color filter R_CF is positioned on the passivation film PAS and the color filter is not positioned on the white subpixel WSP because the light emitted from the light emitting layer is white. The overcoat layer OC is positioned on the passivation film PAS and the red color filter R_CF and the overcoat layer OC includes a via hole 155 exposing the drain electrode 145 of the driving thin film transistor D_TFT . A first electrode ANO is disposed on the overcoat layer OC and a bank layer BNK including an opening 167 exposing the first electrode ANO on the substrate 110 including the first electrode ANO. ). The light emitting layer (EML) is located on the first electrode (ANO) exposed by the opening (167) of the bank layer (BNK). A second electrode (CAT) is located on a substrate (110) on which a light emitting layer (EML) is formed. Accordingly, an organic light emitting diode (OLED) including a first electrode ANO, a light emitting layer (EML), and a second electrode (CAT) is formed.

Referring to FIG. 10, the organic light emitting diode display 100 according to the second embodiment of the present invention includes one hole BUH formed in the second buffer layer 116 in each subpixel, And a buffer layer pattern (BPT) surrounded by the buffer layer pattern. The hole BUH formed in the second buffer layer 116 is disposed to overlap with the red color filter R_CF in order to reduce the level difference of the overcoat layer OC with the adjacent white subpixel WSP.

Referring to FIG. 11, the OLED display 100 includes a red subpixel RSP, a white subpixel WSP, a green subpixel GSP, and a blue subpixel BSP. Each of the subpixels includes a light emitting portion (LEP) located below the circuit portion (CIP) and the circuit portion (CIP). The color filters R_CF, G_CF, and B_CF have a larger area than the light emitting portion (LEP).

In the present invention, the holes BUH of the second buffer layer 116 are formed in a frame shape surrounding the edges of the red color filter R_CF and the green color filter G_CF on a plane. That is, one edge of the red color filter (R_CF) and the green color filter (G_CF) are superimposed on the inside of the hole (BUH) when viewed in plan view. Further, the buffer layer pattern BPT is surrounded by a hole BUH. That is, it is seen that the buffer layer pattern BPT is included in the red color filter R_CF and the green color filter G_CF when viewed in plan view.

The hole BUH of the second embodiment of the present invention is formed so as to overlap only the edge of the red color filter R_CF and the edge of the green color filter G_CF and the edge of the red color filter R_CF and the edge of the green color filter G_CF Are not overlapped with each other. The buffer layer pattern BPT is superimposed on other regions except the edges of the red color filter R_CF and the green color filter G_CF. That is, the buffer layer pattern BPT is separated from the edges of the red color filter R_CF and the green color filter G_CF.

The edge of the red color filter R_CF adjacent to the white subpixel WSP and the edge of the green color filter G_CF are separated by the step of the overcoat layer OC so that the red color filter R_CF and the green color filter G_CF It corresponds to the area which can be exposed. Therefore, in the second embodiment of the present invention, the holes BUH of the buffer layer 116 are not formed largely, but may be formed so as to overlap only the edges of the red color filter R_CF and the edges of the green color filter G_CF.

As described above, the OLED display 100 according to the second embodiment of the present invention includes a white subpixel WSP, a white subpixel WSP, a red subpixel RSP and a green subpixel GSP adjacent to each other, (OC) of the red color filter (R_CF) and the green color filter (G_CF) are not exposed. Therefore, the present invention can prevent a short circuit between the first electrode ANO and the second electrode CAT, and can prevent the defect of the dark spot of the subpixel.

≪ Third Embodiment >

FIG. 12 is a cross-sectional view of an OLED display according to a third embodiment of the present invention, FIG. 13 is a cross-sectional view illustrating a part of an organic light emitting display device, and FIG. 14 is a schematic diagram of a red, white, FIG. In the following, the same reference numerals are assigned to the same components as those of the first and second embodiments described above, and a description thereof will be simplified.

Referring to FIG. 12, an OLED display 100 according to a third exemplary embodiment of the present invention includes red subpixels RSP and white subpixels WSP on a substrate 110. The driving thin film transistor D_TFT and the organic light emitting diode OLED connected to the driving thin film transistor D_TFT are located in the red subpixel RSP and the white subpixel WSP, respectively.

More specifically, the first buffer layer 112 is located on the substrate 110, and the light-shielding layer 114 is located on the first buffer layer 112. The second buffer layer 116 is located on the light shielding layer 114 and the semiconductor layer 120 is located on the second buffer layer 116. A gate insulating film 125 is located on the semiconductor layer 120 and a gate electrode 130 is located on the gate insulating film 125. The interlayer insulating film 135 is located on the gate electrode 130 and the contact holes 137 and 138 are located in some regions of the interlayer insulating film 135 and the gate insulating film 125. A source electrode 140 and a drain electrode 145 are located on the interlayer insulating film 135. Therefore, a driving thin film transistor (D_TFT) including the semiconductor layer 120, the gate electrode 130, the source electrode 140, and the drain electrode 145 is formed.

A passivation film (PAS) for protecting the lower thin film transistor is disposed on the entire surface of the substrate 110 including the driving thin film transistor (D_TFT). The red color filter R_CF is positioned on the passivation film PAS and the color filter is not positioned on the white subpixel WSP because the light emitted from the light emitting layer is white. The overcoat layer OC is positioned on the passivation film PAS and the red color filter R_CF and the overcoat layer OC includes a via hole 155 exposing the drain electrode 145 of the driving thin film transistor D_TFT . A first electrode ANO is disposed on the overcoat layer OC and a bank layer BNK including an opening 167 exposing the first electrode ANO on the substrate 110 including the first electrode ANO. ). The light emitting layer (EML) is located on the first electrode (ANO) exposed by the opening (167) of the bank layer (BNK). A second electrode (CAT) is located on a substrate (110) on which a light emitting layer (EML) is formed. Accordingly, an organic light emitting diode (OLED) including a first electrode ANO, a light emitting layer (EML), and a second electrode (CAT) is formed.

Referring to FIG. 13, the organic light emitting diode display 100 according to the third embodiment of the present invention includes one hole BUH formed in the second buffer layer 116 in each subpixel, And a plurality of buffer layer patterns (BPT) surrounded by the plurality of buffer layer patterns. The hole BUH formed in the second buffer layer 116 is disposed to overlap with the red color filter R_CF in order to reduce the level difference of the overcoat layer OC with the adjacent white subpixel WSP.

Referring to FIG. 14, the OLED display 100 includes a red subpixel RSP, a white subpixel WSP, a green subpixel GSP, and a blue subpixel BSP. Each of the subpixels includes a light emitting portion (LEP) located below the circuit portion (CIP) and the circuit portion (CIP). The color filters R_CF, G_CF, and B_CF have a larger area than the light emitting portion (LEP).

In the present invention, the holes BUH of the second buffer layer 116 are formed on a plane so as to surround the edges of the red color filter R_CF and the green color filter G_CF. That is, one edge of the red color filter (R_CF) and the green color filter (G_CF) are superimposed on the inside of the hole (BUH) when viewed in plan view. Further, the plurality of buffer layer patterns BPT are surrounded by the holes BUH. That is, it is seen that a plurality of buffer layer patterns BPT are included in the red color filter R_CF and the green color filter G_CF when viewed on a plane.

The hole BUH of the second embodiment of the present invention is formed so as to overlap the edge of the red color filter R_CF and the edge of the green color filter G_CF and the edge of the red color filter R_CF and the edge of the green color filter G_CF (LEP) of the remaining regions except for the light emitting portion (LEP). In addition, a plurality of buffer layer patterns BPT are superimposed on the light emitting portion LEP among the regions other than the edges of the red color filter R_CF and the green color filter G_CF.

That is, the hole BUH and the plurality of buffer layer patterns BPT overlap each other in the light emitting portion LEP of the red subpixel RSP and the light emitting portion LEP of the green subpixel GSP. A difference in luminance may occur between the light passing through the hole BUH and the light passing through the buffer layer pattern BPT in the path of light emitted from the light emitting layer (EML). In the third embodiment of the present invention, holes (BUH) and buffer layer patterns (BPT) are alternately arranged in a direction perpendicular to the longitudinal direction of the red subpixel (RSP). The buffer layer patterns (BPT) and the alternating holes (BUH) act like a slit, so that a difference in light luminance in the red subpixel RSP can be prevented.

As described above, the OLED display 100 according to the third embodiment of the present invention includes the white subpixel WSP, the white subpixel WSP, the red subpixel RSP and the green subpixel GSP adjacent to each other, (OC) of the red color filter (R_CF) and the green color filter (G_CF) are not exposed. Therefore, the present invention can prevent a short circuit between the first electrode ANO and the second electrode CAT, and can prevent the defect of the dark spot of the subpixel.

In the embodiments of the present invention described above, formation of a hole (BUH) in the second buffer layer 116 has been disclosed. It is preferable that the first buffer layer 112 located under the second buffer layer 116 is not provided with a hole BUH. The first buffer layer 112 is a functional layer for preventing impurities from penetrating from the substrate 110, and it is difficult for the holes BUH to be formed in the first buffer layer 112. The second buffer layer 116 is formed to insulate the light shielding layer 114 formed on the first buffer layer 112. Since the light shielding layer 114 is not located in a region overlapping the color filter, ). Therefore, it is preferable that the hole (BUH) is formed in the second buffer layer 116 according to the present invention.

In addition, in the embodiments of the present invention, the hole (BUH) of the second buffer layer 116 is formed in the red subpixel RSP and the green subpixel GSP adjacent to the white subpixel WSP, And the hole BUH of the second buffer layer 116 may be formed in the blue subpixel BSP not adjacent to the white subpixel WSP.

In the third embodiment of the present invention, three buffer layer patterns BPT are formed in each of the red subpixel RSP and the green subpixel GSP. However, the present invention is not limited to this, Or four or more buffer layer patterns (BPT) may be formed.

Also, in the embodiments of the present invention, it has been described by way of example that one hole BUH successively connected to the red subpixel RSP and the green subpixel GSP is formed. Alternatively, a plurality of discontinuous holes may be formed have.

While the present invention has been described in connection with what is presently considered to be practical exemplary embodiments thereof, it is to be understood that the invention is not limited to the disclosed embodiments, but, on the contrary, It will be understood that the invention may be practiced. It is therefore to be understood that the embodiments described above are to be considered in all respects only as illustrative and not restrictive. In addition, the scope of the present invention is indicated by the appended claims rather than the detailed description. Also, all changes or modifications derived from the meaning and scope of the claims and their equivalents should be construed as being included within the scope of the present invention.

100: display device 110: substrate
112: first buffer layer 114: shielding layer
116: second buffer layer 147: passivation film
BUH: Hall D_TFT: Driving Thin Film Transistor
R_CF: Red color filter OC: Overcoat layer
ANO: first electrode BNK: bank layer
EML: light emitting layer CAT: second electrode
OLED: Organic Light Emitting Diode

Claims (11)

Board;
A buffer layer located on the substrate;
A thin film transistor located on the buffer layer;
A passivation film located on the thin film transistor;
A color filter disposed on the passivation film and spaced apart from the thin film transistor;
An overcoat layer disposed on the color filter; And
And an organic light emitting diode (OLED) disposed on the overcoat layer and connected to the thin film transistor,
Wherein the buffer layer includes at least one hole and the hole overlaps with the color filter.
The method according to claim 1,
And the holes of the buffer layer surround the color filter in a plane.
3. The method of claim 2,
And the area of the hole of the buffer layer is larger than the area of the color filter.
The method according to claim 1,
And the holes of the buffer layer overlap with at least one edge of the color filter.
The method according to claim 1,
Wherein the at least one hole includes at least one buffer layer pattern therein.
6. The method of claim 5,
The organic light emitting diode includes a light emitting portion for blasting light,
Wherein the at least one buffer layer pattern overlaps the light emitting portion.
The method according to claim 6,
Wherein the at least one buffer layer pattern is spaced apart from an edge of the color filter.
The method according to claim 1,
Wherein the buffer layer has a thickness of 10 to 1000 nm.
The method according to claim 1,
Wherein the organic light emitting diode is a backlight type.
A substrate comprising at least a white sub-pixel and a colored sub-pixel in contact with the white sub-pixel;
A buffer layer located on the entire surface of the substrate;
A thin film transistor located in each of the white and colored subpixels;
A passivation film located on the thin film transistor;
A color filter located on the passivation film in the colored subpixel and spaced apart from the thin film transistor;
An overcoat layer covering the color filter and positioned over the entire surface of the substrate; And
And an organic light emitting diode (OLED) disposed on the overcoat layer and located in the white and colored subpixels, respectively,
Wherein in the colored subpixel, the buffer layer includes at least one hole, and the hole overlaps with the color filter.
11. The method of claim 10,
Wherein the white subpixel does not include holes of the color filter and the buffer layer.

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