KR102646400B1 - Display Device - Google Patents

Abstract

The present invention relates to a display device, and more specifically, to a display device that can prevent light leakage. A display device according to an embodiment of the present invention includes a first subpixel located on a substrate, wherein the first subpixel includes a first gate line located on the substrate and a first subpixel parallel to the first gate line. 2 gate lines, a first data line crossing the first gate line and the second gate line, a light emitting area arranged in parallel with the first data line and including an organic light emitting diode, and arranged in parallel with the light emitting area However, it includes a capacitor area disposed adjacent to the first data line with the light emitting area in between.

Description

Display Device

The present invention relates to a display device, and more specifically, to a display device that can prevent light leakage.

As the information society develops, the demand for display devices for displaying images is increasing in various forms. The display device field has been rapidly changing toward thin, light, large-area flat panel displays (FPDs) replacing bulky cathode ray tubes (CRTs). Flat panel displays include Liquid Crystal Display Device (LCD), Plasma Display Panel (PDP), Organic Light Emitting Display Device (OLED), and Electrophoretic Display Device. : ED), etc.

Among these, organic light emitting display devices are self-emitting devices that emit light on their own and have the advantages of fast response speed, high luminous efficiency, brightness, and viewing angle. In particular, organic light emitting display devices can not only be formed on flexible substrates, but can also be driven at lower voltages and consume relatively less power than plasma display panels or inorganic electroluminescence (EL) displays. It has the advantage of excellent color.

In an organic light emitting display device, three subpixels of red, green, and blue make up one unit pixel, or four subpixels plus white make up one unit pixel. Organic light emitting display devices are being designed to improve display quality by increasing the aperture ratio of each subpixel. At this time, as the light emitting area of each subpixel is placed adjacent to each other, there is a problem in that light leakage occurs in which light from adjacent subpixels is emitted through other subpixels.

The present invention provides a display device that can prevent light leakage.

To achieve the above object, a display device according to an embodiment of the present invention includes a first subpixel located on a substrate, wherein the first subpixel includes a first gate line and a first gate line located on the substrate. A second gate line parallel to the first gate line, a first data line crossing the first gate line and the second gate line, a light emitting area disposed in parallel with the first data line and including an organic light emitting diode, and a capacitor area arranged in parallel with the light-emitting area and adjacent to the first data line with the light-emitting area in between.

It includes a second subpixel adjacent to the first subpixel, wherein the second subpixel includes the first gate line, a second data line that intersects the second gate line, and is arranged in parallel with the second data line. It includes a light-emitting area including an organic light-emitting diode, and a capacitor area arranged in parallel with the light-emitting area and between the light-emitting area and the second data line.

A capacitor area of the first subpixel is disposed between the light-emitting area of the first subpixel and the light-emitting area of the second subpixel.

The first data line is disposed between the capacitor area of the first subpixel and the light emitting area of the second subpixel.

It is adjacent to the capacitor area of the first subpixel with the light emitting area of the first subpixel in between, and includes a first power line shared by the first subpixel and the second subpixel, respectively.

It is adjacent to the capacitor area of the second subpixel with the second data line in between, and includes a sensing line shared by the first subpixel and the second subpixel, respectively.

It includes a third subpixel and a fourth subpixel that are symmetrical to the first subpixel and the second subpixel based on the sensing line, and the sensing line is shared by the third subpixel and the fourth subpixel. .

The third subpixel includes a third data line, a light emitting area, and a capacitor area, where the third data line is adjacent to the sensing line and the light emitting area is adjacent to the sensing line with the capacitor area interposed therebetween.

The fourth subpixel includes a fourth data line, a light-emitting area, and a capacitor area, and the fourth data line is adjacent to the light-emitting area with the capacitor area interposed therebetween.

A capacitor area of the fourth subpixel is disposed between the light-emitting area of the third subpixel and the light-emitting area of the fourth subpixel.

It includes a third subpixel and a fourth subpixel neighboring the first subpixel and the second subpixel with the sensing line interposed therebetween, and the sensing line is shared by the third subpixel and the fourth subpixel. do.

The third subpixel includes a third data line, a light-emitting area, and a capacitor area, and the third data line and the light-emitting area are adjacent to each other with the capacitor area in between.

The fourth subpixel includes a fourth data line, a light-emitting area, and a capacitor area, and the fourth data line and the light-emitting area are adjacent to each other with the capacitor area in between.

The third data line and the fourth data line are disposed adjacent to each other, and a capacitor area of the third subpixel and the fourth subpixel are positioned between the light-emitting area of the third subpixel and the light-emitting area of the fourth subpixel. The capacitor area of the pixel is placed.

It is adjacent to the capacitor area of the fourth subpixel with the light emitting area of the fourth subpixel in between, and includes a second power line shared by the third subpixel and the fourth subpixel, respectively.

Display devices according to embodiments of the present invention arrange data lines and light emitting areas adjacent to each other with the capacitor areas of subpixels in between, so that capacitor areas are placed between the light emitting areas of adjacent subpixels. Accordingly, light leakage between adjacent subpixels can be prevented.

In addition, the display device according to the embodiments of the present invention has the advantage of easy processing by arranging the capacitor area between the light emitting areas of each subpixel, so that the color filter can have a margin for further application to the capacitor area. .

1 is a schematic block diagram of an organic light emitting display device.
2 is a schematic circuit diagram of a subpixel.
3 is a detailed circuit diagram of a subpixel.
Figure 4 is a cross-sectional view of the display panel.
Figure 5 is a diagram schematically showing the planar layout of subpixels according to the present invention.
Figure 6 is a diagram showing a planar layout of a subpixel of the present invention.
Figure 7 is a cross-sectional view taken along line A-A' of Figure 6.
Figure 8 is a diagram briefly showing the planar layout of subpixels according to an embodiment of the present invention.
Figure 9 is a detailed plan layout of subpixels according to an embodiment of the present invention.
Figure 10 is a cross-sectional view taken along line B-B' of Figure 9.
Figure 11 is a cross-sectional view taken along line C-C' of Figure 9.
Figure 12 is a diagram briefly showing the planar layout of subpixels according to another embodiment of the present invention.
Figure 13 is a detailed plan layout of subpixels according to another embodiment of the present invention.

Hereinafter, preferred embodiments of the present invention will be described with reference to the attached drawings. Like reference numerals refer to substantially the same elements throughout the specification. In the following description, if it is determined that a detailed description of a known technology or configuration related to the present invention may unnecessarily obscure the gist of the present invention, the detailed description will be omitted. Additionally, the component names used in the following description may have been selected in consideration of ease of specification preparation, and may be different from the component names of the actual product.

The display device according to the present invention is a display device in which display elements are formed on a glass substrate or a flexible substrate. Examples of display devices include organic light emitting display devices, liquid crystal display devices, and electrophoretic display devices. However, in the present invention, the organic light emitting display device is described as an example. The organic light emitting display device includes an organic film layer made of organic material between a first electrode, which is an anode, and a second electrode, which is a cathode. Therefore, the holes supplied from the first electrode and the electrons supplied from the second electrode combine within the organic layer to form excitons, which are hole-electron pairs, and emit light by the energy generated when the excitons return to the ground state. It is a self-luminous display device.

FIG. 1 is a schematic block diagram of an organic light emitting display device, FIG. 2 is a schematic circuit diagram of a subpixel, FIG. 3 is a detailed circuit diagram of a subpixel, and FIG. 4 is a cross-sectional view of a display panel.

As shown in FIG. 1, the organic light emitting display device includes an image processing unit 110, a timing control unit 120, a data driver 130, a scan driver 140, and a display panel 150.

The image processing unit 110 outputs a data enable signal (DE) in addition to a data signal (DATA) supplied from the outside. In addition to the data enable signal DE, the image processor 110 may output one or more of a vertical synchronization signal, a horizontal synchronization signal, and a clock signal, but these signals are omitted for convenience of explanation.

The timing control unit 120 receives a data enable signal (DE) or a driving signal including a vertical synchronization signal, a horizontal synchronization signal, and a clock signal, as well as a data signal (DATA) from the image processing unit 110. The timing control unit 120 provides a gate timing control signal (GDC) for controlling the operation timing of the scan driver 140 and a data timing control signal (DDC) for controlling the operation timing of the data driver 130 based on the driving signal. outputs.

The data driver 130 samples and latches the data signal DATA supplied from the timing control unit 120 in response to the data timing control signal DDC supplied from the timing control unit 120, converts it to a gamma reference voltage, and outputs it. . The data driver 130 outputs the data signal DATA through the data lines DL1 to DLn. The data driver 130 may be formed in the form of an integrated circuit (IC).

The scan driver 140 outputs a scan signal in response to the gate timing control signal (GDC) supplied from the timing control unit 120. The scan driver 140 outputs a scan signal through the gate lines GL1 to GLm. The scan driver 140 is formed in the form of an integrated circuit (IC) or is formed in the display panel 150 using a gate in panel method.

The display panel 150 displays images in response to data signals (DATA) and scan signals supplied from the data driver 130 and the scan driver 140. The display panel 150 includes subpixels (SP) that operate to display images.

The subpixels SP include a red subpixel, a green subpixel, and a blue subpixel, or include a white subpixel, a red subpixel, a green subpixel, and a blue subpixel. The subpixels SP may have one or more different light emission areas depending on light emission characteristics.

As shown in FIG. 2, one subpixel includes a switching transistor (SW), a driving transistor (DR), a capacitor (Cst), a compensation circuit (CC), and an organic light emitting diode (OLED).

The switching transistor SW performs a switching operation in response to the scan signal supplied through the first gate line GL1 so that the data signal supplied through the first data line DL1 is stored as a data voltage in the capacitor Cst. The driving transistor (DR) operates so that a driving current flows between the power line (EVDD) (high potential voltage) and the cathode power line (EVSS) (low potential voltage) according to the data voltage stored in the capacitor (Cst). An organic light-emitting diode (OLED) operates to emit light according to a driving current formed by a driving transistor (DR).

The compensation circuit (CC) is a circuit added to the subpixel to compensate for the threshold voltage of the driving transistor (DR). The compensation circuit (CC) consists of one or more transistors. The composition of the compensation circuit (CC) varies greatly depending on the external compensation method, and an example is as follows.

As shown in FIG. 3, the compensation circuit (CC) includes a sensing transistor (ST) and a sensing line (VREF) (or reference line). The sensing transistor (ST) is connected between the source electrode of the driving transistor (DR) and the anode electrode of the organic light-emitting diode (OLED) (hereinafter referred to as the sensing node). The sensing transistor (ST) supplies the initialization voltage (or sensing voltage) transmitted through the sensing line (VREF) to the sensing node of the driving transistor (DR) or the voltage of the sensing node of the driving transistor (DR) or the sensing line (VREF). Or, it operates to sense current.

The switching transistor SW has a drain electrode connected to the first data line DL1 and a source electrode connected to the gate electrode of the driving transistor DR. The driving transistor (DR) has its drain electrode connected to the power line (EVDD) and its source electrode connected to the anode electrode of the organic light-emitting diode (OLED). The capacitor (Cst) has its upper electrode connected to the gate electrode of the driving transistor (DR) and its lower electrode connected to the anode electrode of the organic light-emitting diode (OLED). The organic light emitting diode (OLED) has an anode connected to the source electrode of the driving transistor (DR) and a cathode connected to the second power line (EVSS). The sensing transistor (ST) has a drain electrode connected to the sensing line (VREF), and a source electrode connected to the anode electrode of the organic light-emitting diode (OLED), which is a sensing node, and the source electrode of the driving transistor (DR).

The operating time of the sensing transistor (ST) may be similar/same or different from that of the switching transistor (SW) depending on the external compensation algorithm (or configuration of the compensation circuit). For example, the switching transistor SW may have its gate electrode connected to the first gate line GL1, and the sensing transistor ST may have its gate electrode connected to the second gate line GL2. In this case, a scan signal (Scan) is transmitted to the first gate line (GL1) and a sensing signal (Sense) is transmitted to the second gate line (GL2). As another example, the first gate line GL1 connected to the gate electrode of the switching transistor SW and the second gate line GL2 connected to the gate electrode of the sensing transistor ST may be connected to share a common feature.

The sensing line (VREF) may be connected to the data driver. In this case, the data driver can sense the sensing node of the subpixel in real time, during the non-display period of the image, or during the N frame period (N is an integer greater than 1) and generate a sensing result. Meanwhile, the switching transistor (SW) and the sensing transistor (ST) may be turned on at the same time. In this case, the sensing operation through the sensing line (VREF) and the data output operation of outputting the data signal are separated (differentiated) from each other based on the time division method of the data driver.

In addition, the compensation target according to the sensing result may be a digital data signal, an analog data signal, or gamma. And the compensation circuit that generates a compensation signal (or compensation voltage) based on the sensing result may be implemented inside the data driver, inside the timing control unit, or as a separate circuit.

The light blocking layer (LS) may be disposed only under the channel region of the driving transistor (DR), or may be disposed not only under the channel region of the driving transistor (DR) but also under the channel regions of the switching transistor (SW) and the sensing transistor (ST). The light blocking layer (LS) can be used simply to block external light, or it can be used to connect with other electrodes or lines, and can be used as an electrode to form a capacitor, etc. Therefore, the light blocking layer (LS) is selected as a multi-layer (multi-layer of different metals) metal layer to have light-blocking properties.

In addition, in Figure 3, a subpixel of a 3T (Transistor) 1C (Capacitor) structure including a switching transistor (SW), a driving transistor (DR), a capacitor (Cst), an organic light emitting diode (OLED), and a sensing transistor (ST) is shown. Although explained as an example, if a compensation circuit (CC) is added, it may be configured as 3T2C, 4T2C, 5T1C, 6T2C, etc.

As shown in FIG. 4, subpixels are formed on the display area AA of the substrate (or thin film transistor substrate) SUB1 based on the circuit described in FIG. 3. Subpixels formed on the display area AA are sealed by a protective film (or protective substrate) SUB2. Other unexplained NAs refer to non-display areas. The substrate SUB1 may be selected from glass or a flexible material.

Subpixels are arranged horizontally or vertically in the order of red (R), white (W), blue (B), and green (G) on the display area (AA). And the subpixels of red (R), white (W), blue (B), and green (G) become one pixel (P). However, the arrangement order of subpixels may vary depending on the light emitting material, light emitting area, composition (or structure) of the compensation circuit, etc. Additionally, the subpixels may be red (R), blue (B), and green (G) into one pixel (P).

Figure 5 is a diagram schematically showing the planar layout of subpixels according to the present invention.

As shown in FIGS. 4 and 5, on the display area (AA) of the substrate (SUB1), first to fourth subpixels (SPn1) to fourth subpixels (SPn4) having an emission area (EMA) and a circuit area (DRA) This is formed. An organic light-emitting diode (light-emitting device) is formed in the light-emitting area (EMA), and a circuit including switching, sensing, and driving transistors that drive the organic light-emitting diode is formed in the circuit area (DRA). The first subpixel (SPn1) to the fourth subpixel (SPn4) cause the organic light emitting diode located in the light emitting area (EMA) to emit light in response to the operation of the switching and driving transistor located in the circuit area (DRA). do. “WA” located between the first subpixel (SPn1) to the fourth subpixel (SPn4) is a wiring area, including the power line (EVDD), the sensing line (VREF), and the first to fourth data lines (DL1 to DL1). DL4) is deployed. The first and second gate lines GL1 and GL2 are arranged across the first to fourth subpixels SPn1 to SPn4.

Wires such as the power line (EVDD), the sensing line (VREF), and the first to fourth data lines (DL1 to DL4), as well as the electrodes that make up the thin film transistor, are located in different layers, but are connected through contact holes (via holes). They are electrically connected by contact. The sensing line (VREF) is connected to each sensing transistor (not shown) of the first to fourth subpixels (SPn1 to SPn4) through the sensing connection line (VREFC). The power line (EVDD) is connected to each driving transistor (not shown) of the first to fourth subpixels (SPn1 to SPn4) through the power connection line (EVDDC). The first and second gate lines GL1 and GL2 are connected to each sensing and switching transistor (not shown) of the first to fourth subpixels SPn1 to SPn4.

FIG. 6 is a diagram showing the plan layout of a subpixel of the present invention, and FIG. 7 is a cross-sectional view taken along line A-A' of FIG. 6.

Referring to FIG. 6, in the organic light emitting display device of the present invention, the first and second gate lines (GL1, GL2) and the first to fourth data lines (DL1 to DL4) intersect to form first to fourth subpixels ( SPn1~SPn4) are defined. Specifically, the first to fourth subpixels (SPn1 to SPn4) respectively connected to the first to fourth data lines (DL1 to DL4) are commonly connected to the sensing line (VREF). The sensing line VREF is directly connected to the second and third subpixels SPn2 and SPn3, and is connected to the first and fourth subpixels SPn1 and SPn4 through the sensing connection line VREFC. Power lines (EVDD) are disposed at both edges of the first to fourth subpixels (SPn1 to SPn4), and the first and fourth subpixels (SPn1, SPn4) adjacent to the power line (EVDD) are directly connected to each other. The second and third subpixels (SPn2, SPn3) are connected through a power connection line (EVDDC).

The first electrode (ANO) of an organic light emitting diode (OLED) is disposed in the light emitting area (EMA) of each subpixel, and the driving transistor (DR), capacitor (Cst), and sensing transistor (ST) are located in the circuit area (DRA). and a switching transistor (SW) is disposed. For example, the sensing transistor ST is composed of a gate electrode 240, a drain electrode 250D, a source electrode 250S, and a semiconductor layer 220. The sensing line (VREF) is connected to each sensing transistor (ST) of the first to fourth subpixels (SPn1 to SPn4) through the sensing connection line (VREFC). The power line EVDD is connected to each driving transistor DR of the first to fourth subpixels SPn1 to SPn4 through the power connection line EVDDC. The first and second gate lines GL1 and GL2 are connected to each of the sensing and switching transistors ST and SW of the first to fourth subpixels SPn1 to SPn4.

Refer to the cross section of the boundary between the first and second subpixels SPn1 and SPn2 shown in FIG. 7. The first subpixel SPn1 may be a red subpixel and the second subpixel SPn2 may be a white subpixel.

A first buffer layer (BUF1), a second buffer layer (BUF2), a gate insulating layer (GI), and an interlayer insulating layer (ILD) are sequentially disposed on the substrate SUB, and the first data line DL1 and the second data line are formed thereon. Line DL2 is placed. A passivation film (PAS) is disposed on the first and second data lines DL1 and DL2, and a red color filter (CF) is disposed in the first subpixel (SPn1) area. An overcoat layer (OC) is disposed on the red color filter (CF), and a first electrode (ANO) is disposed on the overcoat layer (OC) in the first and second subpixels (SPn1 and SPn2), respectively. A bank layer (BNK) defining the light emitting area of each subpixel is disposed on the first electrode (ANO).

The first subpixel SPn1 is equipped with a red color filter (CF) and emits red light through the red color filter (CF). The second subpixel SPn2 does not have a color filter and emits white light as is. If the red color filter (CF) of the first subpixel (SPn1) partially invades the area of the second subpixel (SPn2), when the second subpixel (SPn2) is driven, white light invades the red color filter ( CF) is partially transmitted and becomes reddish. Therefore, display quality deteriorates due to light leakage between adjacent subpixels.

In the following, a display device for preventing light leakage between subpixels described above is disclosed.

<Example>

FIG. 8 is a diagram briefly showing the planar layout of subpixels according to an embodiment of the present invention, FIG. 9 is a diagram showing in detail the planar layout of subpixels according to an embodiment of the present invention, and FIG. 10 is a diagram of FIG. 9 It is a cross-sectional view taken along the cutting line B-B', and FIG. 11 is a cross-sectional view taken along the cutting line C-C' of FIG. 9.

Referring to FIG. 8 , first to fourth subpixels SPn1 to SPn4 having emission areas E1 to E4 and capacitor areas C1 to C4 are disposed on the substrate SUB1. Organic light-emitting diodes (light-emitting devices) are formed in the light-emitting areas (E1 to E4), and capacitors among the circuits that drive the organic light-emitting diodes are placed in the capacitor areas (C1 to C4). In addition to the light emitting region (E1 to E4) and capacitor region (C1 to C4), switching, sensing and driving transistors are formed among the circuits that drive the organic light emitting diode. The organic light emitting diodes of the first subpixels (SPn1) to the fourth subpixels (SPn4) located in the light emitting areas (E1 to E4) emit light in response to operations such as switching and driving transistors. First and second power lines (EVDD1, EVDD2), sensing lines (VREF), and first to fourth data lines (DL1 to DL4) are disposed in the first subpixels (SPn1) to fourth subpixels (SPn4). do. The first gate line GL1 and the second gate line GL2 are disposed across the first to fourth subpixels SPn1 to SPn4, and the first to fourth subpixels SPn1 to SPn4 ( They are arranged adjacent to each other with the light emitting areas (E1 to E4) of SPn4) in between.

Wires such as the first and second power lines (EVDD1 to EVDD2), the sensing line (VREF), and the first to fourth data lines (DL1 to DL4), as well as the electrodes that make up the thin film transistor, are located in different layers. They are electrically connected by contact through a contact hole (not shown). The sensing line (VREF) is connected to each sensing transistor (not shown) of the first to fourth subpixels (SPn1 to SPn4). The first power line EVDD1 is connected to each driving transistor (not shown) of the first and second subpixels SPn1 and SPn2. The second power line EVDD2 is connected to each driving transistor (not shown) of the third and fourth subpixels SPn3 and SPn4. The first gate line GL1 is connected to the switching transistor (not shown) of the first to fourth subpixels SPn1 to SPn4, and the second gate line GL2 is connected to the first to fourth subpixels SPn1 to SPn4. ) is connected to the sensing transistor (not shown).

Each of the subpixels (SPn1 to SPn4) of the present invention has an emission area (E1 to E4) and a capacitor area (C1 to C4) arranged in parallel with the first data line (DL1). Specifically, the capacitor area C1 of the first subpixel SPn1 is arranged in parallel with the light emitting area E1 and between the light emitting area E1 and the first data line DL1.

The capacitor area C2 of the second subpixel SPn2 is arranged in parallel with the emission area E2 and adjacent to the first data line DL1 with the emission area E2 in between. The second data line DL2 is disposed adjacent to the emission area E2 of the second subpixel SPn2 with the capacitor area C2 of the second subpixel SPn2 interposed therebetween. The capacitor area C1 of the first subpixel SPn1 is disposed between the emission area E1 of the first subpixel SPn1 and the emission area E2 of the second subpixel SPn2. The first data line DL1 is disposed between the capacitor area C1 of the first subpixel SPn1 and the emission area E2 of the second subpixel SPn2.

The first power line EVDD1 is disposed adjacent to the capacitor area C1 of the first subpixel SPn1 with the light emitting area E1 of the first subpixel SPn1 interposed therebetween. The first power line EVDD1 is shared by the first subpixel SPn1 and the second subpixel SPn2, respectively. The sensing line (VREF) is disposed adjacent to the capacitor region (C2) of the second subpixel (SPn2) with the second data line (DL2) interposed therebetween. The sensing line (VREF) is shared by the first subpixel (SPn1) and the second subpixel (SPn2), respectively.

It includes a third subpixel (SPn3) and a fourth subpixel (SPn4) that are symmetrical to the first subpixel (SPn1) and the second subpixel (SPn2) with respect to the sensing line (VREF). The third subpixel SPn3 includes a third data line DL3, an emission area E3, and a capacitor area C3. The third data line DL3 is placed adjacent to the sensing line VREF, and the light emitting area E3 is placed adjacent to the sensing line VREF with the capacitor area C3 in between. The fourth subpixel SPn4 includes a fourth data line DL4, an emission area E4, and a capacitor area C4. The fourth data line DL4 is disposed adjacent to the light emitting area E4 with the capacitor area C4 in between. The capacitor area C4 of the fourth subpixel SPn4 is disposed between the emission area E3 of the third subpixel SPn3 and the emission area E4 of the fourth subpixel SPn4.

The second power line EVDD2 is disposed adjacent to the capacitor area C4 of the fourth subpixel SPn4 with the light emitting area E4 of the fourth subpixel SPn4 interposed therebetween. The second power line EVDD2 is shared by the third subpixel SPn3 and the fourth subpixel SPn4, respectively.

The structure of the first subpixel SPn1 will be representatively described with reference to FIG. 9 along with FIG. 8 . The first subpixel SPn1 is defined by the intersection of the first and second gate lines GL1 and GL2 and the first data line DL1. The first subpixel (SPn1) includes a driving transistor (DR), a sensing transistor (ST), a switching transistor (SW), a capacitor (Cst), and an organic light emitting diode (OLED).

The first electrode (ANO) of the organic light emitting diode (OLED) is disposed in the light emitting area (E1), and the capacitor (Cst) is disposed in the capacitor area (C1). A driving transistor (DR), a sensing transistor (ST), and a switching transistor (SW) are disposed outside the light emitting area (E1) and the capacitor area (C1). For example, the switching transistor SW is composed of a first gate line GL1, a drain electrode 250D, a source electrode 250S, and a semiconductor layer 220. Additionally, the sensing transistor ST is composed of a source electrode 240S connected to a sensing connection line VREFC extending from the sensing line VREF, a second gate line GL2, and a semiconductor layer 210. The driving transistor DR includes a semiconductor layer 230 serving as a drain electrode and a semiconductor layer, a gate electrode 260, and a source electrode 270S connected to a power connection line (EVDDC) extending from the first power line (EVDD). It consists of The capacitor Cst is composed of a capacitor lower electrode (LCst), a capacitor middle electrode (MCst), and a first electrode (ANO). The first electrode (ANO) is connected to the semiconductor layer 230, which acts as a drain electrode of the driving transistor (DR), through a via hole (VIA).

Looking at the cross-sectional structure of the above-described first subpixel SPn1 with reference to FIG. 10, in the display device according to an embodiment of the present invention, the light blocking layer LS is located on the substrate SUB1. The light blocking layer (LS) serves to prevent photocurrent from occurring in the thin film transistor by blocking external light from entering. A buffer layer (BUF) is located on the light blocking layer (LS). The buffer layer (BUF) serves to protect the thin film transistor formed in the subsequent process from impurities such as alkali ions leaking from the light blocking layer (LS). The buffer layer (BUF) may be silicon oxide (SiOx), silicon nitride (SiNx), or a multilayer thereof.

The semiconductor layer 230 is located on the buffer layer (BUF). The semiconductor layer 230 may be made of a silicon semiconductor or an oxide semiconductor. Silicon semiconductors may include amorphous silicon or crystallized polycrystalline silicon. Here, polycrystalline silicon has high mobility (over 100㎠/Vs), low energy consumption and excellent reliability, so it can be applied to gate drivers and/or multiplexers (MUX) for driving elements or to driving TFTs within pixels. there is. Meanwhile, oxide semiconductors have low off-current, so they are suitable for switching TFTs that have a short on time and a long off time. In addition, since the off-current is small, the pixel voltage maintenance period is long, making it suitable for display devices that require low-speed driving and/or low power consumption. Additionally, the semiconductor layer 230 includes a drain region and a source region containing p-type or n-type impurities, and includes a channel between them.

A gate insulating film (GI) is located on the semiconductor layer 230. The gate insulating film (GI) may be silicon oxide (SiOx), silicon nitride (SiNx), or a multilayer thereof. The gate electrode 260 is located on the gate insulating film GI in a certain area of the semiconductor layer 230, that is, in a position corresponding to the channel where impurities are injected. The gate electrode 260 is selected from the group consisting of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), and copper (Cu). It is formed from either one or an alloy thereof. In addition, the gate electrode 260 is a group consisting of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), and copper (Cu). It may be a multi-layer made of any one selected from or an alloy thereof. For example, the gate electrode 260 may be a double layer of molybdenum/aluminum-neodymium or molybdenum/aluminum.

An interlayer insulating layer (ILD) that insulates the gate electrode 260 is located on the gate electrode 260. The interlayer insulating layer (ILD) may be a silicon oxide layer (SiOx), a silicon nitride layer (SiNx), or a multilayer thereof. A source electrode 270S and a drain electrode 270D are located on the interlayer insulating layer (ILD). The source electrode 270S and the drain electrode 270D are connected to the semiconductor layer 230 through a contact hole exposing the source region of the semiconductor layer 230. The source electrode 270S and the drain electrode 270D may be made of a single layer or multiple layers. If the source electrode 270S is a single layer, molybdenum (Mo), aluminum (Al), chromium (Cr), gold ( It may be made of any one selected from the group consisting of Au), titanium (Ti), nickel (Ni), neodymium (Nd), and copper (Cu), or an alloy thereof. In addition, when the source electrode 270S and the drain electrode 270D are multi-layered, a double layer of molybdenum/aluminum-neodymium, a triple layer of titanium/aluminum/titanium, molybdenum/aluminum/molybdenum, or a triple layer of molybdenum/aluminum-neodymium/molybdenum. It can be done. Accordingly, the driving transistor DR is configured including the semiconductor layer 230, the gate electrode 260, the source electrode 270S, and the drain electrode 270D.

A passivation film (PAS) is located on the substrate (SUB1) including the driving transistor (DR). The passivation film (PAS) is an insulating film that protects the underlying device and may be a silicon oxide film (SiOx), a silicon nitride film (SiNx), or a multiple layer thereof. An overcoat layer (OC) is located on the passivation film (PAS). The overcoat layer (OC) may be a flattening film to alleviate steps in the lower structure, and is made of organic materials such as polyimide, benzocyclobutene series resin, and acrylate. The overcoat layer (OC) can be formed in a method such as SOG (spin on glass) in which the organic material is coated in a liquid form and then cured.

A via hole (VIA) exposing the drain electrode (270D) is located in some areas of the overcoat layer (OC). An organic light emitting diode (OLED) is located on the overcoat layer (OC). More specifically, the first electrode (ANO) is located on the overcoat layer (OC). The first electrode (ANO) acts as a pixel electrode and is connected to the drain electrode (270D) of the driving transistor (DR) through the via hole (VIA). The first electrode (ANO) is an anode and may be made of a transparent conductive material such as ITO (Indium Tin Oxide), IZO (Indium Zinc Oxide), or ZnO (Zinc Oxide). When the first electrode (ANO) is a reflective electrode, the first electrode (ANO) further includes a reflective layer. The reflective layer may be made of aluminum (Al), copper (Cu), silver (Ag), nickel (Ni), or an alloy thereof, and is preferably made of APC (silver/palladium/copper alloy).

A bank layer (BNK) that partitions pixels is located on the substrate (SUB1) including the first electrode (ANO). The bank layer (BNK) is made of organic materials such as polyimide, benzocyclobutene series resin, and acrylate. The bank layer (BNK) has a pixel definition portion (OP) that exposes the first electrode (ANO). An organic layer (EML) in contact with the first electrode (ANO) is located on the front surface of the flexible substrate (PI). The organic layer (EML) is a layer that emits light by combining electrons and holes, and may include a hole injection layer or hole transport layer between the organic layer (EML) and the first electrode (ANO), and may include a hole injection layer or a hole transport layer on the organic layer (EML). It may include an electron transport layer or an electron injection layer.

The second electrode (CAT) is located on the organic layer (EML). The second electrode (CAT) is located in front of the display unit (A/A), and as a cathode electrode, it can be made of magnesium (Mg), calcium (Ca), aluminum (Al), silver (Ag), or an alloy thereof with a low work function. there is. If the second electrode (CAT) is a transmissive electrode, it is thin enough to allow light to pass through, and if it is a reflective electrode, it is thick enough to reflect light.

Meanwhile, in the above-mentioned Figure 6, the emission areas of each subpixel are arranged adjacent to each other in the direction in which the gate line extends. Therefore, there is a possibility that light leakage may occur between adjacent subpixels. On the other hand, as shown in FIG. 8, in the present invention, the light emitting area (E1)/capacitor area (C1)/second subpixel (SPn2) of the first subpixel (SPn1) in the direction in which the first gate line (GL1) extends The light emitting area (E2)/capacitor area (C2) is disposed. That is, since the capacitor area C1 of the first subpixel SPn1 is disposed between the light emitting area E1 of the first subpixel SPn1 and the light emitting area E2 of the second subpixel SPn2, the first The capacitor area C1 of the first subpixel SPn1 blocks light leaking laterally between the subpixel SPn1 and the second subpixel SPn2.

Specifically, referring to FIG. 11, a capacitor lower electrode (LCst), a capacitor middle electrode (MCst), and a first electrode (ANO) are formed on the substrate (SUB1) of the first subpixel (SPn1) and the second subpixel (SPn2), respectively. ) A capacitor (Cst) containing ) is disposed. A passivation film (PAS) is placed on the capacitor middle electrode (MCst), and a red color filter (RCF) is placed on the passivation film (PAS). The overcoat layer (OC) is located on the red color filter (RCF), and the first electrodes (ANO) of each subpixel are located on top of it. Additionally, a bank layer (BNK) is located that partitions the light-emitting area of each subpixel.

As shown in FIG. 8, the capacitor area C1 of the first subpixel SPn1 is between the light emitting area E1 of the first subpixel SPn1 and the light emitting area E2 of the second subpixel SPn2. By being arranged, light leakage between adjacent subpixels can be prevented.

Additionally, the red color filter (RCF) of the first subpixel (SPn1) may have a margin for further application to the area where the capacitor region (C1) of the first subpixel (SPn1) is disposed. In addition, as the capacitor area C1 of the first subpixel SPn1 exists between the light emitting area E1 of the first subpixel SPn1 and the light emitting area E2 of the second subpixel SPn2, The bank layer (BNK) where it is located can also have a wide margin.

Comparing the above-described FIGS. 7 and 10, in FIG. 7, since there are only two data lines between subpixels, the spacing between subpixels is narrow, so light leakage may occur. On the other hand, in FIG. 11, the capacitor area C1 and the first data line DL1 of the wide first subpixel SPn1 are disposed between the first subpixel SPn1 and SPn2. The gap between the first and second subpixels SPn1 and SPn2 can be significantly widened, thereby preventing light leakage. In addition, as the gap between the first and second subpixels (SPn1, SPn2) widens, the red color filter (RCF) can also have a margin that can be formed further toward the second subpixel (SPn2), making it easier to form. It can happen. In addition, as the gap between the first and second subpixels (SPn1, SPn2) widens, the bank layer (BNK) can also have a margin, so the margin of the first electrode (ANO) of the first subpixel (SPn1) also increases. It becomes wider. By widening the margins of the red color filter (RCF), bank layer (BNK), and first electrode (ANO), design can be freed, the aperture ratio can be improved, and the process can be facilitated.

Referring again to FIG. 8, the third subpixel (SPn3) and the fourth subpixel (SPn4) are arranged in the same manner as the first subpixel (SPn1) and the second subpixel (SPn2) to prevent light leakage that may occur between them. can be prevented. And between the second subpixel (SPn2) and the third subpixel (SPn3), the sensing line (VREF), the second data line (DL2), the third data line (DL3), and the capacitor area of the second subpixel (SPn2) The capacitor area (C3) of (C2) and the third subpixel (SPn3) is disposed between the light emitting area (E2) of the second subpixel (SPn2) and the light emitting area (E3) of the third subpixel (SPn3). Prevent possible light leakage.

Meanwhile, the present invention may have a subpixel array structure according to another embodiment to prevent light leakage.

FIG. 12 is a diagram briefly showing the plan layout of subpixels according to another embodiment of the present invention, and FIG. 13 is a diagram showing the plan layout of subpixels in detail according to another embodiment of the present invention. In the following, descriptions of the same configurations as those in FIGS. 8 to 11 described above will be omitted.

Referring to FIGS. 12 and 13 together, first to fourth subpixels (SPn1) to fourth subpixels (SPn4) having light emitting areas (E1 to E4) and capacitor areas (C1 to C4) are arranged on the substrate (SUB1). do. Organic light-emitting diodes (light-emitting devices) are formed in the light-emitting areas (E1 to E4), and capacitors among the circuits that drive the organic light-emitting diodes are placed in the capacitor areas (C1 to C4). In addition to the light emitting region (E1 to E4) and capacitor region (C1 to C4), switching, sensing and driving transistors are formed among the circuits that drive the organic light emitting diode.

First and second power lines (EVDD1, EVDD2), sensing lines (VREF), and first to fourth data lines (DL1 to DL4) are disposed in the first subpixels (SPn1) to fourth subpixels (SPn4). do. The first gate line GL1 and the second gate line GL2 are disposed across the first to fourth subpixels SPn1 to SPn4, and the first to fourth subpixels SPn1 to SPn4 ( They are arranged adjacent to each other with the light emitting areas (E1 to E4) of SPn4) in between.

Wires such as the first and second power lines (EVDD1 to EVDD2), the sensing line (VREF), and the first to fourth data lines (DL1 to DL4), as well as the electrodes that make up the thin film transistor, are located in different layers. They are electrically connected by contact through a contact hole (not shown). The sensing line (VREF) is connected to each sensing transistor (ST) of the first to fourth subpixels (SPn1 to SPn4). The first power line EVDD1 is connected to each driving transistor DR of the first and second subpixels SPn1 and SPn2. The second power line EVDD2 is connected to each driving transistor DR of the third and fourth subpixels SPn3 and SPn4. The first gate line GL1 is connected to the switching transistor SW of the first to fourth subpixels SPn1 to SPn4, and the second gate line GL2 is connected to the switching transistor SW of the first to fourth subpixels SPn1 to SPn4. It is connected to the sensing transistor (ST).

In another embodiment of the present invention, the structure of the third subpixel SPn3 in FIGS. 8 and 9 described above is formed in the left and right directions. Specifically, referring to the third subpixel SPn3, the light emitting area E3 and the capacitor area C3 of the third subpixel SPn3 are arranged in parallel. The sensing line (VREF) and the capacitor area (C3) are arranged adjacent to each other with the light emitting area (E3) in between. Additionally, the third data line DL3 is disposed adjacent to the light emitting area E3 with the capacitor area C3 interposed therebetween.

The third data line DL3 of the third subpixel SPn3 is disposed adjacent to the fourth data line DL4 of the third subpixel SPn3. In particular, in this embodiment, the capacitor area C3 of the third subpixel (SPn3) and the fourth subpixel (SPn3) are formed between the light emitting area (E3) of the third subpixel (SPn3) and the light emitting area (E4) of the fourth subpixel (SPn4). A capacitor area (C4) of 4 subpixels (SPn4) is disposed.

That is, between the light emitting area E3 of the third subpixel SPn3 and the light emitting area E4 of the fourth subpixel SPn4, the capacitor area C3 of the third subpixel SPn3 and the fourth subpixel ( Since the capacitor area C4 of SPn4) is disposed, the capacitor areas C3 and C4 block light leaking laterally between the third subpixel SPn3 and the fourth subpixel SPn4. In addition, the capacitor area C3 of the third subpixel SPn3 and the fourth subpixel ( By arranging the third data line DL3 and the fourth data line DL4 as well as the capacitor area C4 of SPn4), light leakage between adjacent third and fourth subpixels SPn3 and SPn4 can be prevented. there is.

As described above, the display device according to embodiments of the present invention arranges the data line and the light emitting area adjacent to each other with the capacitor area of the subpixel in between, so that the capacitor area is placed between the light emitting area of the adjacent subpixels. Accordingly, light leakage between adjacent subpixels can be prevented.

In addition, the display device according to the embodiments of the present invention has the advantage of easy processing by arranging the capacitor area between the light emitting areas of each subpixel, so that the color filter can have a margin for further application to the capacitor area. .

Although embodiments of the present invention have been described with reference to the accompanying drawings, the technical configuration of the present invention described above can be modified by those skilled in the art in the technical field to which the present invention belongs in other specific forms without changing the technical idea or essential features of the present invention. You will understand that it can be done. Therefore, the embodiments described above should be understood in all respects as illustrative and not restrictive. In addition, the scope of the present invention is indicated by the claims described later rather than the detailed description above. In addition, the meaning and scope of the patent claims and all changes or modified forms derived from the equivalent concept should be construed as being included in the scope of the present invention.

GL1 to GL2: first and second gate lines DL1 to DL4: first to fourth data lines
VREF: Sensing lines EVDD1~EVDD2: 1st and 2nd power lines
SPn1 to SPn4: 1st to 4th subpixels E1 to E4: light emitting area
C1~C4: Capacitor area

Claims (15)

It includes a first subpixel located on the substrate,
The first subpixel is,
a first gate line located on the substrate and a second gate line parallel to the first gate line;
a first data line crossing the first gate line and the second gate line;
a light emitting area disposed in parallel with the first data line and including an organic light emitting diode;
a capacitor area arranged parallel to the light emitting area and between the light emitting area and the first data line; and
a first power line disposed in parallel with the capacitor region with the light emitting region in between, so as not to overlap the capacitor region;
The display device wherein the capacitor area is spaced apart from the first data line in the direction of the light emitting area so as not to overlap the first data line. According to claim 1,
Comprising a second subpixel adjacent to the first subpixel,
The second subpixel is,
a second data line crossing the first gate line and the second gate line;
a light emitting area disposed in parallel with the second data line and including an organic light emitting diode; and
A display device including a capacitor area arranged in parallel with the light-emitting area and between the light-emitting area and the second data line. According to clause 2,
A display device in which a capacitor area of the first subpixel is disposed between a light-emitting area of the first subpixel and a light-emitting area of the second subpixel. According to clause 3,
A display device wherein the first data line is disposed between a capacitor area of the first subpixel and a light emitting area of the second subpixel. According to clause 4,
The first power line is shared by the first subpixel and the second subpixel, respectively. According to claim 5,
A display device adjacent to the capacitor area of the second subpixel with the second data line in between, and including a sensing line shared by the first subpixel and the second subpixel, respectively. According to clause 6,
It includes a third subpixel and a fourth subpixel that are symmetrical to the first subpixel and the second subpixel based on the sensing line, and the sensing line is shared by the third subpixel and the fourth subpixel. Display device. According to clause 7,
The third subpixel includes a third data line, a light emitting area, and a capacitor area,
The display device wherein the third data line is adjacent to the sensing line, and the light emitting area is adjacent to the third data line with the capacitor area interposed therebetween. According to clause 8,
The fourth subpixel includes a fourth data line, a light emitting area, and a capacitor area,
The fourth data line is adjacent to the light emitting area with the capacitor area interposed therebetween. According to clause 9,
A display device wherein the capacitor area of the fourth subpixel is disposed between the light-emitting area of the third subpixel and the light-emitting area of the fourth subpixel. According to clause 6,
It includes a third subpixel and a fourth subpixel neighboring the first subpixel and the second subpixel with the sensing line interposed therebetween, and the sensing line is shared by the third subpixel and the fourth subpixel. displayed display device. According to claim 11,
The third subpixel includes a third data line, a light emitting area, and a capacitor area,
A display device in which the third data line and the light emitting area are adjacent to each other with the capacitor area in between. According to claim 12,
The fourth subpixel includes a fourth data line, a light emitting area, and a capacitor area,
A display device in which the fourth data line and the light emitting area are adjacent to each other with the capacitor area in between. According to claim 13,
The third data line and the fourth data line are arranged adjacent to each other, and a capacitor area of the third subpixel and the fourth subpixel are positioned between the light-emitting area of the third subpixel and the light-emitting area of the fourth subpixel. A display device in which the capacitor area of the pixel is placed. The method of claim 8 or 11,
A display device adjacent to the capacitor area of the fourth subpixel with the light emitting area of the fourth subpixel in between, and including a second power line shared by the third subpixel and the fourth subpixel, respectively.

Images