KR100515465B1 - The organic electro-luminescence device and method for fabricating of the same - Google Patents

Abstract

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an organic light emitting device, and in particular, to block light generated unevenly in this area under the influence of a partition wall, and to provide an organic light emitting device that can further secure storage capacitance. It is about a method.

In the related art, the light emitting layer was not evenly formed by the partition wall formed at the boundary of the pixel region, and the light emission state was uneven in the vicinity of the partition wall.

In order to solve this problem, a separate blocking layer to which a signal is applied is further configured under the partition wall, and the power wiring is extended to the upper portion of the blocking layer.

Such a structure can block light leakage and further secure an auxiliary capacitance, and thus there is an advantage in that a high quality organic light emitting device can be manufactured.

Description

The organic electroluminescent device and method for manufacturing the same

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an organic light emitting device, and more particularly, to a structure and a manufacturing method of an organic light emitting device capable of blocking an uneven light emitting area and further securing an auxiliary capacitance.

In general, organic light emitting diodes inject electrons and holes into the light emitting layer from the electron injection electrodes and the hole injection electrodes, respectively, to inject the injected electrons. ) Is a device that emits light when the exciton, which is a combination of holes and holes, drops from the excited state to the ground state.

Due to this principle, unlike a conventional thin film liquid crystal display device, since a separate light source is not required, there is an advantage in that the volume and weight of the device can be reduced.

The method of driving the organic light emitting device may be divided into a passive matrix type and an active matrix type.

The passive matrix type organic light emitting device has a simple structure and a simple manufacturing method. However, the passive matrix type organic light emitting device has a high power consumption and a large area of the display device, and the opening ratio decreases as the number of wirings increases.

Therefore, the passive matrix type organic light emitting display device is used for a small display device, whereas the active matrix type organic light emitting display device is used for a large display device.

Hereinafter, a configuration of a conventional active matrix organic electroluminescent device will be described with reference to FIG. 1.

1 is a cross-sectional view schematically showing the configuration of an organic light emitting device according to the related art.

As illustrated, the organic light emitting diode 10 includes a thin film transistor (T) array portion 14 on the transparent first substrate 12 and a first electrode 16 on the thin film transistor array portion 14. ) And the organic light emitting layer 18 and the second electrode 20.

In this case, the light emitting layer 18 expresses the colors of red (R), green (G), and blue (B). In a general method, a separate light emitting red, green, and blue light is generated for each pixel (P). Organic materials are patterned and used.

The first substrate 12 is bonded to the second substrate 28 having the moisture absorbent 22 and the sealant 26, thereby completing the encapsulated organic light emitting device 10.

At this time, the moisture absorbent 22 is for removing moisture and oxygen that can penetrate into the capsule, and a part of the substrate 28 is etched and the moisture absorbent 22 is filled in the etched portion and fixed with a tape 25. .

2 is a plan view schematically illustrating a thin film transistor array unit of a conventional organic light emitting diode.

In general, the active matrix thin film transistor array unit includes a switching element T _S , a driving element T _D , and a storage capacitor C _{ST for} each of a plurality of pixels defined in the substrate 12. According to a characteristic, the switching element T _S or the driving element T _D may be formed of a combination of one or more thin film transistors, respectively.

In this case, the substrate 12 uses a transparent insulating substrate, and the material may be, for example, glass or plastic.

As shown in the drawing, a gate wiring 32 formed in one direction spaced apart from each other by a predetermined interval on the substrate 12 and a data wiring 34 intersecting with the gate wiring 32 and an insulating film interposed therebetween.

At the same time, a power supply wiring 35 spaced in parallel with the data wiring 34 and intersecting with the gate wiring 32 is formed.

The switching element T _S and the driving element T _D include gate electrodes 36 and 38, an active layer 40 and 42, a source electrode 46 and 48, and a drain electrode 50 and 52, respectively. Thin film transistors are used.

In the above-described configuration, the gate electrode 36 of the switching element T _S is connected to the gate line 32, and the source electrode 46 is connected to the data line 34.

The drain electrode 50 of the switching element T _S is connected to the gate electrode 38 of the driving element T _D through the contact hole 54.

The source electrode 48 of the driving element T _D is connected to the power line 35 through the contact hole 56.

In addition, the drain electrode 52 of the driving element T _D is configured to contact the first electrode 16 configured in the pixel portion P.

The power supply line 35 and the first electrode 15, which is a polycrystalline silicon layer under the power line 35, overlap each other with an insulating layer therebetween to form a storage capacitor C _ST .

In the above-described configuration, the partition wall 60 is formed corresponding to the upper portion of the data line 34 and the power supply line 35, and the partition wall 60 has an organic light emitting layer that emits a specific color for each pixel P. Isolate.

In this case, the organic light emitting layer (not shown) may use a polymer organic light emitting layer and a low molecular organic light emitting layer, and in general, a low molecular organic light emitting layer is formed by a deposition method, and in the case of a polymer organic light emitting layer, a coating or a printing method is formed. do.

However, during the process of forming and curing the organic light emitting layer, the volume thereof is reduced, and in this process, the thickness of the light emitting layer (not shown) of the peripheral portion A of the partition 60 and the portion B corresponding to the pixel region is shown. Varies, and light is unevenly emitted from the periphery A of the partition wall 60.

A description with reference to FIG. 3 is as follows.

3 is a cross-sectional view taken along line II-II ′ of FIG. 2.

(FIG. 2 is a planar configuration, but only the first electrode is shown in order to avoid complexity, but the light emitting layer is shown in the configuration of FIG. 3).

As shown, a partition wall 60 is formed on the data line 34 and the power supply line 35 on the substrate 100, and the first electrode 16 independently of the pixel area P is independently provided. Patterned.

As described above, the organic light emitting layer 62 is formed on the upper portion of the first electrode 60 corresponding to the partition walls 60. As shown in FIG. The thicknesses of the portion A corresponding to the side surface and the portion corresponding to the center B of the pixel region are different.

Accordingly, the light emitted from the portion A corresponding to the side surface of the partition wall 60 represents a difference from the light emitted from the central portion B of the pixel region, and the light leakage from the side pixel region portion A of the partition wall. The phenomenon appears and there is a problem that causes the image quality unevenness of the organic light emitting device.

The present invention has been proposed for the purpose of solving the above problems, proposes a configuration to prevent light leakage by configuring a separate blocking pattern on the portion where the light leakage occurs.

In addition, the power supply wiring described above is extended to the upper portion of the blocking pattern.

Such a configuration can block the light emission non-uniformity region by the blocking pattern, and can further secure the auxiliary capacitance by the auxiliary capacitance portion formed by the blocking pattern and the power wiring, and thus a high quality organic light emitting device can be manufactured. There is an advantage.

According to an aspect of the present invention, there is provided an organic light emitting display device including: gate wiring and data wiring defining a pixel region by crossing vertically with an insulating film interposed therebetween on a substrate; A switching element formed at an intersection of said gate wiring and data wiring, said switching element comprising a gate electrode, an active layer, a source electrode and a drain electrode; A drive element comprising a gate electrode in contact with the drain electrode of the switching element, an active layer, a source electrode and a drain electrode; A blocking pattern branched from the gate electrode of the driving element and vertically extending to both sides of the pixel region in close proximity to the data line; A power supply wire in contact with a drain electrode of the driving device, the power wire including a vertical branch extending in one direction in parallel with the gate wire and branched to an upper portion of the blocking pattern; A partition wall extending in one direction on a front surface of the data line and an upper portion corresponding to a portion of the blocking pattern; A transparent first electrode configured to correspond to the pixel region; An organic light emitting layer formed on the first electrode; It includes a second electrode configured on the organic light emitting layer.

The blocking pattern is a means for blocking the light emitting non-uniformity generated in the periphery of the partition wall is located on the lower side of one side and the other side of the partition wall.

A storage capacitor portion having the blocking pattern as the first electrode and a power supply wiring configured to overlap the plane of the blocking pattern in a planar manner as the second electrode is formed.

According to an aspect of the present invention, there is provided a method of manufacturing an organic light emitting display device, the method comprising: forming a gate wiring and a data wiring on a substrate to vertically intersect an insulating film therebetween to define a pixel region; Forming a switching element formed at an intersection of said gate wiring and data wiring, said switching element comprising a gate electrode, an active layer, a source electrode and a drain electrode; Forming a driving element including a gate electrode in contact with the drain electrode of the switching element, an active layer, a source electrode and a drain electrode; Forming a blocking pattern branched from the gate electrode of the driving device and extending vertically to both sides of the pixel area in close proximity to the data line; Forming a power line in contact with the drain electrode of the driving element, the power line including a vertical branch extending in one direction in parallel with the gate line and branched to an upper portion of the blocking pattern; Forming a partition wall configured to extend in one direction on a front surface of the data line and a portion corresponding to a portion of a blocking pattern; Forming a transparent first electrode corresponding to the pixel region; Forming an organic emission layer on the first electrode corresponding to the pixel region; And forming a second electrode on the organic light emitting layer.

The first electrode is an anode electrode for injecting holes into the light emitting layer, the second electrode is a cathode electrode for injecting electrons into the light emitting layer, and the first electrode is an indium-tin-oxide ( ITO), and the second electrode is formed of one selected from metals including calcium (Ca), aluminum (Al), and magnesium (Mg).

The active layer is in contact with the source and drain electrodes, and the contact portion is a polycrystalline silicon layer partially doped with n + or p + and impurities.

Hereinafter, exemplary embodiments of the present invention will be described with reference to the accompanying drawings.

Example

A feature of the present invention is characterized by further comprising a blocking pattern that covers the light emission non-uniform area around the partition wall, by using it can further secure the auxiliary capacitance.

4 is a diagram schematically illustrating a wiring configuration of an organic light emitting diode according to the present invention.

As shown in the drawing, the gate line 126 is formed in one direction of the substrate 100, and the data line 148 defining the pixel area P is formed by crossing the gate line 126 perpendicularly.

The power supply wiring 130 including the vertical portions 130 (A) and 130 (B) spaced apart in parallel with the gate wiring 126 and vertically branched in a direction parallel to the data wiring 148. Form.

A switching element T _S and a driving element T _D connected thereto are formed at an intersection point of the gate line 126 and the data line 148.

The switching and driving elements T _S and T _D are thin film transistors including gate electrodes 120 and 122, active layers (polycrystalline layers) 112 and 114, source electrodes 142 and 150, and drain electrodes 146 and 152, respectively. The source electrode 142 of the element T _S is connected to the data line 148, and the gate electrode 120 uses a part of the gate line 126. At the same time, the driving element T _D The gate electrode 122 is connected to the drain electrode 146 of the switching element T _S , the source electrode 150 is connected to the power supply line 130, and the drain electrode 152 is formed in the display area. It is connected to the negative first electrode 158.

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In the above-described configuration, the partition wall 164 is formed on the upper portion of the data line 148, and the extension part 24 extending from the gate electrode 122 of the driving element T _{D on} both lower sides of the partition wall 164. ) And the blocking patterns 124 (A) and (B) extending perpendicularly to both sides of the pixel region P in the extension part, extend along the partition wall 164. In this case, the blocking patterns 124 (A) and (B) are configured for each pixel area P. FIG.

In the above-described configuration, the blocking patterns 124 (A) and (B) have a shape overlapping with each other at a lower portion of the branched vertical portions 130 (A) and (B) of the power wiring 130. As a result, an auxiliary capacitance portion C _ST having the blocking pattern 124 as the first electrode and the vertical portions 130 (A) and (B) of the power supply wiring 130 as the second electrode is formed. .

As described above, the blocking patterns 124 (A) and (B) may block abnormal light emission generated in the vicinity of the partition wall 164, and thus, the auxiliary storage unit C _ST may be further conventionally added. It is a structure that can be secured.

Hereinafter, a method of manufacturing an organic light emitting diode according to the present invention will be described with reference to FIGS. 5A to 5G, 6A to 6G, and 7A to 7G.

5A to 5G, 6A to 6G, and 7A to 7G are cut along the lines V-V ′, VI-VI ′, and VIII-V of 4, and are shown in the process sequence of the present invention. to be.

5A to 5G, 6A to 6G, and 7A to 7G describe a conventional manufacturing process in the order of a mask process, and the mask process is a process of exposing, developing, and etching a thin film. A process of patterning into a shape, and a thin film transistor having a coplanar structure using an active layer of a thin film transistor used as a switching element as polysilicon.

First, as shown in FIGS. 5A and 6A to 7A, the switching unit S, the driving unit D, and the display unit P are defined on the substrate.

Subsequently, after depositing amorphous silicon (a-Si: H) on the entire surface of the substrate 100, a dehydrogenation process and a crystallization process using heat, formed into a polycrystalline silicon layer, and then patterned the switching First and second active patterns 112 and 114 are formed in the unit S and the driving unit D, respectively.

The first and second active patterns 112 and 114 may be defined as first active regions 112a and 114a and second active regions 112b and 114b, respectively.

Subsequently, the gate insulating layer 116, which is the first insulating layer, and the first metal layer 118 are sequentially stacked on the entire surface of the substrate 100 on which the first and second active patterns 112 and 114 are formed.

The gate insulating layer 116 is formed by depositing one selected from a group of inorganic insulating materials including silicon nitride (SiN _X ) and silicon oxide (SiO ₂ ), and the first metal layer is formed of aluminum (Al), aluminum alloy, and copper. (Cu), tungsten (W), tantalum (Ta) and molybdenum (Mo), including one selected from the group of conductive metals.

As shown in FIGS. 5B, 6B, and 7B, the gate insulating layer 116 is patterned to correspond to the first active regions 112a and 114a of the switching unit S and the driving unit D, respectively. Gate electrodes 120 and 122 are formed on the top of the substrate.

At the same time, an extension part connected to the gate electrode 120 of the switching unit S and extending in one direction to form a gate wiring (126 in FIG. 4) and extending from the gate electrode 122 of the driving unit D is formed. Blocking patterns 124 (A) and (B) branched at both sides of the pixel region P at 124 and extending along both sides of the pixel region P which are not parallel to the gate wiring 126 of FIG. 4. To form.

In this case, the blocking patterns 124 (A and B) are connected to the gate electrode 122 of the driving unit D so as to be configured independently for each pixel region P. The vertical portion of the power line is configured to be stacked up and down to form the storage capacitor C _ST , which is formed on both sides of the pixel area unlike the conventional art, and thus has an advantage of further securing the storage capacitor.

Next, gate electrodes 120 and 122 are formed to correspond to the blocking patterns 124 (A and B), the gate wiring 126 of FIG. 4, and the switching unit S and the driving unit D, respectively. After doping p + or n + over the entire surface of the substrate 100 and activating the second active region 112b and 114b corresponding to the switching unit S and the driving unit D, an ohmic contact layer is formed. Be sure to

The substrate 100 on which the blocking patterns 124 (A) and (B), the gate wiring line 126 of FIG. 4, and the gate electrodes 120 and 122 are formed in correspondence with the switching unit S and the driving unit D, respectively. The interlayer insulating film, which is the second insulating film 128, is formed on the entire surface of the _N-C ) as one selected from the group of inorganic insulating materials including silicon nitride (SiN _X ) and silicon oxide (SiO ₂ ).

Next, a conductive metal is deposited and patterned on the entire surface of the substrate 100 on which the second insulating layer 120 is formed, extending in one direction in parallel with the gate wiring 126 of FIG. 4, and blocking the pattern 124. Power wiring 130 having vertical branch portions 130 (A) and 130 (B) extending along the blocking patterns 124 (A) and (B) and branching to the upper portions of (A) and (B). To form.

As shown in FIGS. 5C, 6C, and 7C, a third insulating layer 132 is formed by depositing one selected from the aforementioned group of insulating materials on the entire surface of the substrate 100 on which the power wiring 130 is formed. And patterns to form the first, second, third and fourth contact holes 134a, 134b, 136a, and 136b exposing the second active regions 112b and 114b corresponding to the switching unit S and the driving unit D. And a fifth contact hole 138 exposing a part of the end of the gate electrode 122 formed in the driving unit D, and a sixth contact hole 140 exposing a part of the power wiring 130. do.

As shown in FIGS. 5D, 6D, and 7D, the conductive metal as described above is deposited and patterned on the third insulating layer 132 on which the plurality of contact holes are formed to correspond to the switching unit S. FIG. And the source electrode 142 and the drain electrode 146 respectively contacting the exposed second active region 112a and the data connected to the source electrode 142 and perpendicularly intersect the gate wiring 126 of FIG. 4. The wiring 148 is formed, and the source electrode 150 and the drain electrode 152 are formed to contact the second active region 114b exposed in correspondence with the driving unit D.

At the same time, the drain electrode 146 formed corresponding to the switching unit S is configured to be in contact with the gate electrode 122 corresponding to the driving unit D, and the source electrode formed corresponding to the driving unit D ( 150 is in contact with the exposed power wiring 130.

In the process as described above, a switching thin film transistor T _S is formed in the switching unit S, and a driving thin film transistor T _D is formed in the driving unit D.

5E, 6E, and 7E, an insulating film is coated on the entire surface of the substrate 100 on which the source electrodes 142 and 150 and the drain electrodes 146 and 152 of the thin film transistors T _S and T _D are formed. A protective film 154 that is a fourth insulating film is formed.

The protective layer is successively patterned to form a drain contact hole 156 exposing a part of the drain electrode 152 constituting the driving thin film transistor T _D.

5F, 6F, and 7F, a transparent conductive layer including indium tin oxide (ITO) and indium zinc oxide (IZO) on the entire surface of the substrate 100 on which the passivation layer 152 is formed. A selected one of the metal materials is deposited and patterned to form a first electrode 158 formed in the pixel portion P while contacting the exposed drain electrode 154.

The first electrode 158 is a hole injection electrode (anode) for injecting a hole (hole).

5G, 6G, and 7G, a fifth insulating film 160 is formed on the entire surface of the substrate 100 on which the first electrode 158 is formed, and then patterned to form the first electrode 158. Proceed with the process of exposing.

Next, a partition wall 164 is formed on the data line 148 including the blocking patterns 124 (A) and (B) on the first electrode 158.

In general, the partition 164 is formed by patterning an acrylic resin, which is generally a photosensitive resin.

Next, an emission layer 166 is formed by depositing or coating an organic light emitting material corresponding to the display unit inside the partition 164, and a metal having a low work function such as aluminum (Al) is formed on the emission layer 166. The deposition forms a second electrode 168.

In this case, the light emitting layer 166 may be configured as a single layer or a multi-layer, and in the case of the multilayer structure, the hole transport layer 166a is further formed between the main light emitting layer 166b and the first electrode 158, and the main light emitting layer ( 166b and the electron transport layer 166c of the second electrode 168 are further configured.

The material forming the second electrode may be formed of one selected from aluminum (Al), calcium (Ca), and magnesium (Mg) or a double metal layer of lithium fluorine / aluminum (LIF / Al).

Through the process as described above it can be produced an organic light emitting device according to the present invention.

 The organic light emitting device according to the present invention manufactured as described above forms a blocking pattern on one side and the other side of the partition walls located on both sides of the pixel region while forming the gate wiring, and the power wiring is formed on the blocking pattern. It is characterized by extending.

As described above, the organic light emitting device according to the present invention may mask the light emission non-uniformity generated around the partition wall by the blocking pattern, and the auxiliary capacitor formed by the power line and the blocking pattern may have more capacitive characteristics than before. The structure can be more secured.

Therefore, there is an effect that can produce an organic light emitting device that implements high quality.

1 is a plan view schematically showing one pixel of a conventional organic light emitting diode,

2 is a plan view schematically illustrating an array wiring configuration of a conventional organic light emitting device,

3 is a cross-sectional view taken along II-II ′ of FIG. 2;

4 is an enlarged plan view illustrating an enlarged pixel of an organic light emitting diode according to the present invention;

5A to 5G, 6A to 6G, and 7A to 7G are cut along VVV ′, VI-VI ′, VIII-VIII of FIG. 4, and are shown according to the process sequence of the present invention. It is a cross section.

<Brief description of the main parts of the drawing>

100 substrate 112 active layer of switching element

114: active layer of driving element 124: blocking pattern

130: power supply wiring 142: source electrode of the switching element

146: drain electrode of switching element 148: data wiring

150 source electrode of driving element 152 drain electrode of switching element

158: first electrode of the light emitting portion 164: partition wall

Claims (14)

Gate wiring and data wiring crossing the insulating film on the substrate and vertically intersecting to define a pixel region; A switching element formed at an intersection of said gate wiring and data wiring, said switching element comprising a gate electrode, an active layer, a source electrode and a drain electrode; A drive element comprising a gate electrode in contact with the drain electrode of the switching element, an active layer, a source electrode and a drain electrode; A blocking pattern branched from the gate electrode of the driving element and vertically extending to both sides of the pixel region in close proximity to the data line; A power supply wire in contact with a drain electrode of the driving device, the power wire including a vertical branch extending in one direction in parallel with the gate wire and branched to an upper portion of the blocking pattern; A partition wall extending in one direction on a front surface of the data line and an upper portion corresponding to a portion of the blocking pattern; A transparent first electrode configured to correspond to the pixel region; An organic light emitting layer formed on the first electrode; A second electrode formed on the organic light emitting layer An organic light emitting device comprising a. The method of claim 1, The blocking pattern is disposed below the barrier rib, and is an organic light emitting device as a means for blocking the light emitting non-uniformity generated around the barrier rib. The method of claim 1, An organic light emitting device comprising an auxiliary capacitor having the blocking pattern as a first electrode and a power line formed on the blocking pattern planarly overlapping with the second electrode as a second electrode. The method of claim 1, The first electrode is an anode electrode for injecting holes into the light emitting layer, and the second electrode is a cathode electrode for injecting electrons into the light emitting layer. The method of claim 4, wherein The first electrode is an indium tin oxide (ITO) organic light emitting device. The method of claim 4, wherein The second electrode is an organic light emitting device comprising one selected from metals including calcium (Ca), aluminum (Al), magnesium (Mg). The method of claim 1, And the active layer is in contact with the source and drain electrodes, and the contact portion is a n + or p + polycrystalline silicon layer partially doped with impurities. Forming gate wirings and data wirings on the substrate to vertically intersect an insulating film therebetween to define pixel regions; Forming a switching element formed at an intersection of the gate line and the data line, the switching element including a gate electrode, an active layer, a source electrode, and a drain electrode; Forming a driving element including a gate electrode in contact with the drain electrode of the switching element, an active layer, a source electrode and a drain electrode; Forming a blocking pattern branched from the gate electrode of the driving device and extending vertically to both sides of the pixel area in close proximity to the data line; Forming a power line in contact with the drain electrode of the driving element, the power line including a vertical branch extending in one direction in parallel with the gate line and branched to an upper portion of the blocking pattern; Forming a partition wall configured to extend in one direction on a front surface of the data line and a portion corresponding to a portion of a blocking pattern; Forming a transparent first electrode corresponding to the pixel region; Forming an organic emission layer on the first electrode corresponding to the pixel region; Forming a second electrode on the organic light emitting layer Organic electroluminescent device manufacturing method comprising a. The method of claim 8, The blocking pattern is a lower portion of the partition, the organic light emitting device manufacturing method means for blocking the light emitting non-uniformity generated around the partition. The method of claim 8, And a storage capacitor portion having the blocking pattern as a first electrode and a power wiring formed on the blocking pattern planarly overlapping with the second electrode as a second electrode. The method of claim 8, The first electrode is an anode electrode (hole electrode) for injecting holes in the light emitting layer, the second electrode is a cathode electrode (cathode electrode) for injecting electrons into the light emitting layer (cathode electrode) manufacturing method. The method of claim 11, The first electrode is an indium tin oxide (ITO) manufacturing method of an organic light emitting device. The method of claim 11, The second electrode is an organic electroluminescent device manufacturing method formed of one selected from metals including calcium (Ca), aluminum (Al), magnesium (Mg). The method of claim 8, And the active layer is in contact with the source and drain electrodes, and the contact portion is a n + or p + polycrystalline silicon layer partially doped with impurities.