KR20100071704A - Dual plate type organic electro-luminescent device and the method for fabricating thereof - Google Patents

Abstract

PURPOSE: A dual plate type organic electro-luminescent device and a method for fabricating thereof are provided to minimize the bonding failure by improving the durability of elements. CONSTITUTION: A first substrate(105) and a second substrate(110) are divided into a display space and a non-display area. A gate wiring and a data line define a pixel region. A switching transistor is formed at each crossing point of the data line and the gate wiring. A driving transistor(Td) is connected to the switching transistor. An inter-layer insulating film(165) covers the top of the driving transistor and switching. An inter-layer insulating film comprises a drain contact hole and a plurality of groove patterns(GP). A connecting electrode(170) is connected to the drain electrode of the driving transistor. The first electrode is formed over the bottom of the second substrate.

Description

Dual plate type organic electroluminescent device and its manufacturing method {Dual Plate Type Organic Electro-luminescent Device and the method for fabricating example}

The present invention relates to an organic electroluminescent device of a dual plate method, and more particularly, to improve the problem of lowering the production yield due to poor bonding between the first and second substrates.

In general, organic light emitting diodes, which are one of flat panel displays, have high luminance and low operating voltage characteristics. In addition, the self-luminous self-illuminating type provides high contrast ratio, enables ultra-thin display, easy response time with several microsecond response time, no restriction on viewing angle, and stable at low temperatures. Since it is driven at a low voltage of 5V to 15V of DC, it is easy to manufacture and design a driving circuit.

The organic light emitting diode having such characteristics is classified into a passive matrix type and an active matrix type. In the passive matrix method, since a scan line and a signal line cross each other and constitute a device in a matrix form, the scan lines are sequentially driven over time in order to drive each pixel. In order to display, the instantaneous luminance should be as much as the average luminance multiplied by the number of lines.

However, in the active matrix method, a thin film transistor, which is a switching element for turning on / off pixels, is positioned for each pixel, and the first electrode connected to the thin film transistor is turned on and off in units of pixels. The second electrode facing the first electrode is formed on the entire surface to become a common electrode.

In the active matrix method, a voltage applied to a pixel is charged in a storage capacitor (Cst), and the power is applied until the next frame signal is applied, thereby irrespective of the number of scan lines. Run continuously for one screen. Therefore, even when a low current is applied, the same luminance is achieved, and thus, low power consumption, high definition, and large size can be obtained. Recently, an active matrix type organic light emitting diode is mainly used.

Basic structure and operation characteristics of the organic light emitting diode of the active matrix method will be described in detail with reference to the accompanying drawings.

1 is a circuit diagram illustrating a unit pixel of a conventional active matrix type organic light emitting diode.

As illustrated, the unit pixel of the active matrix organic light emitting diode according to the related art includes a switching transistor Ts, a driving transistor Td, a storage capacitor Cst, and an organic light emitting diode E.

That is, the gate line GL formed in one direction, the data line DL defining the pixel region P by crossing the gate line GL perpendicularly, and the power line voltage are spaced apart from the data line DL. Power wirings PL for application are respectively formed.

In addition, a switching transistor Ts is formed at an intersection point of the gate line GL and the data line DL, and a driving transistor Td electrically connected to the switching transistor Ts is formed.

In this case, the driving transistor Td is electrically connected to the organic light emitting diode E. That is, the first electrode, which is one terminal of the organic light emitting diode E, is connected to the drain electrode of the driving transistor Td, and the second electrode, which is the other terminal, is connected to the power supply wiring PL. The power wiring PL serves to transfer the power voltage to the organic light emitting diode E. In addition, a storage capacitor Cst is formed between the gate electrode and the source electrode of the driving transistor Td.

Therefore, when a signal is applied through the gate line GL, the switching transistor Ts is turned on, and the signal of the data line DL is transferred to the gate electrode of the driving transistor Td. Light is output by the electric field-pole pair of the organic light emitting diode E connected thereto at the turn-on of the driving transistor Td. At this time, when the driving transistor Td is turned on, the level of the current flowing from the power supply line PL to the organic light emitting diode E is determined, which causes the organic light emitting diode E to have a gray scale (gray). scale).

In addition, the storage capacitor Cst serves to maintain a constant gate voltage of the driving transistor Td when the switching transistor Ts is turned off, thereby turning off the switching transistor Ts. Even in the state, the level of the current flowing through the organic light emitting diode E can be kept constant until the next frame.

In general, such an organic light emitting diode has an organic light emitting diode including an array element such as a thin film transistor, an anode and a cathode electrode, and an organic light emitting layer formed on one substrate. As an example, studies have been actively conducted on a dual plate type organic light emitting diode having a structure in which an array device and an organic light emitting diode are formed on different substrates and connected to each other by a columnar connection electrode.

Hereinafter, the organic light emitting diode of the dual plate type according to the related art will be described with reference to the accompanying drawings.

2 is a cross-sectional view schematically illustrating a conventional dual plate type organic light emitting device.

As shown in the drawing, a conventional dual plate type organic light emitting diode 1 includes a first substrate 5 divided into a display area AA that implements an image and a non-display area NAA that does not implement an image. And a second substrate 10. The panel 30 is referred to as including the first substrate 5 and the second substrate 10. In this case, the display area AA is subdivided into a pixel region P and a driving region Dr in which the driving transistor Td is formed, which is defined by the vertical intersection of the gate wiring (not shown) and the data wiring (not shown). do.

A gate wiring and a data wiring on the first substrate 5 that vertically intersect to define the pixel region P, a switching transistor (not shown) positioned at each intersection of the gate wiring and the data wiring, and the switching transistor; One side of the driving transistor Td is formed to be spaced apart from one side. A passivation layer 55 including a drain contact hole DCH exposing the drain electrode 34 of the driving transistor Td is formed on the switching transistor and the driving transistor Td. The connection electrode 70 is formed on the passivation layer 55 to be in contact with the drain electrode 34 through the drain contact hole DCH.

In this case, the driving transistor Td includes a gate electrode 25, a gate insulating layer 45, a semiconductor layer 40, and source and drain electrodes 32 and 34. The semiconductor layer 40 may be formed of a single layer made of crystalline silicon (p-Si).

On the other hand, the auxiliary electrode 60 is formed on a lower surface of the second substrate 10 at a position corresponding to the data line of the first substrate 5. In addition, a first electrode 80 is formed on a lower front surface of the auxiliary electrode 60, and a buffer pattern covering the auxiliary electrode 60 for each pixel region P is formed below the first electrode 80. 62) is formed.

In this case, the auxiliary electrode 60 is selected from a group of conductive materials including molybdenum (Mo) and molybdenum alloy (MoNd), and the first electrode 80 is indium tin oxide (ITO) and indium zinc. Each is selected from a group of transparent conductive materials having a relatively high work function such as -oxide (IZO).

In addition, a partition 64 having a reverse taper structure is formed in a lower portion overlapping the buffer pattern 62 with the buffer pattern 62 interposed therebetween, and a pixel is formed at one side spaced apart from the partition 64. One-to-one patterned spacer 50 corresponding to each region P is formed.

Each pixel region P divided by the partition 64 has an organic emission layer 82 in contact with the first electrode 80 and a second electrode 84 in contact with the lower portion of the organic emission layer 82. It is formed in turn. At this time, the organic emission layer 82 and the second electrode 84 formed in the pixel region P are separated from the neighboring pixel region P by the partition wall 64 having an inverse taper shape, and the patterned spacer 50 is formed. It is formed covering the side and the bottom surface.

The patterned spacer 50 positioned on the lower surface in contact with the buffer pattern 62 connects the connection electrode 70 of the formulation 1 substrate 5 and the second electrode 84 of the second substrate 10. At the same time, the cell gap between the first substrate 5 and the second substrate 10 is kept constant.

The organic emission layer 82 may be designed to be made of an organic material emitting red (R), green (G), and blue (B) for each pixel area P, thereby realizing full color. The first substrate 5 and the second substrate 10 are opposed to each other by a seal pattern 90 formed along an edge of the non-display area NAA.

The seal pattern 90 may be formed by applying a sealant made of a thermosetting resin or an ultraviolet curable resin by screen printing, and curing the sealant by a thermosetting and an ultraviolet curing process.

Referring to the bonding process of the conventional dual-plate type organic light emitting device having the above-described configuration, the sealant is applied along the edge of the inside of the vacuum chamber (not shown) maintained in about 3 to 10torr atmosphere The second substrate 10 is dropped, and the first contact with the first substrate 5 is performed. At this time, the sealant may be formed along the edge of the first substrate 5. The inside of the first and second substrates 5 and 10 is brought into a vacuum state by using an inert gas including N ₂ and Ar into the first and second substrates 5 and 10 that are in primary contact. . The first and second substrates 5 and 10 are bonded to each other by using a pressure difference between the inside and the outside of the panel 30 generated at this time.

In particular, the bonding of the first and second substrates 5 and 10 is performed through the seal pattern 90 formed along the edge of the non-display area NAA. The seal pattern 90 functions to prevent moisture permeation due to moisture or oxygen from the outside of the panel 30.

In addition, in order to secure the reliability of the device to form a metal thin film layer (not shown) that acts as a moisture absorbent, such as Ca, CaO, Sr, SrO on the lower surface of the second electrode 84 to prevent defective shrinkage of organic matter The structure may be applied.

However, in the bonding process of the first and second substrates 5 and 10 using the above-described vacuum bonding method, the patterned spacers 50 made of photoresist and positioned for each pixel region P are formed of the first and second. The problem is that some of the patterned spacers 50 whose hardness is weak due to non-uniformity or excessive pressure on the entire surfaces of the substrates 5 and 10 are lost or collapsed.

In particular, the patterned spacer 50 is designed to have a relatively high height than other devices, and is made of a photoresist material having a weak hardness. For this reason, a defect may occur in which the patterned spacer 50 is lost or collapsed in the process of bonding the first and second substrates 5 and 10. This defect acts as a passage through which moisture or oxygen introduced from the outside penetrates into the inner space of the organic light emitting layer 82 positioned for each pixel region P, and furthermore, the lifespan is reduced due to the shrinkage of the organic light emitting layer 82. It is causing a problem.

In addition, when the organic light emitting device of the dual plate type is made medium / large, the height of the patterned spacer 50 of the entire panel 30 may be precisely adjusted due to the difference in the exposure amount at the center and the outer portion of the panel 30. Difficulty in controlling Due to the height difference of the patterned spacer 50, the production yield is rapidly reduced due to the contact failure during the bonding process of the first and second substrates 5 and 10.

SUMMARY OF THE INVENTION The present invention has been made to solve the above-described problem, and an object of the present invention is to minimize the defect of bonding and to prolong the life of the device in the dual-plate type organic light emitting device.

According to an aspect of the present invention, there is provided a dual plate type organic light emitting device, which is divided into a display area and a non-display area, and includes: a first substrate and a second substrate facing each other; Gate wirings and data wirings defining a pixel area perpendicularly crossing the first substrate; A switching transistor formed at each intersection point of the gate wiring and data wiring, and a driving transistor connected one-to-one with the switching transistor; An interlayer insulating layer covering an upper portion of the switching and driving transistor, the drain contact hole exposing the drain electrode of the driving transistor, and having a plurality of groove patterns formed in each pixel region except the drain contact hole; A connection electrode connected to the drain electrode of the driving transistor on the interlayer insulating layer; A first electrode formed on the lower front surface of the second substrate; A buffer pattern covering the auxiliary electrode under the first electrode; A partition wall formed in an inverse taper shape in a lower portion overlapping the buffer pattern; A patterned spacer positioned at each pixel area toward one side spaced apart from the partition wall; An organic emission layer and a second electrode sequentially connected to the first electrode for each pixel area divided by the barrier rib; And a seal pattern for bonding the first and second substrates along the non-display area, and an internal filler interposed by each pixel region except for an area corresponding to the patterned spacer by the plurality of groove patterns. .

In this case, a passivation layer may be further formed between the switching and driving transistor and the interlayer insulating layer.

The protective layer may be formed of one selected from the group of inorganic insulating materials including silicon oxide and silicon nitride, and the interlayer insulating film is selected from the group of organic insulating materials including benzocyclobutene and photoacryl.

The plurality of groove patterns may be formed by patterning the interlayer insulating layer, and the plurality of groove patterns may be formed in any one selected from a checkerboard shape and a red cross shape in plan view.

The plurality of groove patterns are selected from a design range of a depth that does not expose the switching and driving transistors from the exposed surface to the outside.

According to an aspect of the present invention, there is provided a method of manufacturing a dual plate organic light emitting device, the method including: forming a gate line and a data line vertically crossing a first substrate to define a pixel area; Forming a switching transistor and a driving transistor connected to the switching transistor one-to-one at each intersection point of the gate wiring and the data wiring; Forming an interlayer insulating layer covering an upper portion of the switching and driving transistor and including a drain contact hole exposing a drain electrode of the driving transistor and a plurality of groove patterns for each pixel region excluding the drain contact hole; Forming a connection electrode connected to the drain electrode of the driving transistor on the interlayer insulating layer; Forming a first electrode on a lower front surface of the second substrate; Forming a buffer pattern covering the auxiliary electrode under the first electrode; Forming a patterned spacer and a barrier under the overlapping buffer pattern; Forming an organic emission layer and a second electrode connected to the first electrode for each pixel area separated from the barrier rib; Applying a first sealant along an edge of the non-display area of the first substrate, and dropping a second sealant for each pixel area except for an area corresponding to the patterned spacer; Hardening the first and second sealants to form a seal pattern and an internal filler.

In this case, a passivation layer may be further formed between the switching and driving transistor and the interlayer insulating layer. The protective layer may be formed of one selected from the group of inorganic insulating materials including silicon oxide and silicon nitride, and the interlayer insulating film is selected from the group of organic insulating materials including benzocyclobutene and photoacryl.

The plurality of groove patterns may be formed by patterning the interlayer insulating film, and the plurality of groove patterns may be formed in any one selected from a checkerboard shape and a red cross shape in plan view.

The second sealant is characterized in that formed in the dropping method using the injection device. In this case, the plurality of groove patterns may be selected from a design range having a depth that does not expose the switching and driving transistors to the outside from the exposed surface.

In the present invention, first, the durability of the panel may be improved by filling the internal filler for each pixel region except for the portion where the patterned spacer is formed.

Second, it is possible to improve the device reliability and lifespan as a structural advantage that can more effectively shield the moisture, oxygen, etc. flowing from the outside, it is possible to improve the problem of lowering the production yield due to contact failure.

--- Example ---

The present invention forms an interlayer insulating film including a plurality of groove patterns partitioned by pixel regions on a first substrate, and interposes an internal filler capable of improving durability of the first substrate and the second substrate corresponding to the plurality of groove patterns. It is characterized by one.

Hereinafter, a dual plate type organic light emitting diode according to the present invention will be described with reference to the accompanying drawings.

3 is a cross-sectional view showing an organic light emitting device of a dual plate type according to the present invention.

As illustrated, the dual plate organic light emitting diode according to the present invention includes a first substrate 105 and a first substrate divided into a display area AA that implements an image and a non-display area NAA that does not implement an image. 2 includes a substrate 110. The panel 130 is referred to as including the first substrate 105 and the second substrate 110. In this case, the display area AA is subdivided into a pixel region P and a driving region Dr in which the driving transistor Td is formed, which is defined by the vertical intersection of the gate wiring (not shown) and the data wiring (not shown). do.

A gate wiring and a data wiring crossing each other on the first substrate 105 to define a pixel region P, a switching transistor (not shown) positioned at each intersection of the gate wiring and the data wiring, and the switching transistor; The driving transistor Td is connected one to one with one side spaced apart.

An interlayer insulating layer may include a passivation layer 155 formed on the switching transistor and the driving transistor Td, and a plurality of groove patterns GP partitioned by pixel regions P on the passivation layer 155. Form 165. In this case, the passivation layer 155 and the interlayer insulating layer 165 include a drain contact hole DCH exposing the drain electrode 134 of the driving transistor Td.

The plurality of groove patterns GP is a pattern of the exposed surface of the interlayer insulating layer 165 for each pixel region P, and the width w and the depth t may be changed in various shapes. That is, the plurality of groove patterns GP may be designed and changed in various forms, such as a checkerboard shape and a red cross shape, in a plan view. In particular, the depth t of the plurality of groove patterns GP may be formed as deep as possible so as not to expose the devices under the interlayer insulating layer 165.

In this case, the passivation layer 155 and the interlayer insulating layer 165 may include an inorganic insulating material group including silicon oxide (SiO ₂ ) and silicon nitride (SiNx), or benzocyclubutene and photo acryl. Each of the selected organic insulating material group may be formed of one.

In particular, the protective layer 155 is a deposition process using a plasma chemical vapor deposition equipment selected one of the inorganic insulating material group, the interlayer insulating film 165 is a coating process using a spin coating equipment selected one of the organic insulating material group. It is preferable to form.

The connection electrode 170 may be formed as a double layer in which the first layer 170a and the second layer 170b are sequentially stacked. The first layer 170a is a group of transparent conductive materials including indium tin oxide (ITO) and indium zinc oxide (IZO), and the second layer 170b is a group of conductive materials including molybdenum or molybdenum alloy. Each can be selected from.

The driving transistor Td includes a gate electrode 125, a gate insulating layer 145, a semiconductor layer 140, and source and drain electrodes 132 and 134. The semiconductor layer 140 may be formed of a single layer made of crystalline silicon (p-Si). In addition, the semiconductor layer 140 may be formed of a double layer in which an active layer made of pure amorphous silicon (a-Si: H) and an ohmic contact layer made of amorphous silicon (n + a-Si: H) containing impurities are sequentially stacked. Can be.

Meanwhile, the auxiliary electrode 160 is formed on a lower surface of the second substrate 110 at a position corresponding to the data line of the first substrate 105. The first electrode 180 is formed on the lower front surface of the auxiliary electrode 160, and the buffer pattern 162 covering the auxiliary electrode 160 for each pixel area P is formed below the first electrode 180. Form.

In addition, the bottom surface overlapping the buffer pattern 162 forms a partition wall 164 having an inverse taper structure. On one side spaced apart from the partition wall 164, the patterned spacer 150 corresponding to the pixel area P is formed one to one. Each pixel region P divided by the barrier rib 164 is formed with an organic emission layer 182 in contact with the first electrode 180, and a second electrode 184 in contact with the lower portion of the organic emission layer 182. ) In turn.

At this time, the organic light emitting layer 182 and the second electrode 184 formed in the pixel region P are separated from the neighboring pixel region P by the partition wall 164 formed in the reverse taper shape, and the patterned spacer 150 is formed. It is formed covering the side and the bottom surface.

The auxiliary electrode 160 is selected from the group of conductive materials including molybdenum and molybdenum alloys, and the first electrode 180 has a work function such as indium tin oxide (ITO) and indium zinc oxide (IZO). Are each formed of one selected from the group of relatively high transparent conductive materials.

In this case, the auxiliary electrode 160 is formed to lower the resistance value of the first electrode 180 made of a material having a relatively high resistance, and may be omitted if necessary. The patterned spacer 150 positioned on the bottom surface in contact with the buffer pattern 162 connects the connection electrode 170 of the first substrate 105 and the second electrode 184 of the second substrate 110. It plays a role.

Although not shown in detail in the drawings, the second electrode 184 may be formed of a triple layer structure, in which the first layer is made of aluminum (Al) or aluminum alloy (AlNd), and the second layer is made of silver (Ag). The third layer may be made of calcium (Ca), respectively. In this case, the first layer is disposed such that the organic light emitting layer 182 and the third layer are in contact with the connection electrode 170, respectively. The first electrode 180, the organic emission layer 182, and the second electrode 184 may be referred to as an organic light emitting diode (E).

In addition, a hole transporting layer and a hole injection layer may be disposed between the organic light emitting layer 182 and the first electrode 180 serving as an anode electrode, and the organic light emitting layer 182 and the cathode electrode. An electron injection layer and an electron transporting layer may be further formed between the second electrodes 184 which serve as a channel.

The organic light emitting layer 182 is designed to be made of an organic material that emits red (R), green (G), and blue (B) for each pixel area P to implement full color.

As the space between the first substrate 105 and the second substrate 110 described above, the internal fillers correspond to the internal spaces of the plurality of groove patterns GP for each pixel region P divided by the partition wall 164. 192). In this case, the plurality of groove patterns GP may be formed by patterning an exposed surface of the interlayer insulating layer 165, and an internal space having a predetermined depth t may be secured from the surface of the interlayer insulating layer 165. . That is, when the internal filler 192 is interposed in correspondence with the internal space, there is an advantage that the pixel region P may be partitioned.

The internal filler 192 functions as a buffer to improve the durability of the panel 130 while maintaining a constant cell gap between the first and second substrates 105 and 110.

As such, the plurality of groove patterns GP partitioned by the pixel regions P may serve to prevent the internal filler 192 injected into the liquid phase from flowing to the side and top surfaces of the patterned spacer 150.

Therefore, the patterned spacer 150 is positioned in the internal filler 192 filled in the space between the first and second substrates 105 and 110 by the plurality of groove patterns GP partitioned by pixel region P. FIG. It can be prevented to flow into the portion to cause a poor contact of the connection electrode 170 and the second electrode 184.

In particular, the present invention is characterized in that the internal filler 192 is selectively filled to correspond to the plurality of groove patterns GP partitioned for each pixel region P by using the Valk injection method. Such a balk injection method corresponds to a non-impact type by printing by spraying a liquid material. Therefore, it is possible to fill the internal filler 192 so as to correspond to the plurality of groove patterns GP positioned for each pixel region P. FIG.

In particular, during the bonding process between the first and second substrates 105 and 110, the internal filler 192, which is not the patterned spacer 150, functions to maintain the gap in the display area AA. Accordingly, the inner filler 192 simultaneously functions as a buffer to prevent damage to the patterned spacer 150. As the liquid material used as the internal filler 192, a thermosetting resin or an ultraviolet curable resin may be used. As the thermosetting resin, an epoxy-based sealant may be used.

In addition, the first substrate 105 and the second substrate 110 are coated with a sealant made of a thermosetting resin and an ultraviolet curable resin along the edge of the non-display area NAA, and the seal pattern 190 is formed by curing the sealant 190. Are opposed to each other.

The characteristic feature of the above-described configuration is that the durability of the panel can be improved by filling the liquid internal filler to correspond to the plurality of groove patterns for each pixel region except for the portion where the patterned spacer is formed.

In addition, the introduction of the internal filler has a structural advantage to more effectively shield the moisture, oxygen, etc. flowing from the outside, through which can improve the device reliability and life, and further lower the production yield due to contact failure You can solve the problem.

Hereinafter, a method of manufacturing a dual plate type organic light emitting diode according to the present invention will be described with reference to the accompanying drawings.

4A to 4G are cross-sectional views sequentially illustrating a method of manufacturing a dual plate type organic light emitting diode according to the present invention, in order of process.

4A is a cross-sectional view illustrating a step of forming an array device on a first substrate.

As shown in FIG. 4A, a pixel region P and a driving region in which a driving transistor is to be formed and a pixel region P defined by vertical crossings of a gate wiring (not shown) and a data wiring (not shown) are formed on the first substrate 105. Proceed to the step of defining). On the first substrate 105 in which the pixel region P and the driving region Dr are defined, a plurality of switching transistors (eg, one-to-one) corresponding to the intersections of the gate lines and the data lines perpendicular to each other and the intersection points of the gates and the data lines (not shown) C). One side spaced apart from the plurality of switching transistors forms a plurality of driving transistors Td individually connected to the plurality of switching transistors.

Next, the passivation layer 155 and the interlayer insulating layer 165 are sequentially stacked on the upper surfaces of the plurality of switching transistors and the plurality of driving transistors Td. The protective layer 155 and the interlayer insulating layer 165 may include an inorganic insulating material group including silicon oxide (SiO ₂ ) and silicon nitride (SiNx), or benzocyclubutene and photo acryl. Each selected from the group of organic insulating materials may be formed.

In particular, the protective layer 155 is a deposition process using a plasma chemical vapor deposition equipment selected one of the inorganic insulating material group, the interlayer insulating film 165 is a coating process using a spin coating equipment selected one of the organic insulating material group. It is preferable to form.

Next, a process of aligning the mask M including the transmission part T1 and the blocking part T2 is spaced apart from the first substrate 105 on which the passivation layer 155 and the interlayer insulating layer 165 are formed. . Assuming that the interlayer insulating layer 165 is formed of an organic material having positive characteristics, the blocking portion T2 of the mask M completely blocks light, and the transmitting portion T1 transmits light. A chemical exposure of the interlayer insulating film 165 exposed to light serves to completely expose the light. In this case, in the mask M, the transmissive part T1 is positioned corresponding to one side of the driving region Dr, and the plurality of transmissive parts T1 and the blocking part T2 are alternately disposed for each pixel area P. Except for this, all areas are designed such that the blocking unit T2 is located.

As shown in FIG. 4B, when the exposure and development processes are performed in the direction of the first substrate 105 above the mask (M in FIG. 4A), a predetermined width is formed on one side of the driving region Dr. a plurality of groove patterns GP patterned with a predetermined width w and a predetermined depth t for each pixel region P, respectively, and the first contact hole CH1 having a pattern of w and a predetermined depth t is formed. Is formed. In this case, the plurality of groove patterns GP may be designed and changed in various forms such as a checkerboard shape and a red cross shape in a plan view.

In the process of forming the plurality of groove patterns GP, the width w and the depth t of the switching transistor and the driving transistor Td may be wide and deep as much as possible without being exposed to the outside. In this case, the plurality of groove patterns GP are not limited to the formation positions of the plurality of groove patterns GP except for portions overlapping the connection electrodes 170 of FIG. 3 to be formed for each pixel region P through a subsequent process. Therefore, in the space overlapping with the gate and data lines or in the space between the inner non-display area NAA of the seal pattern 190 of FIG. 3 and the outermost pixel area P closest to the non-display area NAA. It is also possible to form a plurality of groove patterns GP.

The above-described process shows an example in which the interlayer insulating layer 165 is formed of one selected from the group of organic insulating materials. A process of applying a resist to form a photosensitive layer may be added.

As shown in FIG. 4C, the interlayer insulating film 165 corresponding to the first contact hole CH1 and the passivation film 155 disposed under the interlayer insulating film 165 are sequentially patterned to drive the transistor Td. The second contact hole CH2 exposing the drain electrode 134 is formed. In this case, the first contact hole CH1 and the second contact hole CH2 may be referred to as a drain contact hole DCH.

Although not shown in the drawing, the drain electrode 134 of the driving transistor Td is formed after forming the plurality of groove patterns GP without distinguishing the steps of forming the first contact hole CH1 and the second contact hole CH2. The drain contact hole DCH may be formed by collectively patterning the interlayer insulating layer 165 and the passivation layer 155 corresponding thereto.

Next, an upper portion of the interlayer insulating layer 165 is connected one-to-one with the driving transistor Td for each pixel region P through the drain contact holes DCH including the first and second contact holes CH1 and CH2. An electrode 170 is formed. The connection electrode 170 may be formed as a double layer in which the first layer 170a and the second layer 170b are sequentially stacked.

At this time, the first layer 170a is a transparent conductive material group including indium tin oxide (ITO) and indium zinc oxide (IZO), and the second layer 170b is formed of molybdenum (Mo) or Each may be selected from the group of conductive materials including molybdenum alloy (MoNd).

4D to 4G are cross-sectional views sequentially illustrating the steps of forming an organic light emitting diode on a second substrate in a process sequence.

As shown in FIG. 4D, one selected from the group of conductive materials including molybdenum and molybdenum alloy is deposited on the second substrate 110 and patterned to form the auxiliary electrode 160. The auxiliary electrode 160 may be formed at a position corresponding to the data line of the first substrate 105 of FIG. 4C.

Depositing one selected from a group of transparent conductive materials including indium tin oxide (ITO) and indium zinc oxide (IZO) on the upper surface of the second substrate 110 on which the auxiliary electrode 160 is formed; One electrode 180 is formed. A plurality of buffer patterns 162 respectively covering the auxiliary electrodes 160 are formed on the second substrate 110 on which the first electrodes 180 are formed.

Next, a patterned spacer 150 corresponding to each pixel area (P of FIG. 4C) is formed on one side spaced apart from the plurality of buffer patterns 162, and the upper portion overlapping the plurality of buffer patterns 162. The furnace forms a partition 164 whose cross section has an inverse taper shape. At this time, the partition wall 164 may be formed first.

As shown in FIG. 4E, the organic light emitting layer 182 that contacts the first electrode 180 is formed for each pixel region divided by the partition wall 164. The organic light emitting layer 182 may be formed by sequentially forming organic materials emitting red, green, and blue colors for each pixel region separated by the partition wall 164.

Next, a second electrode 184 connected to the organic emission layer 182 is formed for each pixel area of the second substrate 110 on which the organic emission layer 182 is formed. The second electrode 184 may be selected from a group of relatively low work function metal materials such as calcium (Ca), magnesium (Mg), and aluminum (Al). The first electrode 180, the organic emission layer 182, and the second electrode 184 may be referred to as an organic light emitting diode (E).

4F to 4G are cross-sectional views illustrating a process of bonding the first and second substrates together.

As shown in FIG. 4F, the printing of the first sealant 190a is performed using a dispenser (not shown) along the edge of the non-display area NAA on the first substrate 105. In this case, the process of printing the first sealant 190a on the second substrate 110 may be performed. However, since the bonding process is performed while the second substrate is rotated 180 degrees, the first substrate ( Printing to 105).

Next, the step of aligning the Balk injection device to the upper spaced apart from the first substrate 105, the first sealant 190a is printed. The balk injection device 195 may include a supply pipe 195a receiving a second sealant 192a from a storage tank (not shown), and a syringe for temporarily storing a second sealant 192a from the supply pipe 195a. 195b and a nozzle 195c for ejecting the second sealant 192a from the syringe 195b in an appropriate amount.

Next, a step of selectively dropping the second sealant 192a onto the plurality of groove patterns GP positioned in each pixel region P using the flake injection device 195 is performed. At this time, during the dropping step of the second sealant 192a using the bark injection device 195, a scan method that sequentially prints in a direction parallel to the first to nth gate lines may be applied. In particular, the second sealant 192a should be printed for each pixel region P except for an area corresponding to the patterned spacer 150 of FIG. 4E. At this time, in the printing method using the balk injection device 195, the viscosity of the second sealant 192a is preferably selected in the range of 100,000 to 150,000 cps.

As shown in FIG. 4G, a second substrate having an organic light emitting diode E or the like formed on an upper portion of the first substrate 105 on which the first and second sealants 190a and 192a of FIG. 4F are formed. Proceed to position 110).

Next, when the alignment between the first substrate 105 and the second substrate 110 is completed, the second substrate 110 is dropped and contacted with the first substrate 105. In the contacting step of the first and second substrates 105 and 110, the formation range of the second sealant may be extended by the contact between the first and second substrates 105 and 110. Since a plurality of groove patterns GP are formed for each pixel area P, the second sealant may be prevented from flowing into the patterned spacer 150 by the plurality of groove patterns GP. Therefore, the second sealant can be maintained without a large change in shape of the dropping step by the plurality of groove patterns GP.

That is, the plurality of groove patterns GP functions to partition the second sealant for each pixel area P except for the patterned spacer 150, and thus the second pattern is formed as a portion where the patterned spacer 150 is located. The problem that the sealant flows in and causes a poor contact between the connection electrode 170 and the second electrode 184 can be prevented. In this case, the liquid material used as the second sealant may be selected from a thermosetting resin and an ultraviolet curable resin, and it is particularly preferable to use a thermosetting resin.

Next, when the first and second sealants are cured by a thermosetting or ultraviolet curing process, the seal pattern joining the first substrate 105 and the second substrate 110 along the edge of the non-display area NAA. 190 is formed. In the display area AA, an internal filler 192 partitioned by a plurality of groove patterns GP is formed for each pixel area P except for the patterned spacer 150.

Accordingly, in the present invention, the durability of the panel 130 may be improved by interposing the internal filler 192 for each pixel region P except for the patterned spacer 150. There is an effect that can prevent the dark spot defect due to damage or loss of the patterned spacer 150 in advance.

In addition, it is possible to improve the device reliability and life as a structural advantage that can more effectively shield the moisture, oxygen, etc. flowing from the outside.

As described above, the organic light emitting device of the dual plate type according to the present invention can be manufactured.

However, the present invention is not limited to the above embodiments, and it will be apparent that various modifications and changes can be made without departing from the spirit and the spirit of the present invention.

1 is a circuit diagram of a unit pixel of a conventional active matrix type organic light emitting display device.

Figure 2 is a schematic cross-sectional view of a conventional dual plate type organic light emitting device.

3 is a cross-sectional view showing an organic light emitting device of a dual plate type according to the present invention.

4A to 4G are cross-sectional views sequentially illustrating a method of manufacturing a dual plate type organic light emitting device according to the present invention, in order of process.

* Explanation of symbols for the main parts of the drawings *

105: first substrate 110: second substrate

145 gate insulating film 150 patterned spacer

155: protective film 160: auxiliary electrode

165: interlayer insulating film 162: buffer pattern

164: bulkhead 170: connecting electrode

190: seal pattern 192: internal filler

GP: Groove Pattern Td: Driving Transistor

E: organic light emitting diode

Claims (13)

A first substrate and a second substrate, each of which is divided into a display area and a non-display area; Gate wirings and data wirings defining a pixel area perpendicularly crossing the first substrate; A switching transistor formed at each intersection point of the gate wiring and data wiring, and a driving transistor connected one-to-one with the switching transistor; An interlayer insulating layer covering an upper portion of the switching and driving transistor, the drain contact hole exposing the drain electrode of the driving transistor, and having a plurality of groove patterns formed in each pixel region except the drain contact hole; A connection electrode connected to the drain electrode of the driving transistor on the interlayer insulating layer; A first electrode formed on the lower front surface of the second substrate; A buffer pattern covering the auxiliary electrode under the first electrode; A partition wall formed in an inverse taper shape in a lower portion overlapping the buffer pattern; A patterned spacer positioned at each pixel area toward one side spaced apart from the partition wall; An organic emission layer and a second electrode sequentially connected to the first electrode for each pixel area divided by the barrier rib; An internal filler interposed by each pixel region except for an area corresponding to the patterned spacer by a seal pattern for bonding the first and second substrates along the non-display area; Dual plate type organic light emitting device comprising a. The method of claim 1, And a protective film is formed between the switching and driving transistor and the interlayer insulating film. The method of claim 1, The protective film is an inorganic insulating material group including silicon oxide and silicon nitride, wherein the interlayer insulating film is formed of one selected from the group of organic insulating materials including benzocyclobutene and photoacryl. . The method of claim 1, The plurality of groove patterns are formed by patterning the interlayer insulating film. The method of claim 1, The plurality of groove patterns are formed in any one selected from a checkerboard shape, a red cross shape in a planar organic light emitting device of a dual plate type. The method of claim 1, The plurality of groove patterns are selected from a design range of a depth that does not expose the switching and driving transistor to the outside from the exposed surface of the dual plate type organic light emitting device. Forming gate wirings and data wirings on the first substrate to vertically intersect to define pixel regions; Forming a switching transistor and a driving transistor connected to the switching transistor one-to-one at each intersection point of the gate wiring and the data wiring; Forming an interlayer insulating layer covering an upper portion of the switching and driving transistor and including a drain contact hole exposing a drain electrode of the driving transistor and a plurality of groove patterns for each pixel region excluding the drain contact hole; Forming a connection electrode connected to the drain electrode of the driving transistor on the interlayer insulating layer; Forming a first electrode on a lower front surface of the second substrate; Forming a buffer pattern covering the auxiliary electrode under the first electrode; Forming a patterned spacer and a barrier under the overlapping buffer pattern; Forming an organic emission layer and a second electrode connected to the first electrode for each pixel area separated from the barrier rib; Applying a first sealant along an edge of the non-display area of the first substrate, and dropping a second sealant for each pixel area except for an area corresponding to the patterned spacer; Hardening the first and second sealants to form a seal pattern and an internal filler; Method of manufacturing a dual-plate organic electroluminescent device comprising a. The method of claim 7, wherein And a protective film is formed between the switching and driving transistor and the interlayer insulating film. The method of claim 7, wherein The protective film is an inorganic insulating material group including silicon oxide and silicon nitride, wherein the interlayer insulating film is formed of one selected from the group of organic insulating materials including benzocyclobutene and photoacryl. Manufacturing method. The method of claim 7, wherein The plurality of groove patterns are formed by patterning the interlayer insulating film. The method of claim 7, wherein And a plurality of groove patterns are formed in one of a checkerboard shape and a red cross shape in plan view. The method of claim 7, wherein The second sealant is a method of manufacturing an organic light emitting device of a dual plate type, characterized in that formed in the dropping method using the injection device. The method of claim 7, wherein And the plurality of groove patterns are selected from a design range having a depth that does not expose the switching and driving transistor to the outside from the exposed surface thereof.

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