JP2019091072A - Electro-optical device and electronic apparatus - Google Patents

Abstract

To cause an electro-optical device to be hardly subjected to an influence of noise due to potential variation of data lines, and to control currents flowing through light-emitting elements.SOLUTION: An electro-optical device includes: a scanning line 112 provided in a first direction; a first interlayer dielectric film provided so as to cover the scanning line 112; a third interlayer dielectric film provided so as to cover the first interlayer dielectric film; data lines 114 provided above the third interlayer dielectric film; pixel circuits provided corresponding to intersections among the scanning line 112 and the data lines 114; and shield wiring 81a and 81b. The pixel circuits comprise light-emitting elements and transistors 140 controlling currents flowing through the light-emitting elements. The shield wiring 81a or 81b is provided between the first interlayer dielectric film and the third interlayer dielectric film and, as viewed in a plan view, is provided among the data lines 114 and the transistors 140.SELECTED DRAWING: Figure 10

Description

  The present invention relates to an electro-optical device and an electronic apparatus.

  In recent years, various types of electro-optical devices using light emitting elements such as organic light emitting diodes (hereinafter referred to as “OLED”) have been proposed. In such an electro-optical device, pixel circuits are provided corresponding to the intersections of scanning lines and data lines. The pixel circuit generally has a configuration including the light emitting element, a switching transistor, and a driving transistor (see Patent Document 1). Here, the switching transistor is turned on in the selection period of the scanning line between the data line and the gate of the driving transistor, whereby the potential supplied to the data line is held in the gate. Then, the driving transistor is configured to flow a current corresponding to the holding potential of the gate to the light emitting element.

JP, 2007-310311, A

By the way, in applications where a reduction in display size and a high definition of display are required, the degree of capacitive coupling becomes high as the data line and the drive transistor approach each other. For this reason, when the potential of the data line fluctuates, the fluctuation of the potential propagates as a kind of noise to each part of the drive transistor, particularly the gate, through the parasitic capacitance, and the held potential of the gate is fluctuated. Therefore, it has been pointed out that the display quality is degraded since the target current can not flow to the light emitting element.
The present invention has been made in view of the above-described problems, and one of the objects thereof is to prevent deterioration in display quality due to noise caused by potential fluctuation of data lines.

  In order to solve the above problems, in the electro-optical device according to the present invention, a scanning line provided along a first direction, and a first insulating film provided so as to cover the scanning line. A second insulating film provided to cover the first insulating film, a data line provided above the second insulating film along a second direction different from the first direction, and the scan A pixel circuit provided corresponding to the intersection of a line and the data line, and a shield wiring, wherein the pixel circuit includes a light emitting element, and a first transistor that controls a current flowing to the light emitting element. And a part of the shield wiring is provided between the first insulating film and the second insulating film and between the data line and the first transistor in plan view. It is characterized by

In the present invention, the distance between the shield wire and the data line is preferably shorter than the distance between the shield wire and the first transistor.
Further, in the present invention, it is preferable that the power supply line is further provided, the first transistor is connected between the power supply line and the light emitting element, and the shield wiring is connected to the power supply line. In such a configuration, the power supply line may be provided between the first insulating film and the second insulating film.
A second transistor for connecting a second transistor whose conduction state is controlled according to a scanning signal supplied to the scanning line, a first relay electrode connected to the second transistor, the first relay electrode, and the data line It may further include two relay electrodes, or a first connection portion connecting the first relay electrode and the second relay electrode, and a second connection portion connecting the data line and the second relay electrode. And the first connection portion may overlap with the second connection portion in plan view.

Further, the above object is to provide a scanning line provided along a first direction, a first insulating film provided to cover the scanning line, and a second provided to cover the first insulating film. An insulating film, a first data line provided above the second insulating film along a second direction different from the first direction, and a second insulating film along the second direction Corresponds to the second data line provided above, the first pixel circuit provided corresponding to the intersection of the scanning line and the first data line, and the intersection of the scanning line and the second data line And the first pixel circuit includes a first light emitting element, and a first transistor for controlling a current flowing to the first light emitting element, and the second pixel circuit includes: The pixel circuit includes: a second light emitting element; and a second transistor that controls a current flowing to the second light emitting element. The shield wiring has a first shield wiring and a second shield wiring, and a part of the first shield wiring is between the first insulating film and the second insulating film. When viewed in plan, it is provided between the first transistor and the first data line, and a part of the second shield wiring is between the first insulating film and the second insulating film. This can also be achieved by the configuration provided between the second transistor and the first data line when viewed in plan.
Here, the distance between the first shield wire and the first data line is shorter than the distance between the first shield wire and the first transistor, and the distance between the second shield wire and the first data line May be shorter than the distance between the second shield wire and the second transistor.
In addition, the semiconductor device may further include a storage capacitor having one end connected to the gate of the first transistor, and the shield wiring may be provided to cover the storage capacitor in plan view, and the shield wiring is a flat surface. It may be provided to cover the first transistor when viewed.
The electro-optical device according to the present invention is applicable to various electronic devices. Typically, the display device is a display device, and examples of the electronic device include a personal computer and a mobile phone. In particular, according to the present invention, even when the storage capacitance can not be sufficiently ensured, noise from the data line is absorbed by the shield wiring before reaching the driving transistor of the pixel circuit, thereby preventing the deterioration of the display quality. Therefore, it is suitable for, for example, a display device for forming a reduced image, such as for a head mount display or a projector. However, the application of the electro-optical device according to the present invention is not limited to the display device. For example, the present invention is also applicable to an exposure apparatus (optical head) for forming a latent image on an image carrier such as a photosensitive drum by irradiation of a light beam.

FIG. 1 is a block diagram showing the configuration of an electro-optical device according to a first embodiment. FIG. 2 is a diagram showing an equivalent circuit of a pixel circuit in an electro-optical device. FIG. 7 is a diagram showing a display operation of the electro-optical device. It is a top view which shows the structure of a pixel circuit. It is a fragmentary sectional view which shows the structure fractured | ruptured by the Ee line | wire in FIG. It is a figure which shows the noise absorption from the data line in a pixel circuit. It is a figure which shows various parasitic capacitances in a pixel circuit. It is the figure which modeled various parasitic capacitance in a pixel circuit. It is a figure which shows an example of crosstalk. FIG. 7 is a plan view showing a configuration of a pixel circuit of an electro-optical device according to a second embodiment. It is a fragmentary sectional view which shows the structure fractured | ruptured by the Ff line | wire in FIG. FIG. 10 is a plan view showing the configuration of a pixel circuit of an electro-optical device according to a third embodiment. It is a fragmentary sectional view which shows the structure broken by the Hh line | wire in FIG. It is a top view which shows the structure of the pixel circuit of the electro-optical device which concerns on 4th Embodiment. It is a top view which shows the structure of the pixel circuit of the electro-optical device which concerns on 5th Embodiment. It is a top view which shows the structure of the pixel circuit of the electro-optical device concerning 6th Embodiment. FIG. 17 is a partial cross-sectional view showing a configuration broken at a line Jj in FIG. 16; It is a top view which shows the structure of the pixel circuit of the electro-optical device concerning 7th Embodiment. It is a figure which shows the equivalent circuit of the pixel circuit which concerns on another example. It is a figure which shows the electronic device (the 1) which applied the electro-optical apparatus. It is a figure which shows the electronic device (the 2) which applied the electro-optical apparatus. It is a figure which shows the electronic device (the 3) which applied the electro-optical apparatus.

First Embodiment
FIG. 1 is a block diagram showing the configuration of the electro-optical device according to the first embodiment of the present invention. The electro-optical device 1 displays an image by a plurality of pixel circuits 110.
As shown in this figure, the electro-optical device 1 is configured to include an element unit 100, a scanning line drive circuit 210, and a data line drive circuit 220.
Among them, in the element unit 100, m scanning lines 112 are provided along the row (X) direction in the drawing, and n columns of data lines 114 are along the column (Y) direction, and each scanning is performed. The wires 112 are provided so as to be electrically isolated from one another. The pixel circuits 110 are respectively arranged corresponding to the intersections of the m rows of scanning lines 112 and the n columns of data lines 114. Therefore, in the present embodiment, the pixel circuits 110 are arranged in a matrix of m rows × n columns. Both m and n are natural numbers.

A power supply line 116 is connected in common to each pixel circuit 110 to supply a potential Vel on the high potential side of the element power supply. Although not shown in FIG. 1, a common electrode is provided over each pixel circuit 110 as will be described later, to supply the potential Vct of the low potential side of the element power supply. These potentials Vel and Vct are generated by a power supply circuit (not shown).
In addition, in order to distinguish the scanning lines 112 and the rows of the pixel circuits 110 for convenience, in FIG. 1 there may be cases called as one row, two rows, three rows, ..., (m-1) rows, m rows from the top sequentially is there. Similarly, in order to distinguish the columns of the data lines 114 and the pixel circuits 110 for convenience, in FIG. 1 there may be cases called as one column, two columns, three columns,..., (N-1) columns, n columns sequentially from the left is there.

In the electro-optical device 1, the scanning line driving circuit 210 and the data line driving circuit 220 are arranged around the area where the pixel circuits 110 are arranged in a matrix. The operations of the scanning line drive circuit 210 and the data line drive circuit 220 are controlled by a controller (not shown). Further, to the data line drive circuit 220, gradation data specifying the gradation (brightness) to be expressed by each pixel circuit 110 is supplied from the controller.
The scanning line drive circuit 210 sequentially selects the 1st to m-th rows in each frame. As an example, the scanning line drive circuit 210 transmits the scanning signals Gwr (1), Gwr (2), Gwr (3), to the scanning lines 112 in the 1, 2, 3,. Gwr (m-1) and Gwr (m) are supplied to sequentially and exclusively set the scanning signals to H level in a frame. In the present description, a frame refers to a period required to display an image for one cut (frame) on the electro-optical device 1, and if the vertical scanning frequency is 60 Hz, 16.67 for one period. It refers to the period of milliseconds.

  The data line drive circuit 220 supplies, via the data line 114, a data signal of a potential corresponding to the gradation data of the pixel circuit 110 to the pixel circuit 110 located in the row selected by the scan line drive circuit 210. It is For convenience, the data signals supplied to the data lines 114 of the first, second, third,..., (N−1) th and nth columns are represented by Vd (1), Vd (2), Vd (3),. , Vd (n-1) and Vd (n).

  Next, an equivalent circuit of the pixel circuit 110 will be described with reference to FIG. Note that in FIG. 2, the i-th row and the (i + 1) -th row adjacent to the i-th row below and the j-th column and the j-th row are adjacent to the right (j + 1) A pixel circuit 110 for a total of 4 pixels of 2 × 2 corresponding to the intersection with the data line 114 of the column is shown. Here, i and (i + 1) are symbols in the case where the rows arranged by the pixel circuits 110 are generally indicated, and are integers of 1 or more and m or less. Similarly, j and (j + 1) are symbols in the case where the columns arranged by the pixel circuits 110 are generally indicated, and are integers of 1 or more and n or less.

As shown in FIG. 2, each pixel circuit 110 includes N-channel transistors 130 and 140, a storage capacitor 135, and a light emitting element 150. The respective pixel circuits 110 have the same configuration, and therefore, will be representatively described as one located at i row j column. In the pixel circuit 110 in the i-th row and j-th column, the transistor 130 functions as a switching transistor, and its gate node is connected to the scan line 112 in the i-th row, while its drain node is the data line in the j-th column The source node is connected to one end of the storage capacitor 135 and the gate node of the transistor 140.
The other end of the storage capacitor 135 is connected to the source node of the transistor 140 and the anode of the light emitting element 150. On the other hand, the drain node of the transistor 140 is connected to the power supply line 116.

For convenience, in the pixel circuit 110 in the i-th row and j-th column, the drain node of the transistor 130 is represented by a capital D, and the gate node of the transistor 140 (the source node of the transistor 130 and one end of the storage capacitor 135) is represented by a small letter g. It is written. In particular, the gate node of the transistor 140 in the i-th row and the j-th column is denoted as g (i, j).
In addition, the drain node (power supply line 116) of the transistor 140 is denoted by a small letter d, and the source node of the transistor 140 (the anode of the light emitting element 150) is denoted by a small letter s.

The cathode of the light emitting element 150 is connected to the common electrode 118 across each pixel circuit 100. The common electrode 118 is common to the light emitting elements 150 of each pixel circuit 110. The light emitting element 150 is an OLED in which a light emitting layer made of an organic EL material is held between an anode and a cathode facing each other, and emits light with luminance according to the current flowing from the anode to the cathode.
Note that in FIG. 2, Gwr (i) and Gwr (i + 1) indicate scanning signals supplied to the i and (i + 1) th row scanning lines 112, respectively. Further, Vd (j) and Vd (j + 1) indicate data signals supplied to the data line 114 in the j-th and (j + 1) -th columns, respectively.
Further, in the present embodiment, a shield wire is provided in the vicinity of the data line 114, but the details of the shield wire will be described later.

Next, the display operation of the electro-optical device 1 will be briefly described with reference to FIG. FIG. 3 is a diagram showing an example of the waveforms of the scanning signal and the data signal.
As shown in this figure, the scanning signals Gwr (1), Gwr (2), Gwr (3),..., Gwr (m-1), Gwr (m) are horizontal by the scanning line drive circuit 210 over each frame. It becomes H level sequentially exclusively every scanning period (H).
Here, when the scanning line 112 in the i-th row is selected and the scanning signal Gwr (i) becomes H level, the gray-scale data of the pixel circuit 110 in the i-th row and j-th column The data line drive circuit 220 supplies a data signal Vd (j) having a potential corresponding to the voltage.

  When the scanning signal Gwr (i) becomes H level in the pixel circuit 110 in the i-th row and j-th column, the transistor 130 is turned on, so the gate node g (i, j) is electrically connected to the data line 114 in the j-th column. It will be Therefore, the potential of the gate node g (i, j) becomes the potential of the data signal Vd (j), as indicated by the upper arrow in FIG. At this time, the transistor 140 flows a current corresponding to the potential of the gate node g (i, j) to the light emitting element 150, and the storage capacitor 135 holds the voltage between the gate and the source in the transistor 140 at this time. When the selection of the scan line 112 in the i-th row is finished and the scan signal Gwr (i) becomes L level, the transistor 130 is turned off.

  Even when the transistor 130 is switched from on to off, the voltage between the gate and the source of the transistor 140 when the transistor 130 is on is held by the holding capacitor 135. Therefore, even if the transistor 130 is turned off, the transistor 140 continues to flow the current corresponding to the holding voltage of the holding capacitor 135 to the light emitting element 150 until the scanning line 112 in the i-th row is selected again next time. For this reason, the light emitting element 150 in the pixel circuit 110 in the i-th row and the j-th column has luminance according to the potential of the data signal Vd (j) when the i-th row is selected, that is, With the corresponding brightness, the light continues to be emitted for a period corresponding to one frame.

In the i-th row, the pixel circuits 110 other than the j-th column also emit light with luminance according to the potential of the data signal supplied to the corresponding data line 114. Further, although the pixel circuit 110 corresponding to the scan line 112 in the i-th row is described here, the scan line 112 is selected in the order of 1, 2, 3,..., (M-1), m-th row As a result, each of the pixel circuits 110 emits light at luminance according to the gradation data. Such an operation is repeated for each frame.
Further, in FIG. 3, the potential scales of the data signal Vd (j) and the gate node g (i, j) are expanded for convenience as compared with the potential scale of the scanning signal.

By the way, since the data signal has a potential corresponding to the gradation data of the pixel located in the selected row, the data line 114 fluctuates momentarily in accordance with the display content. For example, since the data signal Vd (j) as shown in FIG. 3 is supplied to the data line 114 in the j-th column, the potential fluctuates in each horizontal scanning period (H).
When the data line 114 is capacitively coupled to each part of the pixel circuit 110, the potential fluctuation of the data line 114 adversely affects the potential of each part of the pixel circuit 110. In particular, in applications where a reduction in display size or high definition of display is required, for example, in a microdisplay having a display size of less than 1 inch diagonally and having a resolution of 1280 × 720 pixels or more, Since the parasitic capacitance of each part becomes relatively large in comparison, the influence appears notably. In particular, since the potentials of the gate node g and the source node s of the transistor 140 define the current to be supplied to the light emitting element 150, the potential fluctuation of this portion causes generation of display or cross talk to be described later. It becomes a factor to make it fall sharply.
Therefore, in the present embodiment, the pixel circuit 110 is configured as follows to make it less susceptible to the noise caused by the potential fluctuation of the data line.

The structure of the pixel circuit 110 will be described with reference to FIGS. 4 and 5.
FIG. 4 is a plan view showing the configuration of four pixel circuits 110 adjacent to each other in the longitudinal and lateral directions, and FIG. 5 is a partial cross-sectional view taken along line E-e in FIG.
Although FIG. 4 shows the wiring structure when the top emission pixel circuit 110 is viewed in plan from the observation side, the structure formed after the pixel electrode (anode) in the light emitting element 150 for simplification I have omitted my body. In FIG. 5, the structure up to the pixel electrode of the light emitting element 150 is shown, and the subsequent structure is omitted. Moreover, in each of the following drawings, the scales are made different in order to make each layer, each member, each region, etc. a recognizable size.

  First, as shown in FIG. 5, semiconductor layers 130a and 140a in which a polysilicon film is patterned in an island shape are respectively provided on a substrate 2 as a base. The semiconductor layer 130 a constitutes a transistor 130, and the semiconductor layer 140 a constitutes a transistor 140. Here, as shown in FIG. 4 in plan view, the semiconductor layer 130 a is formed in a rectangular shape whose longitudinal direction extends along the scanning line 112 to be formed later. On the other hand, the semiconductor layer 140a is formed in a rectangular shape whose longitudinal direction extends along the data line 114 formed later in plan view.

As shown in FIG. 5, the gate insulating film 10 is provided to cover almost the entire surface of the semiconductor layers 130a and 140b. A gate wiring layer of aluminum, tantalum or the like is provided on the surface of the gate insulating film 10, and the scanning line 112 and the gate electrode layer 21 are provided by patterning the gate wiring layer.
The scanning line 112 extends in the lateral direction in FIG. 4 and has a portion branched downward for each pixel circuit 110, and the branched portion overlaps at the central portion of the semiconductor layer 130a. In the semiconductor layer 130a, a region overlapping the branch portion of the scan line 112 is a channel region 130c (see FIG. 5). Of the semiconductor layer 130a, the left direction in FIG. 5 with respect to the channel region 130c is the drain region 130d, and the right direction is the source region 130s.
On the other hand, the gate electrode layer 21 has a shape in which the upper side, the right side, and the lower side are integrated without having the left side in the square frame, as shown in FIG. Among these, the lower sides overlap at the central portion of the semiconductor layer 140a. In the semiconductor layer 140a, a region overlapping the lower side of the gate electrode layer 21 is a channel region 140c (see FIG. 5). Of the semiconductor layer 140a, the left direction in FIG. 5 is the source region 140s and the right direction is the drain region 140d with respect to the channel region 140c.

In FIG. 5, a first interlayer insulating film 11 is formed to cover the scanning line 112, the gate electrode layer 21, or the gate insulating film 10. A conductive wiring layer is formed on the surface of the first interlayer insulating film 11, and relay electrodes 41, 42, 43 and 44 are respectively formed by patterning the wiring layer.
Among these, the relay electrode 41 is connected to the drain region 130 d through contact holes (vias) 31 that respectively open the first interlayer insulating film 11 and the gate insulating film 10.
In FIG. 4, in portions where different types of wiring layers overlap with each other, portions where “×” marks are added to “□” marks are contact holes.

In FIG. 5, one end of the relay electrode 42 is connected to the source region 130 s through the contact hole 32 which respectively opens the first interlayer insulating film 11 and the gate insulating film 10, while the other end of the relay electrode 42 is It is connected to the gate electrode layer 21 through a contact hole 33 which opens the first interlayer insulating film 11.
The relay electrode 43 is connected to the source region 140 s via contact holes 34 which respectively open the first interlayer insulating film 11 and the gate insulating film 10. Here, the shape of the relay electrode 43 in plan view is a rectangle that covers the upper side of the gate electrode layer 21 as shown in FIG. 4. Therefore, as shown in FIG. 5, the storage capacitor 135 has a configuration in which the first interlayer insulating film 11 is sandwiched between the gate electrode layer 21 and the relay electrode 43.
The relay electrode 44 is connected to the drain region 140 d via the contact holes 35 that respectively open the first interlayer insulating film 11 and the gate insulating film 10.

A second interlayer insulating film 12 is formed to cover the relay electrodes 41, 42, 43, 44 or the first interlayer insulating film 11. A conductive wiring layer is formed on the surface of the second interlayer insulating film 12, and relay electrodes 61 and 62 and a power supply line 116 are respectively formed by patterning the wiring layer.
Among these, the relay electrode 61 is connected to the relay electrode 41 through a contact hole 51 that opens the second interlayer insulating film 12. The relay electrode 62 is also connected to the relay electrode 43 through the contact hole 52 that opens the second interlayer insulating film 12.
The power supply line 116 is connected to the relay electrode 44 through a contact hole 53 that opens the second interlayer insulating film 12. Therefore, the power supply line 116 is connected to the drain region 140 d via the relay electrode 44. The power supply line 116 is formed along the lateral direction in which the scan line 112 extends as shown in FIG. 4 in plan view.
The relay electrodes 41 and 61, the relay electrodes 43 and 62, the relay electrode 44 and the power supply are filled by filling the contact holes 51, 52 and 53 with columnar connection plugs made of high melting point metal such as tungsten. The lines 116 may be connected to each other.

A third interlayer insulating film 13 is formed to cover the relay electrodes 61 and 62 or the second interlayer insulating film 12. A conductive wiring layer is formed on the surface of the third interlayer insulating film 13, and the data line 114, shield wirings 81a and 81b (not shown in FIG. 5), and the relay electrode 82 are formed by patterning the wiring layer. It is done.
Among these, the data line 114 is connected to the relay electrode 61 through the contact hole 71 which opens the third interlayer insulating film 13. Therefore, the data line 114 is connected to the drain region 130 d by following the path of the relay electrode 61 and the relay electrode 41. Here, the data lines 114 are formed along the vertical direction orthogonal to the extending direction of the scanning lines 112 as shown in FIG. 4 in plan view.
The relay electrode 82 is connected to the relay electrode 62 through a contact hole 72 that opens the third interlayer insulating film 13.
Alternatively, the contact holes 71 and 72 may be filled with columnar connection plugs made of high melting point metal to connect the relay electrodes 61 and the data lines 114 with each other and the relay electrodes 62 and 82 with each other.

Each of the shield wires 81a and 81b is formed corresponding to each column as shown in FIG. 4 in plan view.
Specifically, the shield wire 81 a in a certain column is formed along the vertical direction on the right side of the data line 114 so as to be located between the data line 114 in the corresponding column and the transistor 140 in the pixel circuit 110 in the corresponding column. Be done. At this time, the shield wiring 81 a is provided closer to the data line 114 when the data line 114 and the transistor 140 are compared. That is, the distance between the shield wire 81 a and the data line 114 is shorter than the distance between the shield wire 81 a and the transistor 140. For this reason, the shield wiring 81 a is easier to capacitively couple with the data line 114 than the transistor 140.

On the other hand, the shield wiring 81b in a certain column is longitudinally located on the left side of the data line 114 so as to be located between the data line 114 adjacent on the right side with respect to the column and the transistor 140 in the pixel circuit 110 in the corresponding column. It is formed along the At this time, the shield wiring 81 b is provided closer to the data line 114 when the data line 114 and the transistor 140 are compared. That is, the distance between the shield wire 81 b and the data line 114 is shorter than the distance between the shield wire 81 b and the transistor 140. For this reason, the shield wiring 81 b is easier to capacitively couple with the data line 114 than the transistor 140.
When viewed from the top of the transistor 140, it is disposed between the left data line 114 and the right data line 114, but the shield wiring 81a is disposed in front of the left data line 114. The shield wire 81b is disposed in front of the data line 114 of FIG.

The shield wirings 81a and 81b are formed in the vertical direction in FIG. 4 and extend to the outside of the area in which the pixel circuits 110 are arranged, and a temporally constant potential, for example, the potential Vel is applied.
The shield wires 81a and 81b may be connected via contact holes at portions intersecting with the power supply line 116 in plan view for each row or every few rows.

A fourth interlayer insulating film 14 is formed to cover the data line 114, the shield wirings 81a and 81b, the relay electrode 82, or the third interlayer insulating film 13. A conductive and reflective wiring layer is formed on the surface of the fourth interlayer insulating film 14, and the anode of the light emitting element 150 is formed by patterning the wiring layer. The anode is an individual pixel electrode for each pixel circuit 110, and is connected to the relay electrode 82 through the contact hole 92 that opens the fourth interlayer insulating film 14. Therefore, the anode (pixel electrode) is connected to the source region 140s by following the path of the relay electrode 82, the relay electrode 62, and the relay electrode 43 which also serves as the other electrode of the storage capacitor 135.
Alternatively, the contact holes 92 may be filled with columnar connection plugs made of high melting point metal to connect the relay electrodes 82 and the pixel electrodes.

Although the structure after the electro-optical device 1 is not shown, a light emitting layer made of an organic EL material is laminated on the anode for each pixel circuit 110, and a common transparent electrode also serves as a cathode over the pixel circuits 110. It is provided as a common electrode 118. Thus, the light emitting element 150 becomes an OLED in which the light emitting layer is sandwiched between the anode and the cathode facing each other, emits light with luminance according to the current flowing from the anode to the cathode, and is opposite to the substrate 2 It will be observed (top emission structure). In addition to this, a sealing glass or the like for shielding the light emitting layer from the air is provided, but the description is omitted.
Further, in FIG. 4, the illustration of the pixel electrode which is the anode of the light emitting element 150 is omitted, so that only the “□” mark indicating the position is attached to the contact hole 92.

Next, the shield function by the shield wires 81a and 81b will be described with reference to FIG. FIG. 6 is a diagram showing the planar structure of the pixel circuit 110 shown in FIG. 4 replaced with an electrical circuit.
As described above, since the data line 114 in each column fluctuates in potential, noise resulting from the fluctuation in the potential propagates to each part of the pixel circuit 110.
In the first embodiment, the shield wiring 81a is located in front of the gate node g and the source node s of the transistor 140 in the i-th row and the j-th column as viewed from the data line 114 in the j-th column. Therefore, the noise generated from the j-th data line 114 is absorbed by the coupling capacitance Ca between the shield wire 81 a and the j-th data line 114.
Further, the shield wiring 81b is also located in front of the gate node g and the source node s of the transistor 140 in the i-th row and j-th column as viewed from the data line 114 in the (j + 1) th column. For this reason, the noise generated from the data line 114 of the (j + 1) th column is absorbed by the coupling capacitance Cb between the shield wiring 81 b and the data line 114 of the (j + 1) th column.
Therefore, according to the electro-optical device 1, the gate node g and the source node s of the transistor 140 are not easily affected by the noise caused by the potential fluctuation of the data line 114, so that stable display is possible.
Further, in the first embodiment, since the shield wires 81a and 81b are formed by patterning the same wiring layer as the data lines 114 and the relay electrodes 82, an additional process is unnecessary in the manufacturing process.

FIG. 7 is a diagram showing an equivalent circuit of the pixel circuit 110 together with the parasitic capacitance of each part.
In this _{figure, C Dg} indicates a parasitic capacitance generated between the gate node g of the drain node D (data line 114) and the transistor 140 of the transistor _{130, C Ds} is the drain node D and the transistor 140 of the transistor 130 The parasitic capacitance generated between the source node s is shown.
C _HOLD indicates the capacity of the holding capacity 135.
C _gd represents a parasitic capacitance generated between the gate node g and the drain node d (power supply line 116) of the transistor 140, and C _ds is a parasitic capacitance generated between the drain node d and the source node s of the transistor 140 , And C _OLED represents a capacitive component in the light emitting element 150.

In the pixel circuit 110, the transistor 130 is turned off when the corresponding scan line is in a non-selection period. Further, the power supply line 116 and the common electrode 118 have a constant potential.
Therefore, the pixel circuit 110 in the non-selection period can be simplified to a model as shown in FIG. In the drawing, Vamp is the potential amplitude of the data line 114 in the non-selection period.
In this model, the variation ΔVgs given to the holding voltage Vgs of the holding capacitance 135 can be expressed as shown in the equation (1) of FIG. The coefficient K ₁ in the equation (1) is expressed as equation (2), and the coefficient K ₂ is expressed as equation (3).
In the present embodiment, since the shield wirings 81a and 81b are provided, the parasitic capacitances C _Dg and C _Ds are respectively reduced as compared with the configuration in which the shield wirings 81a and 81b are not provided.
Therefore, the component of the term (a) in the equation (2) becomes large, and the whole denominator component becomes large, so the coefficient K ₁ becomes small. On the other hand, since the component of the term (b) in the equation (3) becomes large and the whole denominator component becomes large, the coefficient K ₂ also becomes small.
Therefore, in the present embodiment, the variation ΔVgs with respect to the potential amplitude Vamp is smaller compared to the configuration without the shield interconnections 81a and 81b, so that it is stable against the influence of the potential variation of the data line 114 and noise. It becomes possible to display.

  Here, when the potentials of the gate node g and the source node s fluctuate due to noise caused by the potential fluctuation of the data line 114, specifically, they are manifested in the form of the following crosstalk to improve display quality. Reduce.

FIG. 9 is a view showing an example of crosstalk generated in the electro-optical device having no shield wiring 81a and 81b as in the present embodiment.
As shown in FIG. 9A, in the case of displaying a black rectangular area with gray as a background area as shown in FIG. A dark gradation in which the upper area (a2) and the lower area (c2) with respect to the black area (b2) are different from the other gray areas (a1, a3, b1, b3, c1, c3) Is a phenomenon that will be displayed.
In FIG. 9, the brightness of the area is indicated by the density of oblique lines. Also, this crosstalk occurs even when the area (b2) is white. In any case, since an area which is displayed with different gradations appears in the upper and lower direction of the area (b2), it may be particularly referred to as vertical crosstalk.

  This vertical crosstalk is considered to occur due to the following reasons. That is, in a certain frame, the data line 114 across the area (a1, b1, c1) is constant at the potential corresponding to the gray gradation data over the selection from the first row to the final m-th row. Therefore, the pixel circuits 110 belonging to the area (a1, b1, c1) each hold the potential held at the gate node g by the selection of the scan line corresponding to itself without being affected by the noise from the data line. It will be. The same applies to the data line 114 across the area (a3, b3, c3) and the pixel circuit 110 belonging to the area (a3, b3, c3). For this reason, each of the pixel circuits 110 belonging to the region (a1, a3, b1, b3, c1, c3) emits light with luminance according to the holding potential of the gate node g over the entire period corresponding to one frame. become.

On the other hand, the data line 114 extending over the area (a2, b2, c2) has a potential corresponding to gray scale data during selection of the area (a2), and during selection of the area (b2). The potential drops to the potential corresponding to the gray level data of black, and during the selection of the region (c2), the potential again corresponds to the gray level data of gray.
Therefore, in the pixel circuit 110 belonging to the area (a2), even if the gate node g holds the potential corresponding to gray by the selection of the scanning line corresponding to itself, the data line 114 at the time of selection of the area (b2) It will change by the noise resulting from a potential fluctuation.
Since the data line 114 returns to the potential corresponding to gray again when the region (c2) is selected, there is a possibility that the gate node g may return to the potential corresponding to gray by this return.
However, even if the gate node g returns to a potential corresponding to gray, each of the pixel circuits 110 belonging to the area (a2) selects at least the area (b2) in a period corresponding to one frame after writing. Over time, light is emitted at a luminance corresponding to the potential lowered from the potential corresponding to gray.
The same applies to the area (c2). That is, in the pixel circuit 110 belonging to the area (c2), even if the gate node g holds the potential corresponding to gray by the selection of the scanning line corresponding to itself, the data line is selected when the area (b2) is selected in the next frame. It will be pulled by the potential fluctuation of 114 and will change.
Therefore, each of the pixel circuits 110 belonging to the area (a2, c2) belongs to the other area (a1, a3, b1, b3, c1, c3) when viewed from the average value of the period corresponding to one frame. Unlike each of the circuits 110, it is viewed in dark gradation. It is believed that this is the mechanism by which vertical crosstalk occurs.

According to the first embodiment, each of gate node g and source node s is configured to be less susceptible to noise due to potential fluctuation of data line 114 by shield interconnections 81a and 82. Vertical crosstalk can be suppressed, and high-quality display can be achieved.
In the first embodiment, the shield wires 81a and 81b have the same potential Vel as the power supply line 116, but may have another potential, for example, the potential Vct.

Second Embodiment
In the first embodiment, the shield interconnections 81a and 81b are formed by patterning the same interconnection layer as the data line 114. However, the shield interconnections 81a and 81b may be formed from an interconnection layer different from the data line 114. Then, the case where shield wiring 81a, 81b is formed from the same wiring layer as relay electrode 61, 62 under the data line 114 and the power supply line 116 as an example is explained as a 2nd embodiment as an example. .

FIG. 10 is a plan view showing the configuration of the pixel circuit 110 of the electro-optical device in the second embodiment, and FIG. 11 is a partial cross-sectional view taken along line F-f in FIG.
When the shield wires 81a and 81b are formed from the same wiring layer as the relay electrodes 61 and 62 and the power supply line 116, it is necessary to avoid interference (electrical contact) between the shield wire 81a and the relay electrode 61. Specifically, the contact hole 51 needs to be provided outside the shield wiring 81a (on the left side in FIGS. 10 and 11) in plan view.
For this reason, in the second embodiment, as shown in FIG. 10, the contact holes 51 and 71 are disposed so as to overlap at the same point in plan view, and the relay electrode 41 is extended to the point . Of course, the relay electrode 61 may be extended to another point, for example, and the contact holes 51 and 71 may be arranged to be different points when viewed in plan (not shown).

Also in the second embodiment, the shield wire 81a is located in front of each node of the transistor 140 in the i-th row and the j-th column in plan view as viewed from the data line 114 in the j-th column. The noise generated from 114 is absorbed by the coupling capacitance between the shield interconnection 81a and the data line 114 in the j-th column.
Further, the shield wiring 81b is also located in front of each node of the transistor 140 in the i-th row and the j-th column in plan view as viewed from the data line 114 of the (j + 1) th column. The noise generated from 114 is absorbed by the coupling capacitance between the shield wire 81 b and the data line 114 in the (j + 1) th column.
For this reason, also in the second embodiment, stable display is possible because it is unlikely to be affected by noise or the like.
Further, in the second embodiment, since the shield wires 81a and 81b are formed by patterning the same wiring layer as the relay electrodes 61 and 62 and the power supply line 116, in the manufacturing process as in the first embodiment. No additional process is required.

  Furthermore, in the second embodiment, the shield interconnections 81a and 81b are formed using an interconnection layer different from the data line 114. For this reason, since contact with shield wire 81a, 81b and data line 114 is avoided, narrowing of the pixel circuit is facilitated. That is, in the first embodiment, the shield wires 81a and 81b are formed from the same wiring layer as the data line 114. Therefore, in order to secure the shield function, the shield wires 81a and 81b are separated from the data line 114. There is a need. On the other hand, in the second embodiment, there is no such need, so even if the shield wires 81a and 81b overlap the data line 114 in plan view, it is electrical if separated at the relay electrode 61. This makes it possible to narrow the pitch easily.

  By the way, if the shield wiring is formed to intersect with each node in the transistor 140 in plan view, a stronger shielding function can be expected. Therefore, an example in which the shield wiring is formed from the same wiring layer as the data line to strengthen the shield function will be described as the third embodiment and the fifth embodiment. Further, an example in which the shield wiring is formed from a wiring layer different from the data line and the shielding function is enhanced will be described later as the sixth embodiment and the seventh embodiment.

Third Embodiment
FIG. 12 is a plan view showing the configuration of the pixel circuit 110 of the electro-optical device in the third embodiment, and FIG. 13 is a partial cross-sectional view taken along line H-h in FIG.
As shown in FIG. 12, in the third embodiment, a part of the shield wire 81 a is extended toward the right side, and is formed to cover the relay electrode 43 in plan view. The storage capacitor 135 is a region where the relay electrode 43 and the gate electrode layer 21 overlap in plan view, and the relay electrode 43 is the other electrode of the storage capacitor 135 and is also the source node s of the transistor 140. For this reason, in the third embodiment, the shield function is further enhanced as compared to the first embodiment.

Fourth Embodiment
FIG. 14 is a plan view showing the configuration of the pixel circuit 110 of the electro-optical device according to the fourth embodiment.
As shown in this figure, shield wires 81 a and 81 b are formed in a strip shape along the data line 114 for each pixel circuit 110, and are connected to the power supply line 116. In the fourth embodiment, the shield wires 81a and 81b are formed of the same wiring layer as the data line 114. Therefore, shield interconnection 81a is connected to power supply line 116 through contact hole 73 which opens third interlayer insulating film 13, and shield interconnection 81b similarly contacts which open third interlayer insulating film 13. It is connected to the power supply line 116 through the hole 74. The cross sectional view is omitted.

  As in the first embodiment, when the shield wires 81a and 81b are respectively formed along the data line 114, if the resistivity is relatively large or if they are separated from the connection point of the constant potential, In some cases, the impedances of the shield wires 81a and 81b become relatively high, and noise can not be sufficiently absorbed. On the other hand, according to the fourth embodiment, since the shield wires 81a and 81b are provided for each pixel circuit 110 and connected to the power supply line 116, the impedance can be reduced and the noise absorbing ability can be achieved. It will be possible to raise

Fifth Embodiment
FIG. 15 is a plan view showing the configuration of the pixel circuit 110 of the electro-optical device according to the fifth embodiment. The fifth embodiment is a combination of the third embodiment and the fourth embodiment, and is formed to cover the relay electrode 43 in plan view by changing the shape of the shield wiring 81a shown in FIG. It is
For this reason, according to the fifth embodiment, it is possible to enhance the shielding function and enhance the noise absorbing capability.

Sixth Embodiment
When the shield wiring is formed from a wiring layer different from the data line 114 as in the second embodiment, the data wiring 114 is overlapped with the data line 114 in plan view, not on both sides of the data line 114. It may be provided on the lower side of
On the other hand, it has already been described in the fourth (fifth) embodiment that the ability to absorb noise can be enhanced by connecting shield wiring to, for example, the power supply line 116 for each pixel circuit 110.
Then, the two are combined to form a shield wiring from a wiring layer different from the data line 114, and provided on the lower layer side of the data line 114 so as to overlap the data line 114 in plan view. A sixth embodiment of the invention will be described.

FIG. 16 is a plan view showing the configuration of the pixel circuit 110 of the electro-optical device according to the sixth embodiment, and FIG. 17 is a partial cross-sectional view taken along the line J-j in FIG.
In the first to fifth embodiments, the shield wires 81a and 81b are provided in one row in one row, but in the sixth embodiment, the shield wires 81a and 81b are integrated with the shield wire 81 and also used as the power supply line 116. There is.
As shown in FIG. 17, the shield wiring 81 which doubles as the power supply line 116 is obtained by patterning the wiring layer formed on the second interlayer insulating film 12 together with the relay electrodes 61 and 62. The shape of the shield wiring 81 in a plan view is wider than the data line 114 and integrated with the power supply line 116 in the horizontal direction so as to overlap with the data line 114 in the vertical direction, as shown in FIG. It has a lattice shape.

The data line 114 is connected to the drain region 130 d via the relay electrodes 61 and 41 in order, but since the shield wiring 81 is formed of the same wiring layer as the relay electrode 61, it is necessary to avoid interference. Therefore, data line 114 is branched in the right direction in FIG. 16 and extends to a portion where shield interconnection 81 is not formed. A contact hole 51 is formed in the extended portion to connect the data line 114 to the relay electrode 61. As a result, the shield wiring 81 and the relay electrode 61 are electrically separated without interfering with each other.
In this example, the contact holes 51 and 71 are arranged to overlap at the same point when viewed in plan, but may be arranged to be different points (not shown).

  In the sixth embodiment, since the data line 114 is branched and extended to the right, noise may jump from the extended portion to the gate node g and the source node s of the transistor 140. . Therefore, in the sixth embodiment, a branch wiring 81d in which the shield wiring 81 is extended to the right side is provided between the branch portion of the data line 114 and the relay electrode 43 / gate electrode layer 21 in plan view. ing. Thus, the noise from the portion extended to the right side of the data line 114, that is, the vicinity of the contact hole 71 is absorbed by the branch wiring 81d before reaching each node of the transistor 140.

  According to the sixth embodiment, the shield wiring 81 is provided so as to overlap the data line 114 in plan view, and the potential is fixed by being shared with the power supply line 116, so that the shield function is reinforced. Will be

Seventh Embodiment
FIG. 18 is a plan view showing the configuration of the pixel circuit 110 of the electro-optical device according to the seventh embodiment.
As shown in this figure, in the seventh embodiment, the shield wiring 81 which also serves as the power supply line 116 is configured to cover the storage capacitor 135 (gate electrode layer 21) and the transistor 140 in plan view. .
As described above, since the shield wiring 81 (power supply line 116) is formed by patterning the same wiring layer as the relay electrodes 61 and 62, it is necessary to avoid interference with the relay electrodes 61 and 62. In the seventh embodiment, the shield wiring 81 which also serves as the power supply line 116 has a shape opened in the vicinity of the relay electrodes 61 and 62.
The cross-sectional view of the main parts of the pixel circuit 110 according to the seventh embodiment is as in FIG. 17 with the addition of the part indicated by the broken line.

According to the seventh embodiment, the shield wiring 81 is provided so as to overlap the data line 114 in plan view and to cover the storage capacitor 135 and the transistor 140, and the potential is fixed by sharing the power supply line 116. Therefore, the shield function can be further enhanced.
In the seventh embodiment, the opening area of the shield wiring 81 may be narrowed as long as the relay electrodes 61 and 62 do not interfere with each other. Further, in the seventh embodiment, the entire area of the storage capacitor 135 and the transistor 140 is covered with the shield wiring 81 in plan view, but only a part may be covered.

<Example of application / modification>
The present invention is not limited to the embodiment described above, and the following applications and modifications are possible.
For example, regarding the configuration of the storage capacitor 135, although the first interlayer insulating film 11 is sandwiched between the gate electrode layer 21 and the relay electrode 43, a semiconductor layer is provided to overlap the gate electrode layer 21 in plan view, for example. The gate insulating film 10 may be sandwiched between the layer and the gate electrode layer 21. As a semiconductor layer, what extended the source region 140s may be used, and what was separately patterned may be used. In addition to this, an interlayer insulating film or a gate insulating film may be sandwiched between electrodes and wirings formed of different wiring layers, or a plurality of parallel connected ones may be used as a storage capacitor 135 as a whole.
Further, as to the position where the storage capacitance 135 is electrically interposed, between the gate node g and the common electrode 118 as shown in FIG. Although not shown, it may be between the gate node g and a wire fixed to another potential.

The driving of the pixel circuit 110 is not limited to the method of holding the data signal of the potential corresponding to the gray scale data in the gate node g during the selection period in which the transistor 130 is in the ON state. For example, in the selection period in which the transistor 130 is in the on state, the data line 114 is set to the reference potential, and the power supply by the power supply line 116 and the common electrode 118 is switched between the first potential and the second potential. A voltage corresponding to the threshold voltage may be held in the storage capacitor 135, and thereafter, the data line 114 may be driven to a potential corresponding to the gradation data. Further, the potential of the data signal may be changed in the selection period, and the temporal change rate of the data signal at the end of the selection period may be driven to a value corresponding to the gradation data. A ramp signal may be supplied row by row via the element to drive the set current to the transistor 140.
In any driving, the potential of each node of the transistor 140 which causes a current to flow to the light emitting element 150 is fluctuated by the noise from the data line 114 by providing the pixel circuit 110 with a shield wiring as in each embodiment. It is possible to reduce

  The shield wiring may be formed by patterning different wiring layers of two or more layers. For example, in the sixth (seventh) embodiment, the same wiring layer as the data line 114 and the relay electrode 82 is patterned to form a double structure of the shield wiring 81 (power supply line 116) and the separately formed shield wiring. Also good. Note that interference with the data line 114 and the relay electrode 82 may be avoided for the separate shield wiring.

  As the light emitting element 150, an element other than an OLED, such as an inorganic EL element or a light emitting diode (LED) element, which emits light with luminance according to current, is applicable.

<Electronic equipment>
Next, some electronic devices to which the electro-optical device according to the present invention is applied will be described.
FIG. 20 is a view showing an appearance of a personal computer adopting the electro-optical device 1 according to the above-described embodiment as a display device. The personal computer 2000 includes the electro-optical device 1 as a display device and a main body portion 2010. The main body portion 2010 is provided with a power switch 2001 and a keyboard 2002.
In the electro-optical device 1, when an OLED is used as the light emitting element 150, it is possible to display a screen with a wide viewing angle and easy to view.

  FIG. 21 is a view showing an appearance of a mobile phone adopting the electro-optical device 1 according to the embodiment as a display device. The cellular phone 3000 includes the electro-optical device 1 described above together with the earpiece 3003 and the mouthpiece 3004 in addition to the plurality of operation buttons 3001 and the direction key 3002. By operating the direction key 3002, the screen displayed on the electro-optical device 1 is scrolled.

  FIG. 22 is a view showing the appearance of a portable information terminal (PDA: Personal Digital Assistants) in which the electro-optical device 1 according to the embodiment is adopted as a display device. The portable information terminal 4000 includes the above-described electro-optical device 1 in addition to the plurality of operation buttons 4001, the direction key 4002, and the like. In the portable information terminal 4000, various information such as an address book and a schedule book are displayed on the electro-optical device 1 by a predetermined operation, and the displayed information is scrolled according to the operation of the direction key 4002.

  As an electronic apparatus to which the electro-optical device according to the present invention is applied, in addition to the examples shown in FIG. 20 to FIG. 22, a television, a car navigation device, a pager, an electronic notebook, an electronic paper, an electronic paper, a calculator, a word processor, a work Stations, video phones, POS terminals, printers, scanners, copiers, video players, devices equipped with touch panels, and the like. In particular, examples of the micro display include a head mounted display and an electronic view finder of a digital still camera or a video camera.

Reference Signs List 1 electro-optical device 81 81a 81b shield wiring 110 pixel circuit 112 scan line 114 data line 116 power line 118 common electrode 130 transistor 135 storage capacitance 140 ... transistor, 150 ... light emitting element, 210 ... scanning line drive circuit, 220 ... data line drive circuit, 2000 ... personal computer, 3000 ... mobile phone, 4000 ... mobile information terminal.

Claims (6)

Scan lines extending in a first direction;
A data line extending in a second direction intersecting the first direction;
A pixel provided corresponding to the intersection of the scanning line and the data line;
Have
The pixel is
A light emitting element,
A first transistor controlling a current flowing to the light emitting element;
One of the source and the drain is electrically connected to the data line, the other of the source and the drain is electrically connected to the gate of the first transistor, and the scanning signal supplied to the scanning line Accordingly, a second transistor in which the conduction state between the source and the drain is controlled;
A storage capacitor that includes a gate electrode layer, a first relay electrode, and a first insulating layer positioned between the gate electrode layer and the first relay electrode, and holds the potential of the gate electrode layer;
Equipped with
The gate of the first transistor is a portion overlapping with the semiconductor layer of the first transistor in the gate electrode layer in plan view,
In cross-sectional view, the gate electrode layer is located between the semiconductor layer and the first relay electrode. Has a first constant potential wiring,
The pixel is
A second relay electrode electrically connected between any one of the source and the drain of the first transistor and the first constant potential wire;
The first constant potential wiring and the second relay electrode are located in a layer between the data line and the first transistor when viewed in cross section. Electro-optical device. A second insulating layer disposed to cover the first insulating layer;
A third insulating layer disposed to cover the second insulating layer;
Equipped with
The data line is disposed between the second insulating layer and the third insulating layer.
The electro-optical device according to claim 2, wherein the first constant potential wiring and the second relay electrode are disposed between the first insulating layer and the second insulating layer. A second constant potential wire extending in the second direction;
The electro-optic according to any one of claims 1 to 3, wherein the second constant potential wiring is located in a layer between the data line and the first transistor when viewed in cross section. apparatus. The electro-optical device according to claim 4, wherein the second constant potential wiring is disposed between the first insulating layer and the second insulating layer. An electronic apparatus comprising the electro-optical device according to any one of claims 1 to 5.

Images