JP6245326B2 - Electro-optical device and electronic apparatus - Google Patents

Description

  The present invention relates to an electro-optical device and an electronic apparatus.

  In recent years, various electro-optical devices using light-emitting elements such as organic light emitting diodes (hereinafter referred to as “OLEDs”) have been proposed. In such an electro-optical device, a pixel circuit is provided corresponding to the intersection of the scanning line and the data line. The pixel circuit generally has a configuration including the light emitting element, a switching transistor, and a driving transistor (see Patent Document 1). Here, the switching transistor is turned on during the scanning line selection period between the data line and the gate of the driving transistor, whereby the potential supplied to the data line is held at the gate. The driving transistor is configured to flow a current corresponding to the holding potential of the gate to the light emitting element.

JP 2007-310311 A

By the way, in applications where a reduction in display size and a higher definition of display are required, the degree to which data lines and drive transistors are close to each other and capacitively coupled is increased. For this reason, when the potential of the data line fluctuates, the potential fluctuation propagates as a kind of noise to each part of the driving transistor, particularly the gate, via the parasitic capacitance, and the holding potential of the gate is fluctuated. Therefore, it has been pointed out that the target current cannot be supplied to the light emitting element, and the display quality is deteriorated.
The present invention has been made in view of the above-described problems, and one of its purposes is to prevent display quality from being deteriorated by noise caused by fluctuations in the potential of a data line.

  In order to solve the above problems, in the electro-optical device according to the present invention, a scanning line provided along the first direction, a first insulating film provided so as to cover the scanning line, A second insulating film provided so as to cover the first insulating film; a data line provided above the second insulating film along a second direction different from the first direction; and the scanning A pixel circuit provided corresponding to the intersection of a line and the data line, and a shield wiring, the pixel circuit comprising: a light emitting element; and a first transistor for controlling a current flowing through the light emitting element; And a part of the shield wiring is provided between the first insulating film and the second insulating film and between the data line and the first transistor when seen in a plan view. It is characterized by.

In the present invention, it is preferable that the distance between the shield wiring and the data line is shorter than the distance between the shield wiring and the first transistor.
In the present invention, it is preferable that the power supply line is further provided, the first transistor is connected between the power supply line and the light emitting element, and the shield wiring is connected to the power supply line. In such a configuration, the power supply line may be provided between the first insulating film and the second insulating film.
A second transistor whose conduction state is controlled in accordance with a scanning signal supplied to the scanning line; a first relay electrode connected to the second transistor; and a first transistor that connects the first relay electrode and the data line. 2 relay electrodes, a first connection part for connecting the first relay electrode and the second relay electrode, and a second connection part for connecting the data line and the second relay electrode. The first connection portion may overlap the second connection portion when seen in a plan view.

Further, the object is to provide a scanning line provided along the first direction, a first insulating film provided so as to cover the scanning line, and a second provided so as to cover the first insulating film. An insulating film, a first data line provided above the second insulating film along a second direction different from the first direction, and a second data line formed along the second direction. Corresponding to the intersection of the second data line provided above, the first pixel circuit provided corresponding to the intersection of the scanning line and the first data line, and the scanning line and the second data line A second pixel circuit provided, wherein the first pixel circuit includes a first light emitting element and a first transistor for controlling a current flowing through the first light emitting element, and the second pixel circuit. The pixel circuit includes a second light emitting element and a second transistor that controls a current flowing through the second light emitting element. The shield wiring includes a first shield wiring and a second shield wiring, and a part of the first shield wiring is between the first insulating film and the second insulating film. When viewed in plan, the second shield wiring is provided between the first transistor and the first data line, and a part of the second shield wiring is between the first insulating film and the second insulating film. This can also be achieved by a configuration provided between the second transistor and the first data line when viewed in plan.
Here, a distance between the first shield wiring and the first data line is shorter than a distance between the first shield wiring and the first transistor, and a distance between the second shield wiring and the first data line. May be shorter than the distance between the second shield wiring and the second transistor.
The storage device may further include a storage capacitor having one end connected to the gate of the first transistor, and the shield wiring may be provided so as to cover the storage capacitor when seen in a plan view. It may be provided so as to cover the first transistor when viewed.
The electro-optical device according to the invention can be applied to various electronic apparatuses. Typically, it is a display device, and examples of the electronic device include a personal computer and a mobile phone. In particular, according to the present invention, even when a sufficient storage capacity cannot be ensured, noise from the data line is absorbed by the shield wiring before reaching the driving transistor of the pixel circuit, thereby preventing deterioration in display quality. Therefore, it is suitable for a display device that forms a reduced image, for example, for a head-mounted display or a projector. However, the use of the electro-optical device according to the invention is not limited to the display device. For example, the present invention can also be applied to an exposure apparatus (optical head) for forming a latent image on an image carrier such as a photosensitive drum by irradiation of light.

1 is a block diagram illustrating a configuration of an electro-optical device according to a first embodiment. It is a figure which shows the equivalent circuit of the pixel circuit in an electro-optical apparatus. It is a figure which shows the display operation of an electro-optical apparatus. It is a top view which shows the structure of a pixel circuit. It is a fragmentary sectional view which shows the structure fractured | ruptured by the EE line | wire in FIG. It is a figure which shows the noise absorption from the data line in a pixel circuit. It is a figure which shows the various parasitic capacitances in a pixel circuit. It is the figure which modeled various parasitic capacitances in a pixel circuit. It is a figure which shows an example of crosstalk. FIG. 6 is a plan view illustrating a configuration of a pixel circuit of an electro-optical device according to a second embodiment. It is a fragmentary sectional view which shows the structure fractured | ruptured by the FF line | wire in FIG. FIG. 10 is a plan view illustrating a configuration of a pixel circuit of an electro-optical device according to a third embodiment. It is a fragmentary sectional view which shows the structure fractured | ruptured by the Hh line | wire in FIG. FIG. 10 is a plan view illustrating a configuration of a pixel circuit of an electro-optical device according to a fourth embodiment. FIG. 10 is a plan view illustrating a configuration of a pixel circuit of an electro-optical device according to a fifth embodiment. FIG. 10 is a plan view illustrating a configuration of a pixel circuit of an electro-optical device according to a sixth embodiment. It is a fragmentary sectional view which shows the structure fractured | ruptured by the JJ line | wire in FIG. FIG. 20 is a plan view illustrating a configuration of a pixel circuit of an electro-optical device according to a seventh embodiment. It is a figure which shows the equivalent circuit of the pixel circuit which concerns on another example. It is a figure which shows the electronic device (the 1) to which an electro-optical apparatus is applied. It is a figure which shows the electronic device (the 2) to which an electro-optical apparatus is applied. It is a figure which shows the electronic device (the 3) to which an electro-optical apparatus is applied.

<First Embodiment>
FIG. 1 is a block diagram showing the configuration of the electro-optical device according to the first embodiment of the invention. The electro-optical device 1 displays an image with a plurality of pixel circuits 110.
As shown in this figure, the electro-optical device 1 includes an element unit 100, a scanning line driving circuit 210, and a data line driving circuit 220.
Among these, in the element unit 100, m rows of scanning lines 112 are provided along the row (X) direction in the drawing, and n columns of data lines 114 are arranged along the column (Y) direction and each scan. The wires 112 are provided so as to be electrically insulated from each other. The pixel circuits 110 are arranged corresponding to the intersections of the m rows of scanning lines 112 and the n columns of data lines 114, respectively. Accordingly, in the present embodiment, the pixel circuits 110 are arranged in a matrix with m rows × n columns. Note that m and n are both natural numbers.

A power line 116 is commonly connected to each pixel circuit 110 and supplies the potential Vel on the higher side of the element power supply. Although not shown in FIG. 1, a common electrode is provided over each pixel circuit 110 to supply power to the lower potential Vct of the element power supply, as will be described later. These potentials Vel and Vct are generated by a power supply circuit (not shown).
In order to distinguish the scanning lines 112 and the rows of the pixel circuits 110 for the sake of convenience, they may be referred to as the first row, the second row, the third row,..., The (m−1) row, the m row in FIG. is there. Similarly, in order to distinguish the columns of the data lines 114 and the pixel circuits 110 for the sake of convenience, they may be referred to as the first column, the second column, the third column,..., The (n−1) column, the n column in order from the left in FIG. is there.

In the electro-optical device 1, a scanning line driving circuit 210 and a data line driving circuit 220 are arranged around a region where the pixel circuits 110 are arranged in a matrix. The operations of the scanning line driving circuit 210 and the data line driving circuit 220 are controlled by a controller (not shown). The data line driving circuit 220 is supplied with gradation data specifying gradation (luminance) to be expressed by each pixel circuit 110 from the controller.
The scanning line driving circuit 210 sequentially selects the first to mth rows in each frame. As an example, the scanning line driving circuit 210 includes scanning signals Gwr (1), Gwr (2), Gwr (3), Gm (1), Gwr (2), Gwr (3), ..., Gwr (m−1), Gwr (m) are supplied, and each scanning signal is sequentially set to the H level exclusively in the frame. In this description, the frame means a period required to display an image for one cut (frame) on the electro-optical device 1, and if the vertical scanning frequency is 60 Hz, 16.67 for one cycle. A period of milliseconds.

  The data line driver circuit 220 supplies a data signal having a potential corresponding to the gradation data of the pixel circuit 110 to the pixel circuit 110 located in the row selected by the scanning line driver circuit 210 via the data line 114. To do. For convenience, the data signals supplied to the data lines 114 of 1, 2, 3,..., (N−1), and the n-th column are represented by Vd (1), Vd (2), Vd (3),. , Vd (n-1), Vd (n).

  Next, an equivalent circuit of the pixel circuit 110 will be described with reference to FIG. In FIG. 2, the scanning line 112 in the (i + 1) th row adjacent to the i-th row and the i-th row is adjacent to the j-th column and the j-th column on the right side (j + 1). A pixel circuit 110 for a total of 4 pixels of 2 × 2 corresponding to the intersection with the data line 114 in the column is shown. Here, i and (i + 1) are symbols for generally indicating the rows in which the pixel circuits 110 are arranged, and are integers of 1 or more and m or less. Similarly, j and (j + 1) are symbols for generally indicating a column in which the pixel circuit 110 is arranged, and are integers of 1 or more and n or less.

As shown in FIG. 2, each pixel circuit 110 includes N-channel transistors 130 and 140, a storage capacitor 135, and a light emitting element 150. Since each pixel circuit 110 has the same configuration, the pixel circuit 110 will be described as being representatively located at i rows and j columns. In the pixel circuit 110 in the i-th row and j-th column, the transistor 130 functions as a switching transistor, and its gate node is connected to the scanning line 112 in the i-th row, while its drain node is the data line in the j-th column. The source node is connected to one end of the storage capacitor 135 and the gate node of the transistor 140.
The other end of the storage capacitor 135 is connected to the source node of the transistor 140 and the anode of the light emitting element 150. On the other hand, the drain node of the transistor 140 is connected to the power supply line 116.

For convenience, in the pixel circuit 110 in the i-th row and j-th column, the drain node of the transistor 130 is denoted by uppercase D, and the gate node of the transistor 140 (the source node of the transistor 130 and one end of the storage capacitor 135) is denoted by lowercase g. It is written. In particular, the gate node of the transistor 140 in i row and j column is expressed as g (i, j).
In addition, the drain node (power supply line 116) of the transistor 140 is represented by a lowercase letter d, and the source node of the transistor 140 (the anode of the light emitting element 150) is represented by a lowercase letter s.

The cathode of the light emitting element 150 is connected to the common electrode 118 over each pixel circuit 100. The common electrode 118 is common across the light emitting elements 150 of the pixel circuits 110. The light-emitting element 150 is an OLED in which a light-emitting layer made of an organic EL material is sandwiched between an anode and a cathode facing each other, and emits light with a luminance corresponding to a current flowing from the anode toward the cathode.
In FIG. 2, Gwr (i) and Gwr (i + 1) indicate scanning signals supplied to the scanning lines 112 in the i and (i + 1) th rows, respectively. Vd (j) and Vd (j + 1) represent data signals supplied to the data lines 114 in the j and (j + 1) th columns, respectively.
In this embodiment, a shield wiring is provided in the vicinity of the data line 114. Details of the shield wiring will be described later.

Next, the display operation of the electro-optical device 1 will be briefly described with reference to FIG. FIG. 3 is a diagram illustrating an example of waveforms of the scanning signal and the data signal.
As shown in this figure, the scanning signals Gwr (1), Gwr (2), Gwr (3),..., Gwr (m−1), Gwr (m) are horizontally generated by the scanning line driving circuit 210 over each frame. It becomes the H level exclusively and sequentially every scanning period (H).
Here, when the scanning line 112 in the i-th row is selected and the scanning signal Gwr (i) becomes H level, the gradation data of the pixel circuit 110 in the i-th row and j-th column is displayed on the j-th data line 114. The data signal Vd (j) having a potential corresponding to the voltage is supplied from the data line driving circuit 220.

  When the scanning signal Gwr (i) becomes H level in the pixel circuit 110 in the i row and j column, the transistor 130 is turned on, so that the gate node g (i, j) is electrically connected to the data line 114 in the j column. It becomes a state. For this reason, the potential of the gate node g (i, j) becomes the potential of the data signal Vd (j) as shown by the up arrow in FIG. At this time, the transistor 140 passes a current corresponding to the potential of the gate node g (i, j) to the light emitting element 150, and the storage capacitor 135 holds the gate-source voltage in the transistor 140 at this time. When selection of the i-th scanning line 112 is completed and the scanning signal Gwr (i) becomes L level, the transistor 130 is turned off.

  Even when the transistor 130 is switched from on to off, the gate-source voltage of the transistor 140 when the transistor 130 is on is held by the storage capacitor 135. For this reason, even if the transistor 130 is turned off, the transistor 140 continues to flow a current corresponding to the holding voltage of the holding capacitor 135 to the light emitting element 150 until the next i-th scanning line 112 is selected again. For this reason, the light emitting element 150 in the pixel circuit 110 in the i-th row and j-th column has luminance corresponding to the potential of the data signal Vd (j) when the i-th row is selected. Light emission continues for a period corresponding to one frame at a corresponding luminance.

Note that, in the i-th row, the pixel circuits 110 other than the j-th column also emit light with luminance corresponding to the potential of the data signal supplied to the corresponding data line 114. Although the pixel circuit 110 corresponding to the scanning line 112 in the i-th row is described here, the scanning line 112 is selected in the order of 1, 2, 3,... (M−1), m-th row. As a result, each of the pixel circuits 110 emits light at a luminance corresponding to the gradation data. Such an operation is repeated every frame.
In FIG. 3, the potential scales of the data signal Vd (j) and the gate node g (i, j) are enlarged for convenience than the potential scale of the scanning signal.

By the way, since the data signal has a potential corresponding to the gradation data of the pixel located in the selected row, the potential of the data line 114 changes every moment according to the display content. For example, since the data signal Vd (j) as shown in FIG. 3 is supplied to the data line 114 in the j-th column, the potential fluctuates every horizontal scanning period (H).
When the data line 114 is capacitively coupled to each part of the pixel circuit 110, the potential fluctuation of the data line 114 adversely affects the potential of each part of the pixel circuit 110. Especially in applications that require a smaller display size and higher display resolution, for example, in a micro display having a display size of less than 1 inch diagonally and a resolution of 1280 × 720 pixels or more, In comparison, the parasitic capacitance of each part becomes relatively large, so that the influence appears remarkably. In particular, the potentials of the gate node g and the source node s of the transistor 140 define the current that flows through the light emitting element 150. Therefore, the potential fluctuation in this portion causes display distortion and crosstalk to be described later. It becomes a factor to greatly reduce.
Therefore, in the present embodiment, the pixel circuit 110 is configured as follows to make it less susceptible to noise caused by potential fluctuations in the data line.

The structure of the pixel circuit 110 will be described with reference to FIGS.
FIG. 4 is a plan view showing a configuration of four pixel circuits 110 adjacent to each other in the vertical and horizontal directions, and FIG. 5 is a partial cross-sectional view taken along line Ee in FIG.
FIG. 4 shows a wiring structure when the top emission pixel circuit 110 is viewed in plan from the observation side. For simplicity, a structure formed after the pixel electrode (anode) in the light emitting element 150 is shown. The body is omitted. In FIG. 5, only the pixel electrode of the light emitting element 150 is shown, and the subsequent structures are omitted. Further, in each of the following drawings, the scales are varied in order to make each layer, each member, each region, etc. recognizable.

  First, as shown in FIG. 5, the base substrate 2 is provided with semiconductor layers 130a and 140a obtained by patterning a polysilicon film in an island shape. The semiconductor layer 130 a constitutes the transistor 130, and the semiconductor layer 140 a constitutes the transistor 140. Here, as viewed in plan, the semiconductor layer 130a is formed in a rectangular shape whose length extends in the lateral direction along the scanning line 112 to be formed later. On the other hand, the semiconductor layer 140a is formed in a rectangular shape whose length extends in the vertical direction along the data line 114 to be formed later when viewed in plan.

As shown in FIG. 5, the gate insulating film 10 is provided so as to cover almost the entire surface of the semiconductor layers 130a and 140b. A gate wiring layer such as aluminum or tantalum is provided on the surface of the gate insulating film 10, and the scanning line 112 and the gate electrode layer 21 are provided by patterning the gate wiring layer.
The scanning line 112 extends in the horizontal direction in FIG. 4 and has a portion branched downward for each pixel circuit 110, and the branched portion overlaps the central portion of the semiconductor layer 130a. In the semiconductor layer 130a, a region overlapping with the branch portion of the scanning line 112 is a channel region 130c (see FIG. 5). Of the semiconductor layer 130a, the left direction in FIG. 5 is the drain region 130d and the right direction is the source region 130s with respect to the channel region 130c.
On the other hand, as shown in FIG. 4 when viewed in plan, the gate electrode layer 21 has a shape in which the upper side, the right side, and the lower side of the square frame are integrated without having the left side. Among these, the lower side overlaps with the central portion of the semiconductor layer 140a. Of the semiconductor layer 140a, a region overlapping the lower side of the gate electrode layer 21 is a channel region 140c (see FIG. 5). Of the semiconductor layer 140a, the left direction in FIG. 5 is the source region 140s and the right direction is the drain region 140d with respect to the channel region 140c region.

In FIG. 5, a first interlayer insulating film 11 is formed so as to cover the scanning line 112, the gate electrode layer 21 or the gate insulating film 10. A conductive wiring layer is formed on the surface of the first interlayer insulating film 11, and relay electrodes 41, 42, 43, and 44 are formed by patterning the wiring layer, respectively.
Among these, the relay electrode 41 is connected to the drain region 130d through a contact hole (via) 31 that opens the first interlayer insulating film 11 and the gate insulating film 10, respectively.
In FIG. 4, the portion where “□” mark is attached to the “□” mark in the portion where the different wiring layers overlap is the contact hole.

In FIG. 5, one end of the relay electrode 42 is connected to the source region 130 s through the contact hole 32 that opens the first interlayer insulating film 11 and the gate insulating film 10, while the other end of the relay electrode 42 is It is connected to the gate electrode layer 21 through a contact hole 33 that opens the first interlayer insulating film 11.
The relay electrode 43 is connected to the source region 140 s through a contact hole 34 that opens the first interlayer insulating film 11 and the gate insulating film 10. Here, the shape of the relay electrode 43 in plan view is a rectangle that covers the upper side of the gate electrode layer 21 as shown in FIG. Therefore, the storage capacitor 135 has a configuration in which the first interlayer insulating film 11 is sandwiched between the gate electrode layer 21 and the relay electrode 43 as shown in FIG.
The relay electrode 44 is connected to the drain region 140d through a contact hole 35 that opens the first interlayer insulating film 11 and the gate insulating film 10, respectively.

A second interlayer insulating film 12 is formed so as to cover the relay electrodes 41, 42, 43, 44 or the first interlayer insulating film 11. A conductive wiring layer is formed on the surface of the second interlayer insulating film 12, and relay electrodes 61 and 62 and a power supply line 116 are formed by patterning the wiring layer.
Among these, the relay electrode 61 is connected to the relay electrode 41 through a contact hole 51 that opens the second interlayer insulating film 12. The relay electrode 62 is also connected to the relay electrode 43 through a contact hole 52 that opens the second interlayer insulating film 12.
The power line 116 is connected to the relay electrode 44 through a contact hole 53 that opens the second interlayer insulating film 12. For this reason, the power line 116 is connected to the drain region 140d through the relay electrode 44. The power supply line 116 is formed along the horizontal direction in which the scanning line 112 extends as shown in FIG.
The contact holes 51, 52, and 53 are filled with columnar connection plugs made of a refractory metal such as tungsten, so that the relay electrodes 41 and 61, the relay electrodes 43 and 62, the relay electrode 44, and the power source are connected. The lines 116 may be connected to each other.

A third interlayer insulating film 13 is formed so as to cover the relay electrodes 61 and 62 or the second interlayer insulating film 12. A conductive wiring layer is formed on the surface of the third interlayer insulating film 13, and a data line 114, shield wirings 81a and 81b (not shown in FIG. 5), and a relay electrode 82 are formed by patterning the wiring layer. Has been.
Among these, the data line 114 is connected to the relay electrode 61 through the contact hole 71 that opens the third interlayer insulating film 13. For this reason, the data line 114 is connected to the drain region 130d along the path of the relay electrode 61 and the relay electrode 41. Here, the data line 114 is formed along a vertical direction orthogonal to the extending direction of the scanning line 112 as shown in FIG.
The relay electrode 82 is connected to the relay electrode 62 through a contact hole 72 that opens the third interlayer insulating film 13.
Alternatively, the contact holes 71 and 72 may be filled with columnar connection plugs made of a refractory metal to connect the relay electrode 61 and the data lines 114 and the relay electrodes 62 and 82 respectively.

Each of the shield wirings 81a and 81b is formed corresponding to each column as shown in FIG. 4 when viewed in plan.
Specifically, the shield wiring 81a of a certain column is formed along the vertical direction on the right side of the data line 114 so as to be positioned between the data line 114 of the column and the transistor 140 in the pixel circuit 110 of the column. Is done. At this time, the shield wiring 81a is provided close to the data line 114 when the data line 114 and the transistor 140 are compared. That is, the distance between the shield wiring 81a and the data line 114 is shorter than the distance between the shield wiring 81a and the transistor 140. For this reason, the shield wiring 81 a is more easily capacitively coupled to the data line 114 than the transistor 140.

On the other hand, the shield wiring 81b in a certain column is arranged in the vertical direction on the left side of the data line 114 so as to be positioned between the data line 114 adjacent to the column on the right side and the transistor 140 in the pixel circuit 110 in the column. Formed along. At this time, the shield wiring 81b is provided close to the data line 114 when the data line 114 and the transistor 140 are compared. That is, the distance between the shield wiring 81b and the data line 114 is shorter than the distance between the shield wiring 81b and the transistor 140. Therefore, the shield wiring 81b is more easily capacitively coupled to the data line 114 than the transistor 140.
When viewed in a plan view, the transistor 140 is disposed between the left data line 114 and the right data line 114, but the shield wiring 81a is disposed in front of the left data line 114, and the right data line 114 is disposed on the right side. The shield wiring 81b is disposed in front of the data line 114.

The shield wirings 81a and 81b are formed in the vertical direction in FIG. 4 and extend to the outside of the region where the pixel circuits 110 are arranged, and are applied with a constant potential, for example, the potential Vel.
Further, the shield wirings 81a and 81b may be connected via contact holes at a portion intersecting the power supply line 116 in a plan view for every row or every few rows.

A fourth interlayer insulating film 14 is formed so as to cover the data lines 114, the shield wirings 81a and 81b, the relay electrode 82, or the third interlayer insulating film 13. A wiring layer having conductivity and reflectivity is formed on the surface of the fourth interlayer insulating film 14, and an anode of the light emitting element 150 is formed by patterning the wiring layer. The anode is an individual pixel electrode for each pixel circuit 110 and is connected to the relay electrode 82 through a contact hole 92 that opens the fourth interlayer insulating film 14. For this reason, the anode (pixel electrode) is connected to the source region 140 s through a path of the relay electrode 82, the relay electrode 62, and the relay electrode 43 that also serves as the other electrode of the storage capacitor 135.
The contact hole 92 may be filled with a columnar connection plug made of a refractory metal to connect the relay electrode 82 and the pixel electrode.

Although the illustration of the subsequent structure as the electro-optical device 1 is omitted, a light emitting layer made of an organic EL material is laminated on the anode for each pixel circuit 110, and a common transparent electrode also serves as a cathode across each pixel circuit 110. It is provided as a common electrode 118. As a result, the light emitting element 150 becomes an OLED having a light emitting layer sandwiched between an anode and a cathode facing each other, emits light with a luminance corresponding to the current flowing from the anode toward the cathode, and in a direction opposite to the substrate 2. Will be observed (top emission structure). In addition, a sealing glass or the like for shielding the light emitting layer from the atmosphere is provided, but the description is omitted.
In FIG. 4, the pixel electrode that is the anode of the light emitting element 150 is not shown, and therefore, the contact hole 92 is given only the “□” mark indicating the position.

Next, the shielding function by the shield wirings 81a and 81b will be described with reference to FIG. FIG. 6 is a diagram in which the planar structure of the pixel circuit 110 illustrated in FIG. 4 is replaced with an electrical circuit.
As described above, since the potential of the data line 114 in each column fluctuates, noise due to the potential fluctuation propagates to each part of the pixel circuit 110.
In the first embodiment, the shield wiring 81a is positioned on the front side of the gate node g and the source node s of the transistor 140 in the i-th row and the j-th column as viewed from the data line 114 in the j-th column. Therefore, noise generated from the j-th data line 114 is absorbed by the coupling capacitance Ca between the shield wiring 81a and the j-th data line 114.
Further, the shield wiring 81b is also positioned on the near side of the gate node g and the source node s of the transistor 140 in the i row and j column, as viewed from the data line 114 in the (j + 1) th column. For this reason, the noise generated from the data line 114 in the (j + 1) th column is absorbed by the coupling capacitor Cb between the shield wiring 81b and the data line 114 in the (j + 1) th column.
Therefore, according to the electro-optical device 1, the gate node g and the source node s of the transistor 140 are not easily affected by noise due to the potential fluctuation of the data line 114, so that stable display is possible.
In the first embodiment, since the shield wirings 81a and 81b are formed by patterning the same wiring layer as the data lines 114 and the relay electrodes 82, no additional process is required in the manufacturing process.

FIG. 7 is a diagram illustrating an equivalent circuit of the pixel circuit 110 together with the parasitic capacitance of each part.
In this figure, C _Dg represents a parasitic capacitance generated between the drain node D (data line 114) of the transistor 130 and the gate node g of the transistor 140, and C _Ds represents the drain node D of the transistor 130 and the transistor 140. The parasitic capacitance generated between the source node s and the source node s is shown.
C _HOLD indicates the capacity of the storage capacitor 135.
C _gd represents a parasitic capacitance generated between the gate node g and the drain node d (power supply line 116) of the transistor 140, and C _ds represents a parasitic capacitance generated between the drain node d and the source node s of the transistor 140. C _OLED indicates a capacitance component in the light-emitting element 150.

In the pixel circuit 110, the transistor 130 is turned off when the corresponding scanning line is in the non-selection period. The power supply line 116 and the common electrode 118 are constant in potential.
Therefore, the pixel circuit 110 in the non-selection period can be simplified to a model as shown in FIG. In the figure, Vamp is the potential amplitude of the data line 114 in the non-selection period.
In this model, the variation ΔVgs given to the holding voltage Vgs of the holding capacitor 135 can be expressed as shown in Equation (1) in FIG. The coefficient _{K 1} in the formula (1) is expressed by equation (2), The coefficient _{K 2} is expressed by the equation (3).
In the present embodiment, since the shield wirings 81a and 81b are provided, the parasitic capacitances C _Dg and C _Ds are reduced as compared with the configuration without the shield wirings 81a and 81b.
Therefore, components of (a) term in Equation (2) is increased, the entire denominator component increases, the coefficient K ₁ is reduced. On the other hand, equation (3) of (b) with component sections is increased, since the whole denominator component increases, the coefficient K ₂ is also reduced.
Therefore, in the present embodiment, the variation ΔVgs with respect to the potential amplitude Vamp is smaller than that in the configuration without the shield wirings 81a and 81b, so that the data line 114 is less susceptible to the potential variation and noise. Display is possible.

  Here, when the potential of the gate node g and the source node s fluctuates due to noise caused by the fluctuation of the potential of the data line 114, specifically, it becomes apparent in the form of the following crosstalk and the display quality is improved. Reduce.

FIG. 9 is a diagram illustrating an example of crosstalk generated in an electro-optical device that does not include the shield wirings 81a and 81b as in the present embodiment.
As shown in FIG. 9A, the crosstalk here is, for example, when a black rectangular region is displayed in a window with gray as a background region, as shown in FIG. 9B, Dark gradation in which the upper region (a2) and the lower region (c2) are different from the other gray regions (a1, a3, b1, b3, c1, c3) with respect to the black region (b2) It is a phenomenon that is displayed.
In FIG. 9, the brightness of the area is indicated by the density of oblique lines. This crosstalk occurs even when the region (b2) is white. In any case, an area that is displayed with a different gradation appears in the vertical direction of the area (b2), and thus is sometimes called vertical crosstalk.

  This vertical crosstalk is considered to occur due to the following causes. That is, in a certain frame, the data line 114 extending over the regions (a1, b1, c1) is constant at a potential corresponding to gray gradation data over the selection from the first row to the last m-th row. Therefore, the pixel circuit 110 belonging to the region (a1, b1, c1) holds the potential held at the gate node g by selection of the scanning line corresponding to itself without being affected by noise from the data line. It will be. The same applies to the data line 114 extending over the region (a3, b3, c3) and the pixel circuit 110 belonging to the region (a3, b3, c3). Therefore, each of the pixel circuits 110 belonging to the regions (a1, a3, b1, b3, c1, c3) emits light with luminance according to the holding potential of the gate node g over the entire period corresponding to one frame. become.

On the other hand, the data line 114 extending over the region (a2, b2, c2) has a potential corresponding to gray gradation data during the selection of the region (a2), and during the selection of the region (b2). The voltage drops to the potential corresponding to the black gradation data, and becomes the potential corresponding to the gray gradation data again during the selection of the region (c2).
Therefore, in the pixel circuit 110 belonging to the region (a2), even if the gate node g holds a potential corresponding to gray by selecting the scanning line corresponding to the pixel circuit 110, the data line 114 at the time of selecting the region (b2) It will change due to noise caused by potential fluctuations.
Note that, when the region (c2) is selected, the data line 114 returns to the potential corresponding to gray again, so that the return may cause the gate node g to return to or approach the potential corresponding to gray.
However, even if the gate node g returns to the potential corresponding to gray, each of the pixel circuits 110 belonging to the region (a2) selects at least the region (b2) in the period corresponding to one frame after writing. Over time, light will be emitted with a luminance corresponding to the potential reduced from the potential corresponding to gray.
The same applies to the region (c2). That is, in the pixel circuit 110 belonging to the region (c2), even when the gate node g holds a potential corresponding to gray by selecting the scanning line corresponding to the pixel circuit 110, the data line is selected when the region (b2) is selected in the next frame. It will be pulled and changed by the potential fluctuation of 114.
Accordingly, each pixel circuit 110 belonging to the region (a2, c2) is a pixel belonging to the other region (a1, a3, b1, b3, c1, c3) when viewed from an average value of a period corresponding to one frame. Unlike each of the circuits 110, it is visually recognized with a dark gradation. This is considered to be a mechanism that causes vertical crosstalk.

According to the first embodiment, each of the gate node g and the source node s has a structure that is hardly affected by noise due to the potential fluctuation of the data line 114 by the shield wirings 81a and 82. This suppresses vertical crosstalk and enables high-quality display.
In the first embodiment, the shield wirings 81a and 81b are set to the same potential Vel as that of the power supply line 116, but may be maintained at another potential, for example, the potential Vct.

Second Embodiment
In the first embodiment, the shield wirings 81 a and 81 b are formed by patterning the same wiring layer as the data line 114, but may be formed from a wiring layer different from the data line 114. Therefore, as a second embodiment, a case where the shield wirings 81a and 81b are formed from the same wiring layer as the relay electrodes 61 and 62 and the power supply line 116 below the data line 114 will be described as an example. .

FIG. 10 is a plan view illustrating a configuration of the pixel circuit 110 of the electro-optical device according to the second embodiment, and FIG. 11 is a partial cross-sectional view taken along line FF in FIG.
When the shield wirings 81a and 81b are formed from the same wiring layer as the relay electrodes 61 and 62 and the power supply line 116, it is necessary to avoid interference (electrical contact) between the shield wiring 81a and the relay electrode 61. Specifically, the contact hole 51 needs to be provided on the outer side (left side in FIGS. 10 and 11) than the shield wiring 81a in a plan view.
Therefore, in the second embodiment, as shown in FIG. 10, the contact holes 51 and 71 are arranged so as to overlap at the same point when viewed in plan, and the relay electrode 41 is extended to the point. . Of course, for example, the relay electrode 61 may be extended to another point, and the contact holes 51 and 71 may be arranged at different points when viewed in plan (not shown).

Also in the second embodiment, since the shield wiring 81a is located on the front side of each node of the transistor 140 in the i-th row and the j-th column when viewed from the j-th column data line 114, the j-th column data line The noise generated from 114 is absorbed by the coupling capacitance between the shield wiring 81a and the j-th data line 114.
Also, the shield wiring 81b is located on the front side of each node of the i-th row and j-th column transistor 140 as viewed from the (j + 1) -th column data line 114, so the (j + 1) -th column data line The noise generated from 114 is absorbed by the coupling capacitance between the shield wiring 81b and the data line 114 in the (j + 1) th column.
For this reason, also in the second embodiment, since it is hardly affected by noise or the like, stable display is possible.
In the second embodiment, since the shield wirings 81a and 81b are formed by patterning the same wiring layer as the relay electrodes 61 and 62 and the power supply line 116, in the manufacturing process as in the first embodiment. No additional process is required.

  Furthermore, in the second embodiment, the shield wirings 81 a and 81 b are formed using a wiring layer different from the data line 114. Therefore, contact between the shield wirings 81a and 81b and the data line 114 can be avoided, so that the pitch of the pixel circuits can be easily reduced. That is, in the first embodiment, since the shield wirings 81a and 81b are formed from the same wiring layer as the data line 114, the shield wirings 81a and 81b are separated from the data line 114 in order to ensure a shielding function. There is a need. On the other hand, in the second embodiment, since there is no such necessity, even if the shield wirings 81a and 81b overlap the data line 114 in a plan view, if the relay electrodes 61 are separated from each other, they are electrically connected. Therefore, it is easy to reduce the pitch.

  By the way, if the shield wiring is formed so as to intersect each node in the transistor 140 in plan view, a stronger shield function can be expected. Therefore, an example in which the shield wiring is formed from the same wiring layer as the data line to enhance the shield function will be described as the third embodiment and the fifth embodiment. An example in which the shield wiring is formed from a wiring layer different from the data line to enhance the shield function will be described later as the sixth embodiment and the seventh embodiment.

<Third Embodiment>
FIG. 12 is a plan view illustrating a configuration of the pixel circuit 110 of the electro-optical device according to the third embodiment, and FIG. 13 is a partial cross-sectional view taken along line Hh in FIG.
As shown in FIG. 12, in the third embodiment, a part of the shield wiring 81a extends toward the right side and is formed so as to cover the relay electrode 43 when viewed in plan. The storage capacitor 135 is a region where the relay electrode 43 and the gate electrode layer 21 overlap when viewed in plan, and the relay electrode 43 is the other electrode in the storage capacitor 135 and also the source node s of the transistor 140. For this reason, in 3rd Embodiment, a shield function is strengthened compared with 1st Embodiment.

<Fourth embodiment>
FIG. 14 is a plan view illustrating a configuration of the pixel circuit 110 of the electro-optical device according to the fourth embodiment.
As shown in this figure, the shield wirings 81a and 81b are formed in strips along the data lines 114 for each pixel circuit 110, and are connected to the power supply lines 116, respectively. In the fourth embodiment, the shield wirings 81 a and 81 b are formed from the same wiring layer as the data lines 114. For this reason, the shield wiring 81a is connected to the power supply line 116 through the contact hole 73 that opens the third interlayer insulating film 13, and the shield wiring 81b is similarly a contact that opens the third interlayer insulating film 13. It is connected to the power line 116 through the hole 74. Note that the sectional view is omitted.

  When the shield wirings 81a and 81b are formed to be one each along the data line 114 as in the first embodiment, if the resistivity is relatively large or away from the constant potential connection point, There is a case where the impedance of the shield wirings 81a and 81b becomes relatively high and noise cannot be sufficiently absorbed. On the other hand, according to the fourth embodiment, since the shield wirings 81a and 81b are provided for each pixel circuit 110 and are connected to the power supply line 116, the impedance is reduced and the noise absorption capability is achieved. Can be increased.

<Fifth Embodiment>
FIG. 15 is a plan view illustrating a configuration of the pixel circuit 110 of the electro-optical device according to the fifth embodiment. This fifth embodiment is a combination of the third embodiment and the fourth embodiment, and is formed so as to cover the relay electrode 43 in plan view by changing the shape of the shield wiring 81a shown in FIG. It is a thing.
For this reason, according to the fifth embodiment, it is possible to enhance the shielding function and increase the noise absorption capability.

<Sixth Embodiment>
When the shield wiring is formed from a wiring layer different from the data line 114 as in the second embodiment, the data line 114 is not overlapped on both sides of the data line 114 but overlaps the data line 114 in plan view. It should be provided on the lower layer side.
On the other hand, if the shield wiring is connected to, for example, the power supply line 116 for each pixel circuit 110, the noise absorption capability can be improved as described in the fourth (fifth) embodiment.
Therefore, next, by combining the two, a shield wiring is formed from a wiring layer different from the data line 114, provided on the lower layer side of the data line 114 so as to overlap the data line 114 in plan view, and integrated with the power supply line 116. A sixth embodiment will be described.

FIG. 16 is a plan view illustrating a configuration of the pixel circuit 110 of the electro-optical device according to the sixth embodiment, and FIG. 17 is a partial cross-sectional view taken along line Jj in FIG.
From the first embodiment to the fifth embodiment, the shield wirings 81a and 81b are provided for each column. In the sixth embodiment, the shield wiring 81 is integrated and the power supply line 116 is also used. Yes.
As shown in FIG. 17, the shield wiring 81 that also serves as the power supply line 116 is obtained by patterning the wiring layer formed on the second interlayer insulating film 12 together with the relay electrodes 61 and 62. As shown in FIG. 16, the shape of the shield wiring 81 in plan view is wider than the data line 114 so as to overlap with the vertical data line 114 and integrated with the power supply line 116 in the horizontal direction. It is a grid.

The data line 114 is connected to the drain region 130d through the relay electrodes 61 and 41 in order, but the shield wiring 81 is formed from the same wiring layer as the relay electrode 61, so that it is necessary to avoid interference. For this reason, the data line 114 branches rightward in FIG. 16 and extends to a portion where the shield wiring 81 is not formed. A contact hole 51 is formed in the extended portion to connect the data line 114 to the relay electrode 61. As a result, the shield wiring 81 and the relay electrode 61 are electrically separated without interfering with each other.
In this example, the contact holes 51 and 71 are arranged so as to overlap at the same point when viewed in plan, but may be arranged so as to be different points (not shown).

  In the sixth embodiment, since the data line 114 is branched and extended to the right side, noise may jump into the gate node g and the source node s of the transistor 140 from the extended portion. . Therefore, in the sixth embodiment, a branch wiring 81d in which the shield wiring 81 is extended to the right side is provided between the branch portion of the data line 114 and the relay electrode 43 / gate electrode layer 21 when viewed in plan. ing. As a result, the portion extending to the right side of the data line 114, that is, noise from the vicinity of the contact hole 71 is absorbed by the branch wiring 81d before reaching each node of the transistor 140.

  According to the sixth embodiment, the shield wiring 81 is provided so as to overlap with the data line 114 in a plan view, and the potential is fixed by using the power supply line 116, so that the shield function can be enhanced. Will be.

<Seventh embodiment>
FIG. 18 is a plan view illustrating a configuration of the pixel circuit 110 of the electro-optical device according to the seventh embodiment.
As shown in this figure, in the seventh embodiment, a shield wiring 81 that also serves as a power supply line 116 covers the storage capacitor 135 (gate electrode layer 21) and the transistor 140 when viewed in plan. .
As described above, since the shield wiring 81 (power supply line 116) is formed by patterning the same wiring layer as the relay electrodes 61 and 62, it is necessary to avoid interference with the relay electrodes 61 and 62. In the seventh embodiment, the shield wiring 81 that also serves as the power supply line 116 has an open shape in the vicinity of the relay electrodes 61 and 62.
Note that the cross-sectional view of the main part of the pixel circuit 110 of the seventh embodiment is the content in which the part indicated by the broken line in FIG. 17 is added.

According to the seventh embodiment, the shield wiring 81 is provided so as to overlap the data line 114 in a plan view and covers the storage capacitor 135 and the transistor 140, and the potential is fixed by using the power supply line 116 as well. Therefore, the shield function can be further strengthened.
In the seventh embodiment, as long as the relay electrodes 61 and 62 do not interfere with each other, the opening area of the shield wiring 81 may be further narrowed. In the seventh embodiment, the shield wiring 81 covers the entire area of the storage capacitor 135 and the transistor 140 in a plan view. However, only a part of the storage capacitor 135 and the transistor 140 may be covered.

<Applications / Modifications>
The present invention is not limited to the above-described embodiments, and the following applications and modifications are possible.
For example, with respect to the configuration of the storage capacitor 135, the first interlayer insulating film 11 is sandwiched between the gate electrode layer 21 and the relay electrode 43. For example, a semiconductor layer is provided so as to overlap the gate electrode layer 21 in a plan view. The gate insulating film 10 may be sandwiched between the layer and the gate electrode layer 21. As the semiconductor layer, a source layer with an extended source region 140s may be used, or a separately patterned layer may be used. In addition, a configuration in which an interlayer insulating film or a gate insulating film is sandwiched between electrodes and wirings made of different wiring layers, or a plurality of them connected in parallel may be used as the storage capacitor 135 as a whole.
Further, regarding the position where the storage capacitor 135 is electrically inserted, other than between the gate node g and the source node s of the transistor 140, for example, between the gate node g and the common electrode 118 as shown in FIG. However, although not particularly illustrated, it may be between the gate node g and a wiring fixed to another potential.

The driving of the pixel circuit 110 is not limited to a method in which a data signal having a potential corresponding to grayscale data is simply held in the gate node g during a selection period in which the transistor 130 is in an on state. For example, during the selection period in which the transistor 130 is on, the data line 114 is set as a reference potential, and the power supply by the power supply line 116 and the common electrode 118 is switched between the first potential and the second potential. A voltage corresponding to the threshold voltage may be held in the storage capacitor 135, and then the data line 114 may be driven to have a potential corresponding to the gradation data. In addition, the potential of the data signal may be changed during the selection period, and the time change rate of the data signal at the end of the selection period may be driven to a value corresponding to the gradation data, or the source node s may have a capacitance. A ramp signal may be supplied for each row via the element, and the transistor 140 may be driven so that a set current flows.
In any drive, by providing the pixel circuit 110 with the shield wiring as in each embodiment, the potential of each node of the transistor 140 that supplies current to the light emitting element 150 varies due to noise from the data line 114. It is possible to suppress this.

  As for the shield wiring, a pattern obtained by patterning two or more different wiring layers may be used. For example, in the sixth (seventh) embodiment, the same wiring layer as the data line 114 and the relay electrode 82 is patterned to form a double structure of the shield wiring 81 (power supply line 116) and a separately formed shield wiring. Also good. For the separate shield wiring, interference with the data line 114 and the relay electrode 82 may be avoided.

  As the light emitting element 150, in addition to the OLED, an element that emits light with luminance corresponding to a current, such as an inorganic EL element or an LED (Light Emitting Diode) element, can be used.

<Electronic equipment>
Next, some electronic apparatuses to which the electro-optical device according to the invention is applied will be described.
FIG. 20 is a diagram illustrating an external appearance of a personal computer that employs the electro-optical device 1 according to the above-described embodiment as a display device. The personal computer 2000 includes the electro-optical device 1 as a display device and a main body 2010. The main body 2010 is provided with a power switch 2001 and a keyboard 2002.
In the electro-optical device 1, when an OLED is used for the light emitting element 150, an easy-to-view screen display with a wide viewing angle becomes possible.

  FIG. 21 is a diagram illustrating an appearance of a mobile phone adopting the electro-optical device 1 according to the embodiment as a display device. The cellular phone 3000 includes the electro-optical device 1 described above together with the earpiece 3003 and the mouthpiece 3004 in addition to a plurality of operation buttons 3001 and direction keys 3002. By operating the direction key 3002, the screen displayed on the electro-optical device 1 is scrolled.

  FIG. 22 is a diagram illustrating an appearance of a personal digital assistant (PDA) that employs the electro-optical device 1 according to the embodiment as a display device. A portable information terminal 4000 includes the above-described electro-optical device 1 in addition to a plurality of operation buttons 4001 and direction keys 4002. In the portable information terminal 4000, various kinds of information such as an address book and a schedule book are displayed on the electro-optical device 1 by a predetermined operation, and the displayed information is scrolled according to the operation of the direction key 4002.

  In addition to the examples shown in FIGS. 20 to 22, the electronic apparatus to which the electro-optical device according to the invention is applied includes a television, a car navigation device, a pager, an electronic notebook, electronic paper, a calculator, a word processor, a work Stations, videophones, POS terminals, printers, scanners, copiers, video players, devices equipped with a touch panel, and the like. In particular, examples of the micro display include a head-mounted display and an electronic viewfinder of a digital still camera or a video camera.

DESCRIPTION OF SYMBOLS 1 ... Electro-optical device 81, 81a, 81b ... Shield wiring, 110 ... Pixel circuit, 112 ... Scan line, 114 ... Data line, 116 ... Power supply line, 118 ... Common electrode, 130 ... Transistor, 135 ... Retention capacity, 140 ... transistor, 150 ... light emitting element, 210 ... scanning line driving circuit, 220 ... data line driving circuit, 2000 ... personal computer, 3000 ... mobile phone, 4000 ... portable information terminal.

Claims (6)

A scan line extending in a first direction;
Shield wiring,
A data line extending in a second direction intersecting the first direction;
A pixel provided corresponding to an intersection of the scanning line and the data line;
Have
The pixel is
A light emitting element;
A first transistor for controlling a current flowing in the light emitting element;
A first extending portion extending from the data line along the first direction ;
A grid- like portion and a second extending portion of the shield wiring ;
Only including,
The shield wiring is located in a layer between the data line and the first transistor when viewed in cross section,
The grid-like portion, in the pixel in a plan view, the first transistor, enclose between the extension Mashimashi portion in a first direction and said second direction extending in part,
The second extending portion extends in the first direction between the first extending portion and the first transistor in the pixel when viewed in plan. Optical device. The electro-optical device according to claim 1.
The grid-like portion, an electro-optical device, characterized in that provided in the same layer as the second extended portion. The electro-optical device according to claim 1,
An electro-optical device, wherein a constant potential is applied to the shield wiring. The electro-optical device according to any one of claims 1 to 3,
A second transistor whose conduction state is controlled according to a scanning signal supplied to the scanning line;
Said second transistor to an electro-optical apparatus characterized by being surrounded by the lattice-like portion. The electro-optical device according to any one of claims 1 to 4,
One end has a storage capacitor connected to the gate of the first transistor;
The storage capacitor is an electro-optical apparatus characterized by being surrounded by the lattice-like portion. An electronic apparatus comprising the electro-optical device according to claim 1.

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