KR102511048B1 - Organic light emitting diode display device and method for manufacturing the same - Google Patents

Abstract

The present invention relates to an OLED display device in which power supply lines are formed in a mesh structure in order to prevent a short circuit between signal lines and to uniformly supply a constant voltage to OLED elements of each sub-pixel in the entire area of the OLED display panel, and an OLED display device thereof. An OLED display device according to the present invention relates to a manufacturing method comprising a plurality of data lines arranged in a first direction, an interlayer insulating film formed on the entire surface of a substrate including the plurality of data lines, and on the plurality of data lines. A plurality of constant voltage lines disposed in the second direction, and an auxiliary constant voltage line formed on the interlayer insulating film corresponding to the stepped portion due to the stepped portion of the plurality of data lines.

Description

Organic light emitting diode display device and method for manufacturing the same {Organic light emitting diode display device and method for manufacturing the same}

The present invention relates to an organic light emitting diode (hereinafter referred to as 'OLED') display device, and in particular, an OLED display device in which short circuits between signal lines are prevented and power supply lines are formed in a mesh structure, and a manufacturing method thereof It is about.

Recently, flat panel display devices that display images using digital data include liquid crystal displays (LCDs) using liquid crystals and OLED displays using organic light emitting diodes (OLEDs). .

Among them, the OLED display device is a self-luminous device that emits light through an organic light emitting layer through recombination of electrons and holes. It has high luminance and low driving voltage, has a response time of several microseconds (μs), is easy to implement moving images, has no viewing angle limitation, and has a low temperature. It also has the advantage of being stable and can be thinned, so it is expected as a next-generation display device.

The OLED display device as described above includes an OLED display panel on which a plurality of scan lines and a plurality of data lines are arranged in different directions to display an image, and a driving circuit for driving the OLED display panel.

In the OLED display panel, a plurality of sub-pixels are defined in an area where the plurality of scan lines and the plurality of data lines cross each other, and each sub-pixel includes an OLED element composed of an organic light emitting layer between an anode and a cathode, and an OLED element. and a pixel circuit that independently drives

The pixel circuit includes a thin film transistor (TFT) for supplying a data voltage to a storage capacitor, a driving transistor for controlling a driving current according to a driving voltage charged in the storage capacitor and supplying the driving current to an OLED device, and the like. The device generates light proportional to the drive current.

In such an OLED display panel, a short circuit between signal lines must be prevented, and a constant voltage must be uniformly supplied to the OLED elements of each sub-pixel in the entire area of the OLED display panel.

In response to the above demands, the present invention provides power supply lines with a mesh structure to prevent short circuits between signal lines and to uniformly supply constant voltage to OLED elements of each sub-pixel in the entire area of an OLED display panel. Its purpose is to provide a formed OLED display device and a manufacturing method thereof.

In order to achieve the above object, the OLED display device according to the present invention arranges a plurality of constant voltage lines at the top, and when the plurality of constant voltage lines are formed, due to a step difference between a plurality of data lines formed on the lower side, the step It is characterized in that a residual film (auxiliary constant voltage line) is formed on the corresponding interlayer insulating layer so that a short circuit occurs between adjacent constant voltage lines by the auxiliary constant voltage line.

In addition, a method of manufacturing an OLED display device according to the present invention for achieving the above object includes forming a plurality of data lines in a first direction on a first interlayer insulating layer, and including the plurality of data lines forming a second interlayer insulating layer on the first interlayer insulating layer; depositing a metal layer on the second interlayer insulating layer; and selectively removing the metal layer by photolithography to form a plurality of second insulating layers in a second direction. forming one constant voltage line, and in the step of forming a plurality of first constant voltage lines, an auxiliary constant voltage line is formed on the second interlayer insulating layer corresponding to the stepped portion due to the stepped portion of the plurality of data lines. has that characteristic.

Side surfaces of the plurality of data lines and the plurality of reference voltage lines may have a taper angle of 80° or more from the substrate surface.

The OLED display device and method for manufacturing the same according to the present invention having the above characteristics have the following effects.

An OLED display device and method of manufacturing the same according to the present invention arrange a plurality of first constant voltage lines at the top, and according to manufacturing conditions of a plurality of data lines or a plurality of reference voltage lines at the bottom, a plurality of first constant voltage lines can be formed in a mesh structure. Accordingly, the first constant voltage may be uniformly provided over the entire area of the display panel.

In addition, when forming a plurality of first constant voltage lines in a mesh structure, since it is not necessary to hard bake the photoresist film pattern, the process can be simplified.

1 is a schematic structural diagram of an OLED display device according to the present invention;
2 is a circuit diagram of a sub-pixel according to the present invention;
3 is a layout diagram schematically showing each signal line of an OLED display panel according to the present invention;
4 is a cross-sectional structural diagram of an OLED display panel according to the present invention along the line II' of FIG. 3
5 is a cross-sectional structural diagram of an OLED display panel according to the present invention taken along line II-II' of FIG. 3;
6 is a cross-sectional structural diagram of an OLED display panel according to the present invention along line III-III' of FIG. 3;
7A to 7D are process cross-sectional views of the OLED display panel along line II' of FIG. 3 according to the first embodiment of the present invention.
8A to 8D are process cross-sectional views of the OLED display panel along line II-II' of FIG. 3 according to the first embodiment of the present invention.
9A to 9D are process cross-sectional views of the OLED display panel along the line III-III' of FIG. 3 according to the first embodiment of the present invention.
10A to 10B are process cross-sectional views of an OLED display panel along line III-III' in FIG. 3 according to a second embodiment of the present invention.
11A is a configuration diagram of first constant voltage lines according to the manufacturing method of the first embodiment ( FIGS. 7A to 7D , 8A to 8D , and 9A to 9D ) of the present invention.
11B is a configuration diagram of first constant voltage lines according to the manufacturing method of the second embodiment ( FIGS. 10A to 10B ) of the present invention.
12a is a constant voltage (VDD) distribution diagram according to the manufacturing method of the first embodiment ( FIGS. 7a to 7d, 8a to 8d, and 9a to 9d) of the present invention.
Figure 12b is a constant voltage (VDD) distribution diagram according to the manufacturing method of the second embodiment (Figs. 10a to 10b) of the present invention

An OLED display panel and a manufacturing method thereof according to the present invention having the above characteristics will be described in more detail with reference to the accompanying drawings.

1 is a schematic structural diagram of an OLED display device according to the present invention.

As shown in FIG. 1, the OLED display device according to the present invention includes an OLED display panel 100 in which a plurality of pixels PX are defined, and various control units and driving units 110 connected to the OLED display panel 100. ~ 140).

In the OLED display panel 100, a plurality of scan lines SCL and data lines DL are disposed on an organic or plastic substrate to cross each other, and the scan lines SCL and the data lines DL cross each other. Sub-pixels PXs displaying gradations corresponding to red, green, and blue, respectively, are defined at points. In addition, each sub-pixel PX is connected to a sensing line SSL for sensing a threshold voltage Vth and an electron mobility μ, and although not shown, the OLED display panel 100 has a power supply voltage Various lines for supplying (ELVDD) and ground voltage (ELVSS) may be further formed.

The scan lines SCL are connected to the scan driver 120 outputting the scan signal SCAN, and the data lines DL are connected to the data driver 130 outputting the data voltage Vdata.

In addition, the sensing line SSL formed on the OLED display panel 100 is connected to the sensing controller 140 that senses the electrical characteristics of the driving thin film transistor through the sink current flowing in the pixel PX. Although the drawing shows an example in which the sensing controller 140 is configured as a separate external IC from the data driver 130, an integrated IC within the data driver 130 may also be applied.

The timing controller 110 receives video data and timing signals such as a clock signal, vertical and horizontal synchronization signals, and the like from the outside to generate a scan control signal (GCS), a data control signal (DCS), and a sensing drive control signal (SCS). generate control signals such as

The timing control unit 110 is connected to an external system through a predetermined interface, receives video-related signals and timing signals output therefrom at high speed without noise, and generates the control signals. The timing controller 110 may be integrated with the data driver 130 as an integrated IC according to the design intention of the OLED display device.

In particular, the timing controller 110 of the present invention controls the pixel PX itself to compensate for the characteristic deviation according to the operator's or user's compensation control signal CC, or requests the sensing controller 140 to Control may be performed to compensate for characteristic deviation of the pixel PX.

The scan driver 120 sequentially applies the scan signal SCAN to each scan line SCL in response to the scan control signal SCS from the timing controller 110 . The scan driver 120 may be implemented as a normal shift register.

The data driver 130 receives the image signal RGB of a digital waveform applied from the timing controller 110 and generates a data voltage Vdata in the form of an analog voltage having a grayscale value that the pixel PX can process. In response to the input data control signal DCS, the data voltage Vdata is supplied to each sub-pixel PX through the data line DL.

The sensing controller 140 adjusts the threshold voltage (Vth) and movement of the driving thin film transistor (DR-TFT) immediately after power-on/off of the OLED display device or at a time point specified by other users according to the control of the timing controller 110. The external compensation method and the internal compensation method are simultaneously sensed, and the sensed result is reflected in the data voltage (Vdata) to compensate for the characteristic deviation of the driving thin film transistor (DR-TFT).

As an example, the output current value of the driving transistor in the normal sub-pixel PX reflects the threshold voltage and electron mobility characteristics of the driving transistor. Accordingly, when deterioration occurs, the current value by the driving transistor is changed, and the change value of the threshold voltage and mobility can be measured by sinking the current. Accordingly, the sensing controller 140 compensates for the change in characteristics of the driving transistor by reflecting the measured result to the data voltage Vdata.

2 is a circuit diagram of a sub-pixel for sensing a change amount of a threshold voltage (Vth) of a driving transistor according to the present invention.

As shown in FIG. 2 , each sub-pixel of the OLED display panel according to the present invention includes an organic light emitting diode (OLED) and a pixel circuit that drives the organic light emitting diode.

The pixel circuit includes first and second switching TFTs (T1, T2), a storage capacitor (Cst), and a driving TFT (DT).

The first switching TFT (T1) charges the storage capacitor (Cst) with a data (DATA) voltage in response to a scan pulse (Scan). The driving TFT (DT) controls the amount of current supplied to the OLED according to the data voltage charged in the storage capacitor (Cst) to adjust the amount of light emitted from the OLED. The second switching TFT (T2) senses the threshold voltage and mobility of the driving TFT (DT) in response to a sensing signal.

The organic light emitting diode (OLED) may include a first electrode (eg, an anode electrode or a cathode electrode), an organic light emitting layer, and a second electrode (eg, a cathode electrode or an anode electrode).

The storage capacitor (Cst) is electrically connected between the gate electrode (gate) and the source electrode (source) of the driving TFT (DT), and a data voltage corresponding to the image signal voltage or a voltage corresponding thereto is supplied for one frame time. can keep you

The method of sensing the threshold voltage (Vth) of the driving TFT (DT) is to operate the driving TFT (DT) in a source follower manner and then receive the source voltage of the driving TFT (DT) as a sensing voltage. Based on the sensing voltage, the amount of change in the threshold voltage of the driving TFT (DT) is detected. The amount of change in the threshold voltage of the driving transistor is determined according to the magnitude of the sensing voltage, through which an offset value for data compensation is obtained.

Therefore, the gate electrode of the first switching TFT (T1) is connected to the scan line (SL) supplying the scan pulse (Scan), and the drain electrode of the first switching TFT (T1) supplies the data voltage (Data). A data line DL is connected, and a source electrode of the first switching TFT (T1) is connected to a first electrode of the storage capacitor (Cst) and a gate electrode of the driving TFT (DT).

The drain electrode of the driving TFT (DT) is connected to the first constant voltage line (EVDD), and the source electrode of the driving TFT (DT) is connected to the second electrode of the storage capacitor (Cst) and the organic light emitting diode (OLED). It is connected to the first electrode (anode). A second electrode (cathode) of the organic light emitting diode (OLED) is connected to a second constant voltage line (EVSS).

The gate electrode of the second switching TFT (T2) is connected to the sensing line supplying the sensing signal (Sense), and the drain electrode of the second switching TFT (T2) is connected to the source electrode of the driving TFT (DT). and the source electrode of the second switching TFT (T2) is connected to the reference voltage line (Ref).

As described above, each sub-pixel configured as described above includes a scan line SL, a data line DL, a first constant voltage line EVDD, a second constant voltage line EVSS, and a reference voltage line Ref. , these lines share a plurality of sub-pixels.

FIG. 3 is a layout diagram schematically illustrating each signal line of the OLED display panel according to the present invention, FIG. 4 is a cross-sectional view of the OLED display panel according to the present invention along the line II' of FIG. 3, and FIG. 3 is a cross-sectional structural diagram of the OLED display panel according to the present invention along line II-II', and FIG. 6 is a cross-sectional structural diagram of the OLED display panel according to the present invention along line III-III' in FIG.

That is, FIG. 4 is a cross-sectional view of an OLED display panel on a data line line, FIG. 5 is a cross-sectional structure diagram of an OLED display panel on a first constant voltage line line, and FIG. 6 is a cross-sectional structure view of an OLED display panel adjacent to a first constant voltage line line. am.

As shown in FIG. 3, in the OLED display panel according to an embodiment of the present invention, a plurality of scan lines SL1 and SL2 and first constant voltage lines EVDD1 and EVDD2 are arranged at regular intervals in the horizontal direction, A plurality of data lines DL1 , DL2 , DL3 , and DL4 and a reference voltage line Vref are disposed in the vertical direction.

In this arrangement, the plurality of scan lines SL1 and SL2 are disposed at the bottom, the plurality of data lines DL1, DL2, DL3, and DL4 and the reference voltage line Vref are disposed thereon, and The two first constant voltage lines EVDD1 and EVDD2 are disposed at the top.

That is, as shown in FIGS. 4 to 6, a buffer layer 20 is formed on a substrate (not shown), and an active layer 21 of each TFT of sub-pixels is formed on the buffer layer 20. and a gate insulating film 22 is formed on the active layer 21 .

The scan lines SL1 and SL2 23 are formed in a horizontal direction on the gate insulating layer 22, and a first interlayer insulating layer 24 is formed on the entire surface of the substrate including the scan lines SL1 and SL2 23 is formed

The plurality of data lines DL1, DL2, DL3, and DL4 25 and the plurality of reference voltage lines Vref1 and Vref2 (shown in FIGS. 4 to 6) on the first interlayer insulating layer 24 in the vertical direction 3) is formed, and a second interlayer insulating layer is formed on the entire surface of the substrate including the plurality of data lines DL1, DL2, DL3, and DL4 25 and the plurality of reference voltage lines Vref1 and Vref2. 26) is formed.

Also, the plurality of first constant voltage lines EVDD1 and EVDD2 27 are formed on the second interlayer insulating layer 26 in a horizontal direction.

Here, the buffer layer 20 is formed to a thickness of about 2500 to 3500 Å, the active layer 21 is formed to a thickness of about 250 to 750 Å, and the gate insulating film 22 is formed to a thickness of about 750 to 1250 Å. The scan lines SL1 and SL2 23 are formed to a thickness of about 1500 to 2500 Å, and the first interlayer insulating layer 24 is formed to a thickness of about 3000 to 5000 Å.

In addition, the plurality of data lines DL1, DL2, DL3, and DL4 25 and the plurality of reference voltage lines Vref1 and Vref2 are formed to a thickness of about 3000 to 5000 Å, and the second interlayer insulating layer 26 ) is formed to a thickness of about 4000 to 6000 Å, and the plurality of first constant voltage lines EVDD1 and EVDD2 27 are formed to a thickness of about 4000 to 6000 Å.

In this way, in order to form the plurality of first constant voltage lines (EVDD1, EVDD2) 27, a metal layer is deposited on the second interlayer insulating layer 26, and photo-lithography is used to form the Pattern the metal layer. That is, the plurality of first constant voltage lines EVDD1 and EVDD2 27 are formed by removing unnecessary portions of the metal layer.

At this time, due to the step difference between the plurality of data lines (DL1, DL2, DL3, DL4) 25 and the plurality of reference voltage lines (Vref1, Vref2) formed below the second interlayer insulating layer 26, the A step is generated in the second interlayer insulating layer 26 on the corner portion of the plurality of data lines DL1, DL2, DL3, and DL4 25 and the plurality of reference voltage lines Vref1 and Vref2, and the second interlayer During the patterning of the metal layer for forming the plurality of first constant voltage lines (EVDD1 and EVDD2) 27 on the stepped portion of the insulating layer 26, the metal layer is not completely removed and a remaining film (hereinafter referred to as 'auxiliary constant voltage line') remains.

As such, the auxiliary constant voltage line remains along the corner portions of the plurality of data lines (DL1, DL2, DL3, DL4) 25 and the plurality of reference voltage lines (Vref1, Vref2), so that the adjacent first constant voltage line (EVDD1, EVDD2) are electrically connected to each other by the auxiliary constant voltage line. Accordingly, since the first constant voltage lines EVDD1 and EVDD2 have a mesh structure by the auxiliary constant voltage line, the first constant voltage can be uniformly provided over the entire area of the display panel.

The remaining film (auxiliary constant voltage line) has a smaller thickness than that of the constant voltage line and a narrower width than that of the constant voltage line. In addition, the remaining film (auxiliary constant voltage line) has a height lower than a stepped portion between an interlayer insulating film on a data line and an interlayer insulating film on which a data line is not formed.

In the process of forming each signal line of the OLED display panel, a residual film may or may not be formed depending on process conditions.

A method of manufacturing an OLED display panel according to the present invention is described as follows.

7A to 7D are process cross-sectional views of an OLED display panel according to the present invention along the line II' of FIG. 3 according to the first embodiment of the present invention, and FIGS. 9A to 9D are process cross-sectional views of the OLED display panel according to the present invention along line III-III' in FIG. 3 .

As shown in FIGS. 7A, 8A, and 9A, a buffer layer 20 is formed on a substrate (not shown) to a thickness of about 2500 to 3500 Å (eg, 3000 Å). And on the buffer layer 20, the active layer 21 of each TFT having a thickness of about 250 to 750 Å (eg, 500 Å) and a gate insulating film of a thickness of about 750 to 1250 Å (eg, 1000 Å) ( 22) are formed sequentially.

And, as shown in FIGS. 7B, 8B, and 9B, a first metal layer is deposited on the gate insulating film 22 to a thickness of about 1500 to 2500 Å (eg, 2000 Å), and the first metal layer is deposited by photolithography. A plurality of scan lines SL1 , SL2 , and 23 are formed in the horizontal direction by selectively removing the first metal layer.

A first interlayer insulating layer 24 is formed on the gate insulating layer 22 including the plurality of scan lines SL1 , SL2 , and 23 to a thickness of about 3000 to 5000 Å (eg, 4000 Å). Then, a second metal layer 25a is formed on the first interlayer insulating film 34 to a thickness of about 3000 to 5000 Å (eg, 4000 Å), and a photoresist film (PR) is formed on the second metal layer 25a. is deposited, and the photoresist layer PR is patterned through exposure and development processes.

As shown in FIGS. 7C, 8C, and 9C, the second metal layer 25a is selectively removed using the patterned photoresist film PR as a mask to form a plurality of data lines 25 or a plurality of data lines 25 in a vertical direction. form two reference voltage lines. At this time, side surfaces of the plurality of data lines 25 or the plurality of reference voltage lines have a taper angle of 80° or more. That is, the side surfaces of the plurality of data lines or the plurality of reference voltage lines 235 have a taper angle of about 80° or more from the substrate surface.

As shown in FIGS. 7D, 8D and 9D, the patterned photoresist film (PR) is removed, and the first interlayer insulating layer 24 including the plurality of data lines 25 or the plurality of reference voltage lines is formed. The second interlayer insulating layer 26 is formed to a thickness of about 4000 to 6000 Å (eg, 5000 Å). Then, a third metal layer is deposited on the second interlayer insulating layer 26 to a thickness of about 4000 to 6000 Å (eg, 5000 Å), and the third metal layer is selectively removed by photolithography in the horizontal direction. A plurality of first constant voltage lines 27 are formed.

In this way, when the third metal layer is selectively removed to form a plurality of first constant voltage lines 27 in the horizontal direction, the plurality of data lines 25 or Since the sides of the plurality of reference voltage lines have a taper angle of about 80° or more from the substrate surface, the plurality of data lines DL1, DL2, DL3, and DL4 25 and the plurality of reference voltage lines A high step is generated in the second interlayer insulating layer 26 on a corner portion, and the plurality of first constant voltage lines EVDD1 and EVDD2 27 are formed on the step portion of the second interlayer insulating layer 26. During patterning of the third metal layer to form the third metal layer, the third metal layer is not completely removed and a residual film (auxiliary constant voltage line 27a) remains.

As such, residual films (auxiliary constant voltage lines) remain along the corners of the plurality of data lines (DL1, DL2, DL3, and DL4) 25 and the plurality of reference voltage lines (Vref1, Vref2), so that the adjacent first constant voltage line ( EVDD1 and EVDD2) are electrically connected to each other by the auxiliary constant voltage line. Accordingly, since the first constant voltage lines EVDD1 and EVDD2 have a mesh structure by the auxiliary constant voltage line, the first constant voltage can be uniformly provided over the entire area of the display panel.

Meanwhile, FIGS. 10A to 10B are process cross-sectional views of the OLED display panel along line III-III' in FIG. 3 according to the second embodiment of the present invention.

As described in FIG. 9B, after patterning the photoresist film (PR) on the second metal layer 25a, as shown in FIG. 10A, the patterned photoresist film (PR) is hard baked. . The hard baking process is heat-treated at a temperature of 100 ° C to 200 ° C for about 10 minutes to 50 minutes.

Then, the second metal layer 25a is selectively removed using the hard-baked photoresist film (PR) pattern as a mask to form a plurality of data lines 25 or a plurality of reference voltage lines in a vertical direction.

In this way, when the second metal layer is selectively removed using the hard-baked photoresist film (PR) pattern as a mask, the side surfaces of the plurality of data lines or the plurality of reference voltage lines 35 are about 80 degrees from the substrate surface. It has a slope of less than °.

As shown in FIG. 10B, the hard-baked photoresist film PR is removed, and a second interlayer insulating layer 24 is formed on the first interlayer insulating layer 24 including the plurality of data lines 25 or the plurality of reference voltage lines. An insulating layer 26 is formed. At this time, since the side surface of the plurality of data lines 25 or the plurality of reference voltage lines has an inclined surface of about 80° or less from the substrate surface, the corner portion of the plurality of data lines 25 or the plurality of reference voltage lines Along , the second interlayer insulating layer 26 also has a step. However, the step of the second interlayer insulating layer 26 has a gentle slope.

Then, a third metal layer is deposited on the second interlayer insulating layer 26, and the third metal layer is selectively removed by photolithography to form a plurality of first constant voltage lines 27 in a horizontal direction.

In this way, since the plurality of data lines 25 or the plurality of reference voltage lines are formed using the hard-baked photoresist film (PR) pattern as a mask, the plurality of data lines 25 or the plurality of reference voltage lines The side surface has an inclined surface of about 80 degrees or less from the substrate surface. That is, since the side surfaces of the plurality of data lines 25 or the plurality of reference voltage lines of the second embodiment of the present invention have a more gentle slope compared to the first embodiment of the present invention, the second interlayer insulating layer (26) also has a gentle step at the corner of the plurality of data lines 25 or the plurality of reference voltage lines.

As such, since the second interlayer insulating film has a gentle step at the corners of the plurality of data lines 25 or the plurality of reference voltage lines, the third metal layer is selectively removed to generate a plurality of first constant voltages in the horizontal direction. When the line 27 is formed, no residual film remains on the stepped portion of the second interlayer insulating layer 26 regardless of the stepped portion of the plurality of data lines 25 or the plurality of reference voltage lines. Therefore, no auxiliary constant voltage line is formed.

11A is a configuration diagram of first constant voltage lines according to the manufacturing method of the first embodiment ( FIGS. 7A to 7D , 8A to 8D , and 9A to 9D ) of the present invention, and FIG. 11B is a configuration diagram of the second embodiment of the present invention. It is a configuration diagram of the first constant voltage lines according to the manufacturing method of ( FIGS. 10A to 10B ).

As shown in FIG. 11A, according to the manufacturing method of the first embodiment (FIGS. 7A to 7D, 8A to 8D, and 9A to 9D) of the present invention, there is a residual film between the adjacent first constant voltage lines EVDD. Since the auxiliary constant voltage line is formed by the auxiliary constant voltage line, the first constant voltage lines EVDD have a mesh structure, and thus the first constant voltage can be uniformly provided over the entire area of the display panel.

Conversely, as shown in FIG. 11B, according to the manufacturing method of the second embodiment (FIGS. 10A to 10B) of the present invention, no residual film (auxiliary constant voltage line) is formed between the adjacent first constant voltage lines EVDD. The first constant voltage lines EVDD do not have a mesh structure.

12A is a constant voltage (VDD) distribution diagram according to the manufacturing method of the first embodiment (FIGS. 7A to 7D, 8A to 8D, and 9A to 9D) of the present invention, and FIG. 12B is a diagram of the second embodiment (FIGS. It is a constant voltage (VDD) distribution diagram according to the manufacturing method of 10a to 10b).

As compared with FIGS. 12A and 12B, when a voltage of 10V is applied as a constant voltage (VDD), the manufacturing method of the first embodiment (FIGS. 7A to 7D, 8A to 8D, and 9A to 9D) of the present invention. According to, it can be seen that the IR drop voltage width is reduced and the luminance is improved.

As described in FIGS. 7A to 7D, 8A to 8D, 9A to 9D, and 10A to 10B, the plurality of first constant voltage lines EVDD1 and EVDD2 are disposed at the top, and the plurality of data lines or According to manufacturing conditions of the plurality of reference voltage lines, the plurality of first constant voltage lines EVDD1 and EVDD2 may be formed in a mesh structure. Accordingly, the first constant voltage may be uniformly provided over the entire area of the display panel.

In addition, when forming the plurality of first constant voltage lines EVDD1 and EVDD2 in a mesh structure, it is not necessary to hard bake the photoresist film pattern, and thus the process can be simplified.

The present invention described above is not limited to the above-described embodiments and the accompanying drawings, and it is common in the technical field to which the present invention belongs that various substitutions, modifications, and changes are possible within a range that does not deviate from the technical spirit of the present invention. It will be clear to those who have knowledge of

20: buffer layer 21: active layer
22: gate insulating film 24, 26: interlayer insulating film
25: a plurality of data lines 27: first constant voltage line
27a: remaining film

Claims (9)

a plurality of data lines disposed in a first direction and having a thickness of 3000 Å to 5000 Å;
an interlayer insulating film formed on the entire surface of the substrate including the plurality of data lines and having a thickness of 4000 Å to 6000 Å;
a plurality of constant voltage lines disposed on the plurality of data lines in a second direction and having a thickness of 4000 Å to 6000 Å; and,
An auxiliary constant voltage line formed on the interlayer insulating film corresponding to the stepped portion due to the stepped portion of the plurality of data lines;
The auxiliary constant voltage line does not overlap with the data line, has a smaller thickness than the constant voltage line, and has a narrower width than the constant voltage line. According to claim 1,
Side surfaces of the plurality of data lines have a taper angle of 80 ° or more from the substrate surface. According to claim 1,
An OLED display device further comprising a plurality of scan lines disposed below the plurality of data lines in the second direction. According to claim 1,
An OLED display device in which a short is generated between adjacent constant voltage lines by the auxiliary constant voltage line. A buffer layer formed on the substrate;
an active layer formed on the buffer layer;
a gate insulating layer formed on the active layer;
a plurality of scan lines formed on the gate insulating layer in a first direction;
a first interlayer insulating layer formed on the entire surface of the substrate including the plurality of scan lines;
a plurality of data lines formed on the first interlayer insulating layer in a second direction and having a thickness of 3000 Å to 5000 Å;
formed on the first interlayer insulating film including the plurality of data lines;
a second interlayer insulating layer having a thickness of 4000 Å to 6000 Å;
a plurality of first constant voltage lines formed on the second interlayer insulating layer in a transverse direction and having a thickness of 4000 Å to 6000 Å; and
An auxiliary constant voltage line formed on the second interlayer insulating film corresponding to the stepped portion due to the stepped portion of the plurality of data lines,
The auxiliary constant voltage line does not overlap with the data line, has a smaller thickness than the first constant voltage line, and has a narrower width than the first constant voltage line. According to claim 5,
Side surfaces of the plurality of data lines have a taper angle of 80 ° or more from the substrate surface. forming a plurality of data lines having a thickness of 3000 Å to 5000 Å in a first direction on the first interlayer insulating layer;
forming a second interlayer insulating layer having a thickness of 4000 Å to 6000 Å on the first interlayer insulating layer including the plurality of data lines; and
depositing a metal layer to a thickness of 4000 Å to 6000 Å on the second interlayer insulating layer, and forming a plurality of first constant voltage lines in a second direction by selectively removing the metal layer by photolithography;
In the step of forming a plurality of first constant voltage lines, an auxiliary constant voltage line is formed on the second interlayer insulating film corresponding to a stepped portion due to a stepped portion of the plurality of data lines;
The auxiliary constant voltage line does not overlap with the data line, has a smaller thickness than the first constant voltage line, and has a narrower width than the first constant voltage line. According to claim 7,
In the step of forming the plurality of data lines, side surfaces of the plurality of data lines have a taper angle of 80° or more from the substrate surface. According to claim 7,
A method of manufacturing an OLED display device in which a short is generated between adjacent constant voltage lines by the auxiliary constant voltage line.

Images