JP2015075717A - Electro-optic device, method for manufacturing electro-optic device, and electronic apparatus - Google Patents

Abstract

PROBLEM TO BE SOLVED: To reduce an area of a contact region (a region not contributing to display) that connects a transistor and a pixel electrode.SOLUTION: An electro-optic device is provided, which includes: a first relay electrode 7 connected to a third transistor 23; an interlayer insulating layer 25 covering the first relay electrode 7; a power source line 14 disposed in contact with the interlayer insulating layer 25; a first insulating film 1 laminated on a surface of the power source line 14 and on a pixel electrode 31 side; a first opening CT1 having a wall surface CT1a; a second insulating film 2 covering the wall surface CT1a; a second opening CT2 formed inside the first opening CT1 interposing the second insulating film 2; a second relay electrode 8 covering at least the inside of the second opening CT2; and a conductive material 9 filling the inside of the second relay electrode 8. The pixel electrode 31 covers at least the first opening CT1 in a plan view and is electrically connected to the first relay electrode 8 via the conductive material 9 and the second relay electrode 8 disposed inside the second opening CT2.

Description

  The present invention relates to an electro-optical device, a method for manufacturing the electro-optical device, and an electronic apparatus in which the electro-optical device is mounted.

As an example of an electro-optical device, for example, an organic EL device in which pixels having organic electroluminescence (hereinafter referred to as organic EL) elements are arranged in a matrix is proposed (Patent Document 1).
In the organic EL device described in Patent Document 1, a portion where a pixel electrode, a light emitting functional layer, and a common electrode are stacked (light emitting portion), a source electrode of a driving transistor, an electrode (relay electrode), and a pixel electrode are stacked. A signal is supplied from the driving transistor to the pixel electrode in the contact portion, and the light emitting functional layer of the light emitting portion emits light. The pixel electrode, the driving transistor, the relay electrode, and the like are formed through a photolithographic method, that is, a photoetching process such as resist coating, exposure (alignment), development, and etching. Further, in the organic EL device described in Patent Document 1, since the resistance of the common electrode is reduced by the auxiliary wiring, high-performance display without display unevenness is provided.

JP 2009-199868 A

  The light emitting portion in which the pixel electrode, the light emitting functional layer, and the common electrode are stacked serves as a region contributing to display, and the contact portion in which the source electrode, the relay electrode, and the pixel electrode are stacked serves as a region that does not contribute to display. In order to realize a bright display, it is necessary to increase a region (light emitting portion) contributing to display and to reduce a region (contact portion) not contributing to display. Since the contact part is formed through a photo-etching process such as resist coating, exposure (alignment), development, etching, etc., for example, the state of the exposure apparatus or the thermal contraction of the substrate affects the alignment error and dimensional variation. Etc. occur. For this reason, it is necessary to form the components (electrodes, contact holes, etc.) of the contact portion with a margin (large dimension) that is not easily affected by the alignment error or the dimension variation. Therefore, if the contact portion is reduced in size, the electrical characteristics (for example, contact resistance) may fluctuate due to the influence of the alignment error and the dimensional variation. Therefore, it is difficult to form a minute contact portion. There was a problem.

  SUMMARY An advantage of some aspects of the invention is to solve at least a part of the problems described above, and the invention can be implemented as the following forms or application examples.

  Application Example 1 An electro-optical device according to this application example includes a base material provided with a transistor, a display pixel electrode that is disposed on the first surface side of the base material and is driven by the transistor, An electro-optical device having a first relay electrode electrically connected to the transistor, an interlayer insulating layer covering the first relay electrode, and between the interlayer insulating layer and the pixel electrode. A conductive layer provided in contact with the interlayer insulating layer, a first insulating film stacked on the pixel electrode side on the surface of the conductive layer, and a first layer from the first surface toward the pixel electrode A first opening penetrating the first insulating film and the conductive film, a second insulating film covering the wall surface, and the second insulating film sandwiched between the first insulating film and the conductive film. A first portion formed inside the first opening and continuous to the first portion A second opening formed to reach the first relay electrode, a second opening that covers at least the inside of the second opening, and the second relay electrode The pixel electrode covers at least the first opening in a plan view, and the conductive material provided on the inner side of the second opening and the first electrode. The second relay electrode is electrically connected to the first relay electrode.

  The electro-optical device according to this application example includes a first opening formed by the first insulating film and the wall surface of the conductive film, and a wall surface of the second insulating film formed inside the first opening ( And a second opening composed of a wall surface (second portion) of the interlayer insulating layer. In other words, the second opening is provided inside the first opening with the second insulating film interposed therebetween, and the dimension between the first opening and the second opening is the second insulation. This is the film thickness (dimension in the direction crossing the first direction). For this reason, the opening dimension of the second opening (the dimension in the direction intersecting the first direction) is the second dimension from the opening dimension of the first opening (the dimension in the direction intersecting the first direction). The dimension is obtained by subtracting the dimension twice as large as the thickness of the insulating film. As described above, in the electro-optical device according to this application example, the opening size of the second opening is automatically (self-aligned) based on the opening size of the first opening and the thickness of the second insulating film. A) to be determined.

  For example, when the second opening is formed inside the first opening by using a photoetching process, the first opening and the second opening are avoided in order to avoid the influence of the alignment error of the exposure apparatus. It is necessary to set the dimension between the two parts at least larger than the alignment error. That is, it is necessary to set the dimension between the first opening and the second opening to a dimension including an alignment error in addition to the film thickness of the second insulating film. Therefore, in the electro-optical device according to this application example, it is not necessary to form the second opening inside the first opening in consideration of the alignment error, and therefore, compared with the case where the photo-etching process is used. Thus, the dimension (interval) between the first opening and the second opening can be reduced. For example, when the first opening is formed with a minimum size that can be formed by a known technique, the second opening is automatically (self-exposed inside the first opening with the second insulating film interposed therebetween. Therefore, a smaller second opening (contact hole) can be formed with high accuracy inside the first opening having the smallest dimension.

  The second opening is a contact hole for electrically connecting the pixel electrode and the first relay electrode. As described above, the electro-optical device according to this application example has a configuration in which a second opening (contact hole) smaller than that formed using the photoetching process can be formed. Therefore, in the electro-optical device according to this application example, it is possible to reduce a contact portion that electrically connects the pixel electrode and the first relay electrode, that is, a region that does not contribute to display and a region that contributes to display. Therefore, a brighter display can be provided.

  Application Example 2 In the electro-optical device according to the application example, it is preferable that the second relay electrode is provided wider than the first opening in a plan view.

  A signal supplied from the transistor to the pixel electrode causes light emission or modulation on the pixel electrode side. Further, the transistor is arranged on the opposite side to the side where the pixel electrode is arranged (the side where light emission or modulation occurs) across the first opening. Since the first opening is shielded from light by the second relay electrode provided wider than the first opening in plan view, the light emission or modulation described above passes through the first opening. Thus, adverse effects on the operation of the transistor are suppressed.

  Application Example 3 In the electro-optical device according to the application example, the conductive layer is formed of a light-reflective material, and the first surface side of the base material is formed along the first direction along the first direction. A light emitting region in which a conductive layer, an optical distance adjusting layer, the pixel electrode, a light emitting functional layer, and a counter electrode are stacked in this order is disposed, and the optical distance adjusting layer has a first layer thickness. A pixel layer electrode having a portion, a second layer thickness portion thicker than the first layer thickness portion, and a third layer thickness portion thicker than the second layer thickness portion. Are provided in the first pixel electrode provided in the first layer thickness portion, in the second pixel electrode provided in the second layer thickness portion, and in the third layer thickness portion. It is preferable that the third pixel electrode is provided.

  The electro-optical device according to this application example has an optical resonance structure in which a light-reflective conductive layer (light-reflective layer), an optical distance adjustment layer, a pixel electrode, a light emitting functional layer, and a counter electrode are stacked in this order. ing. For this reason, the light emitted from the light emitting functional layer reciprocates between the light reflecting layer and the counter electrode, resonates according to the optical distance between the light reflecting layer and the counter electrode, and light of a specific wavelength is transmitted. Amplified. The optical distance varies depending on the thickness of the optical distance adjusting layer. Since the optical distance adjusting layer has a first layer thickness portion, a second layer thickness portion, and a third layer thickness portion, light of three types of resonance wavelengths is emitted. For example, by setting the film thickness of the optical distance adjustment layer so that light of three wavelengths of blue, green, and red is amplified, the colors of blue, green, and red light emitted from the light emitting functional layer The purity can be increased and a vivid display can be provided.

  Application Example 4 In the electro-optical device according to the application example, the first insulating film is provided over a region where the pixel electrode is disposed, and forms a part of the optical distance adjustment layer. It is preferable.

  Since the first insulating film forms part of the optical distance adjusting layer, the optical distance adjusting layer is formed as compared with the case where the optical distance adjusting layer is formed separately from the first insulating film. The process can be simplified.

  Application Example 5 In the electro-optical device according to the application example, the first insulating film is disposed between an outer edge of the second relay electrode and the first opening in a plan view. Is preferred.

  The first insulating film is disposed between the outer edge of the second relay electrode and the first opening in plan view. That is, the optical distance adjustment layer disposed between the light reflection layer and the pixel electrode does not include the first insulating film. Therefore, variations in film thickness and variations occurring in the process of forming the first insulating film do not affect the optical distance adjustment layer.

  Application Example 6 In the electro-optical device according to the application example, the optical distance adjustment layer is formed by sequentially stacking the first insulating film, the third insulating film, and the first insulating film, which are sequentially stacked along the first direction. 4, the first layer thickness portion is composed of the first insulating film, and the second layer thickness portion is the first insulating film and the fourth insulating film. The third layer thickness portion is composed of the first insulating film, the third insulating film, and the fourth insulating film, and the constituent material of the third insulating film and the The constituent material of the fourth insulating film is preferably silicon oxide.

  The portion of the first layer thickness is composed of the first insulating film, the portion of the second layer thickness is composed of the first insulating film and the fourth insulating film (silicon oxide), and the third layer thickness This portion is composed of a first insulating film, a third insulating film (silicon oxide), and a fourth insulating film (silicon oxide). Since silicon oxide has excellent optical properties (for example, light transmittance), at least the second layer thickness portion and the third layer thickness portion having silicon oxide also have excellent optical properties.

  Application Example 7 In the electro-optical device according to the application example described above, the optical distance adjustment layer includes a fifth insulating film, a sixth insulating film, and a seventh layer, which are sequentially stacked along the first direction. The first layer thickness portion is composed of the fifth insulation film, and the second layer thickness portion is composed of the fifth insulation film and the seventh insulation film. The third layer thickness portion is composed of the fifth insulating film, the sixth insulating film, and the seventh insulating film, and the constituent material of the fifth insulating film is silicon nitride It is preferable that the constituent material of the sixth insulating film and the seventh insulating film is silicon oxide.

  The first layer thickness portion is composed of a fifth insulating film (silicon nitride), and the second layer thickness portion is composed of a fifth insulating film (silicon nitride) and a seventh insulating film (silicon oxide). The third layer thickness portion is composed of a fifth insulating film (silicon nitride), a sixth insulating film (silicon oxide), and a seventh insulating film (silicon oxide). Since silicon nitride and silicon oxide have excellent optical properties (for example, light transmittance), the first layer thickness portion, the second layer thickness portion, and the third layer thickness portion are also excellent. Has optical properties.

  Application Example 8 In the electro-optical device according to the application example described above, the optical distance adjustment layer is laminated in order along the first direction, the eighth insulating film, the ninth insulating film, and the tenth film. The first layer thickness portion is composed of the tenth insulating film, and the second layer thickness portion is composed of the ninth insulating film and the tenth insulating film. And the third layer thickness portion is composed of the eighth insulating film, the ninth insulating film, and the tenth insulating film, and the eighth insulating film and the ninth insulating film. Preferably, the constituent material is silicon oxide, and the constituent material of the tenth insulating film is silicon nitride.

  The first layer thickness portion is composed of a tenth insulating film (silicon nitride), and the second layer thickness portion is composed of a ninth insulating film (silicon oxide) and a tenth insulating film (silicon nitride). The third layer thickness portion is composed of an eighth insulating film (silicon oxide), a ninth insulating film (silicon oxide), and a tenth insulating film (silicon nitride). Since silicon nitride and silicon oxide have excellent optical properties (for example, light transmittance), the first layer thickness portion, the second layer thickness portion, and the third layer thickness portion are also excellent. Has optical properties.

  Application Example 9 In the electro-optical device according to the application example, the interlayer insulating layer includes at least a silicon oxide film, and the constituent material of the first insulating film and the second insulating film is silicon nitride. preferable.

  Silicon oxide and silicon nitride are excellent in workability, and a fine pattern can be easily formed by, for example, a dry etching method. Therefore, a minute first opening can be formed through at least the first insulating film (silicon nitride) by dry etching. Further, a minute second opening can be formed inside the first opening by passing through the second insulating film (silicon nitride) and the interlayer insulating layer including at least the silicon oxide film by dry etching. it can.

  Application Example 10 In the electro-optical device according to the application example, it is preferable that the conductive material is tungsten and the second relay electrode is titanium nitride.

  Tungsten is excellent in workability and heat resistance, and is preferable as a material (conductive material) filling the inner surface of the second relay electrode. Titanium nitride is excellent in adhesiveness with the first relay electrode and the conductive material, and suppresses mutual diffusion between the material constituting the first relay electrode and the material constituting the conductive material. Therefore, by disposing titanium nitride (second relay electrode) between the first relay electrode and the conductive material, a contact portion with stable electrical connection is formed.

  Application Example 11 An electronic apparatus according to this application example includes the electro-optical device described in the application example.

  An electronic apparatus according to this application example includes the electro-optical device described in the application example, and can provide a bright and vivid display by a small contact portion and an optical resonance structure provided in the electro-optical device. For example, the electro-optical device described in the application example can be applied to an electronic apparatus having a display unit such as a head-mounted display, a head-up display, an electronic viewfinder of a digital camera, a portable information terminal, or a navigator.

  Application Example 12 An electro-optical device manufacturing method according to this application example includes a base material provided with a transistor and a display pixel that is disposed on the first surface side of the base material and is driven by the transistor. A first relay electrode electrically connected to the transistor, an interlayer insulating layer covering the first relay electrode, the interlayer insulating layer, and the electrode A conductive layer in contact with the interlayer insulating layer provided between the pixel electrode and a first insulating film in contact with the conductive layer; and the pixel electrode in the conductive layer and the first insulating film. The anisotropic etching in the second direction from the first to the first surface is performed, and the wall surface formed of the etching surface of the conductive layer and the first insulating film along the second direction reaches the interlayer insulating layer. Forming the first opening and the wall surface Forming a second insulating film having a covering portion and a portion covering the surface of the interlayer insulating layer; anisotropic etching in the second direction on the second insulating film and the interlayer insulating layer; A first portion in the first opening, the etching surface of the second insulating film reaching the interlayer insulating film, and an etching surface of the interlayer insulating layer in the first portion. A step of forming a second opening made of a second portion which is continuous and reaches the first relay electrode; and covers the inner side of the second opening and covers the first opening in plan view. Forming a second relay electrode wider than the portion, filling the inner surface of the second relay electrode with a conductive material, covering at least the first opening in a plan view, and at least the conductive material Forming the pixel electrode in contact with The features.

  The second insulating film has a portion covering the wall surface along the second direction and a portion covering the surface of the interlayer insulating layer. Furthermore, when the wall surface and the surface of the interlayer insulating layer are covered with the second insulating film having a substantially equal thickness (film thickness), the dimension along the second direction is the portion of the second insulating film covering the wall surface. Is a dimension obtained by adding the film thickness of the first insulating film, the film thickness of the conductive layer, and the film thickness of the second insulating film, and the dimension in the direction intersecting the second direction is that of the second insulating film. The dimension corresponds to the film thickness. In the second insulating film covering the surface of the interlayer insulating layer, the dimension along the second direction is a dimension corresponding to the film thickness of the second insulating film. Accordingly, the dimension along the second direction of the second insulating film covering the wall surface is larger than the dimension along the second direction of the second insulating film covering the surface of the interlayer insulating layer. . As described above, the second insulating film includes a portion having a large dimension along the second direction (a portion covering the wall surface) and a portion having a small dimension along the second direction (a portion covering the surface of the interlayer insulating layer). ).

When anisotropic etching in the second direction is performed on the second insulating film and the interlayer insulating layer, the second insulating film and the interlayer insulating layer are moved in the second direction as compared with the second insulating film having a large dimension along the second direction. Since the second insulating film having a small dimension along the second direction is removed quickly, the second insulating film having a large dimension along the second direction is used as an etching mask to reduce the small dimension along the second direction. An opening is formed through the second insulating film. When the interlayer insulating layer is exposed through the opening, the interlayer insulating layer is also etched in the second direction, and an opening penetrating the interlayer insulating film is formed. That is, using the second insulating film having a large dimension along the second direction as an etching mask, the second insulating film is disposed inside the second insulating film having a large dimension along the second direction. And an opening (second opening) penetrating through the interlayer insulating film.
In addition, since the etching in the direction crossing the second direction is suppressed, in the second insulating film (the second insulating film in the portion covering the wall surface) having a large dimension along the second direction, The dimension in the direction crossing the second direction hardly changes, and the dimension corresponding to the film thickness of the second insulating film is maintained.

  Therefore, the first portion in the first opening and the etching surface of the second insulating film reaches the interlayer insulating film, and the second portion that continues to the first portion and reaches the first relay electrode. A second opening formed of a portion (an etched surface of the interlayer insulating layer) can be formed. In other words, the second opening that penetrates the second insulating film and the interlayer insulating film can be formed inside the first opening with the second insulating film covering the wall surface interposed therebetween.

  As described above, the step of forming the second opening does not include a photoetching step, and the second opening is inside the first opening by using the second insulating film covering the wall surface as an etching mask. Automatically (self-aligned). Therefore, in the step of forming the second opening, since the influence (for example, alignment error) of the photoetching process is excluded, the second opening having a small opening size compared to the case of using the photoetching process. Can be formed with high accuracy.

  The second opening is a contact hole for electrically connecting the pixel electrode and the first relay electrode. As described above, in the manufacturing method according to this application example, a smaller second opening (contact hole) can be formed as compared with the case where the photoetching process is used. Therefore, in the manufacturing method according to this application example, the contact portion that electrically connects the pixel electrode and the first relay electrode, that is, the region that does not contribute to display can be reduced, and the region that contributes to display can be increased. So a brighter display can be provided.

  Application Example 13 In the electro-optical device manufacturing method according to the application example, in the step of forming the second relay electrode, the first relay electrode protruding from between the second relay electrode and the conductive layer. The insulating film is also preferably etched.

  The first insulating film between the second relay electrode and the conductive layer becomes a part of a component of a contact portion that electrically connects the pixel electrode and the transistor. On the other hand, the first insulating film that protrudes between the second relay electrode and the conductive layer is provided at a location different from the contact portion, and does not affect the contact portion that electrically connects the pixel electrode and the transistor. Since it is an extra component, it is preferable to remove it by etching.

1 is a schematic plan view showing a configuration of an organic EL device according to Embodiment 1. FIG. FIG. 2 is an equivalent circuit diagram illustrating an electrical configuration of the organic EL device according to the first embodiment. The schematic plan view of a luminescent pixel. FIG. 4 is a schematic cross-sectional view of a light emitting region along line A-A ′ in FIG. 3. FIG. 4 is a schematic cross-sectional view of a region provided with a pixel contact along the line B-B ′ in FIG. 3. 5 is a process flow showing a method for manufacturing the organic EL device according to the first embodiment. The schematic sectional drawing which shows the state of the organic EL apparatus after passing through each process. The schematic sectional drawing which shows the state of the organic EL apparatus after passing through each process. FIG. 3 is a schematic cross-sectional view of a light emitting region of an organic EL device according to Embodiment 2. FIG. 5 is a schematic cross-sectional view of a pixel contact of an organic EL device according to Embodiment 2. 9 is a process flow showing a method for manufacturing an organic EL device according to Embodiment 2. The schematic sectional drawing which shows the state of the organic EL apparatus after passing through each process. The schematic sectional drawing which shows the state of the organic EL apparatus after passing through each process. FIG. 5 is a schematic cross-sectional view of a light emitting region of an organic EL device according to Embodiment 3. FIG. 5 is a schematic cross-sectional view of a pixel contact of an organic EL device according to Embodiment 3. 9 is a process flow showing a method for manufacturing an organic EL device according to Embodiment 3. The schematic sectional drawing which shows the state of the organic EL apparatus after passing through each process. The schematic sectional drawing which shows the state of the organic EL apparatus after passing through each process. Schematic of a head mounted display.

  Embodiments of the present invention will be described below with reference to the drawings. Such an embodiment shows one aspect of the present invention and does not limit the present invention, and can be arbitrarily changed within the scope of the technical idea of the present invention. In each of the following drawings, the scale of each layer or each part is made different from the actual scale so that each layer or each part can be recognized on the drawing.

(Embodiment 1)
"Outline of organic EL device"
The organic EL device 100 according to the first embodiment is an example of an electro-optical device, and has an optical resonance structure that can increase the color purity of display light.
First, an outline of the organic EL device 100 according to the present embodiment will be described with reference to FIGS. 1 to 3. FIG. 1 is a schematic plan view showing the configuration of an organic EL device, FIG. 2 is an equivalent circuit diagram showing the electrical configuration of the organic EL device, and FIG. 3 is a schematic plan view of a light emitting pixel.
In FIG. 3, components necessary for explanation are illustrated, and other components are not illustrated. In addition, a two-dot chain line in FIG.

As shown in FIG. 1, the organic EL device 100 according to this embodiment includes an element substrate 10 and a sealing substrate 70. Both substrates are bonded by a resin layer 71 (see FIG. 4) described later.
The element substrate 10 includes a plurality of light emitting pixels 20B, 20G, and 20R arranged in a matrix in the display region E, and a peripheral circuit that drives and controls the plurality of light emitting pixels 20B, 20G, and 20R (data line driving circuit 101, scanning line). The drive circuit 102), an external connection terminal 103 for electrical connection with an external circuit, and the like are arranged.

  A plurality of external connection terminals 103 are arranged along the first side of the element substrate 10. A data line drive circuit 101 is provided between the plurality of external connection terminals 103 and the display area E. A scanning line driving circuit 102 is provided between the second and third sides that are orthogonal to the first side and face each other, and the display area E.

Hereinafter, the direction along the first side is the X direction, the direction along the other two sides (second side and third side) orthogonal to the first side and facing each other is the Y direction, and from the element substrate 10. A direction toward the sealing substrate 70 will be described as a Z (+) direction.
The Z (+) direction from the element substrate 10 toward the sealing substrate 70 is an example of the “first direction” in the present invention. The Z (−) direction from the sealing substrate 70 toward the element substrate 10 is an example of the “second direction” in the present invention.

  The sealing substrate 70 is smaller than the element substrate 10 and is disposed so that the external connection terminals 103 are exposed. The sealing substrate 70 is a light-transmitting insulating substrate, and a quartz substrate, a glass substrate, or the like can be used. The sealing substrate 70 has a role of protecting the later-described organic EL element 30 (see FIG. 2) disposed in the display area E from being damaged, and is provided wider than the display area E.

The organic EL device 100 includes a light emitting pixel 20B that can emit blue (B) light, a light emitting pixel 20G that can emit green (G) light, and a light emitting pixel 20R that can emit red (R) light. ing. Further, the light emitting pixel 20B has a pixel electrode 31B, the light emitting pixel 20G has a pixel electrode 31G, and the light emitting pixel 20R has a pixel electrode 31R. In the organic EL device 100, the light emitting pixel 20B, the light emitting pixel 20G, and the light emitting pixel 20R arranged in the X direction serve as a display unit P, and a full color display is provided.
The pixel electrode 31B is an example of the “first pixel electrode” in the present invention, the pixel electrode 31G is an example of the “second pixel electrode” in the present invention, and the pixel electrode 31R is the “third pixel electrode” in the present invention. This is an example of “a pixel electrode”.
In the following description, the light emitting pixels 20B, 20G, and 20R may be collectively referred to as the light emitting pixel 20, and the pixel electrodes 31B, 31G, and 31R may be collectively referred to as the pixel electrode 31.

  In the Y direction, light emitting pixels 20 that can emit light of the same color are arranged. That is, the light emitting pixel 20B from which blue (B) light emission is obtained, the light emitting pixel 20G from which green (G) light emission is obtained, and the light emitting pixel 20R from which red (R) light emission is obtained are repeatedly arranged in the Y direction. ing.

  In the X direction, light emitting pixels 20 that can emit light of different colors are repeatedly arranged in the order of B, G, and R. The arrangement of the light emitting pixels 20 in the X direction may not be in the order of B, G, and R, and may be in the order of R, G, and B, for example.

A translucent optical distance adjustment layer 28 is provided on substantially the entire surface of the element substrate 10 excluding the region where the external connection terminals 103 are formed.
The translucent optical distance adjustment layer 28 includes a first region 28B in which the light emitting pixel 20B (pixel electrode 31B) is disposed, a second region 28G in which the light emitting pixel 20G (pixel electrode 31G) is disposed, A third region 28R in which the light emitting pixel 20R (pixel electrode 31R) is disposed.

The first region 28B extends in the Y direction and is provided in a region where the light emitting pixel 20B is disposed. The second region 28G extends in the Y direction and is provided in a region where the light emitting pixel 20G is disposed. The third region 28R extends in the Y direction and is provided in a region where the light emitting pixel 20R is disposed. The Y-direction dimensions of the first area 28B, the second area 28G, and the third area 28R are the same as the Y-direction dimensions of the display area E.
Note that the Y-direction dimensions of the first area 28B, the second area 28G, and the third area 28R may be larger than the Y-direction dimensions of the display area E.

  The first region 28B, the second region 28G, and the third region 28R are repeatedly arranged in this order in the X direction. The X-direction dimensions of the first region 28B, the second region 28G, and the third region 28R are substantially the same as the X-direction dimensions of the light-emitting pixels 20.

Although details will be described later, the thickness (film thickness) of the optical distance adjustment layer 28 in the first region 28B, the second region 28G, and the third region 28R is different. That is, the film thickness of the optical distance adjustment layer 28 in the second region 28G is larger than the film thickness of the optical distance adjustment layer 28 in the first region 28B. The film thickness of the optical distance adjustment layer 28 in the third region 28R is larger than the film thickness of the optical distance adjustment layer 28 in the second region 28G. Thus, the film thickness of the optical distance adjustment layer 28 increases in the order of the first region 28B, the second region 28G, and the third region 28R.
The optical distance adjusting layer 28 in the first region 28B is an example of the “first layer thickness portion” in the present invention, and the optical distance adjusting layer 28 in the second region 28G is the “first thickness in the present invention”. The optical distance adjusting layer 28 in the third region 28R is an example of the “third layer thickness portion” in the present invention.

  As shown in FIG. 2, the element substrate 10 is provided with scanning lines 11, data lines 12, lighting control lines 13, and power supply lines 14 as signal lines corresponding to the light emitting pixels 20. The scanning line 11 and the lighting control line 13 extend in parallel in the X direction, and are connected to the scanning line driving circuit 102 (FIG. 1). The data line 12 and the power supply line 14 extend in parallel in the Y direction. The data line 12 is connected to the data line driving circuit 101 (FIG. 1). The power supply line 14 is connected to one of the plurality of external connection terminals 103 arranged.

In an area partitioned by the scanning line 11 and the data line 12, a first transistor 21, a second transistor 22, a third transistor 23, a storage capacitor 24, and an organic EL that form a pixel circuit of the light emitting pixel 20 are provided. An element 30 is provided.
The third transistor 23 is an example of the “transistor” in the present invention.

  The organic EL element 30 includes a pixel electrode 31 as an anode, a counter electrode 33 as a cathode, and a light emitting functional layer 32 including a light emitting layer sandwiched between these electrodes. The counter electrode 33 is a common electrode provided across the plurality of light emitting pixels 20. The counter electrode 33 is supplied with a reference potential Vss, a GND potential, or the like, which is lower in potential than the power supply voltage Vdd supplied to the power supply line 14, for example.

  The first transistor 21 and the third transistor 23 are, for example, n-channel transistors. The second transistor 22 is, for example, a p-channel type transistor.

  The gate electrode of the first transistor 21 is connected to the scanning line 11, one current end is connected to the data line 12, and the other current end is connected to the gate electrode of the second transistor 22 and one electrode of the storage capacitor 24. It is connected.

  One current end of the second transistor 22 is connected to the power supply line 14 and to the other electrode of the storage capacitor 24. The other current end of the second transistor 22 is connected to one current end of the third transistor 23. In other words, the second transistor 22 and the third transistor 23 share one current end of the pair of current ends.

The gate electrode of the third transistor 23 is connected to the lighting control line 13, and the other current end is connected to the pixel electrode 31 of the organic EL element 30.
In the following description, a portion where the third transistor 23 and the pixel electrode 31 are connected is referred to as a pixel contact.
One of the pair of current ends in each of the first transistor 21, the second transistor 22, and the third transistor 23 is a source, and the other is a drain.

  In such a pixel circuit, when the voltage of the scanning signal Yi supplied from the scanning line driving circuit 102 to the scanning line 11 becomes Hi level, the n-channel first transistor 21 is turned on (ON). The data line 12 and the storage capacitor 24 are electrically connected via the first transistor 21 in the on state (ON). When a data signal is supplied from the data line driving circuit 101 to the data line 12, a voltage corresponding to the potential difference between the voltage Vdata of the data signal and the power supply voltage Vdd applied to the power supply line 14 is held in the storage capacitor 24. The

  When the voltage of the scanning signal Yi supplied from the scanning line driving circuit 102 to the scanning line 11 becomes low level, the n-channel first transistor 21 is turned off, and the gate-source voltage of the second transistor 22 is turned off. Vgs is held at a voltage when the voltage Vdata is applied. Further, after the scanning signal Yi becomes Low level, the voltage of the lighting control signal Vgi supplied to the lighting control line 13 becomes Hi level, and the third transistor 23 is turned on (ON). Then, the current corresponding to the gate-source voltage Vgs of the second transistor 22, that is, the voltage held in the storage capacitor 24, passes through the second transistor 22 and the third transistor 23 from the power supply line 14, and the organic EL element. 30.

  The organic EL element 30 emits light according to the magnitude of the current flowing through the organic EL element 30. The current flowing through the organic EL element 30 varies depending on the voltage held in the storage capacitor 24 (potential difference between the voltage Vdata of the data line 12 and the power supply voltage Vdd) and the length of the period during which the third transistor 23 is turned on. The light emission luminance of the organic EL element 30 is defined. That is, the luminance gradation according to the image information can be given to the light emitting pixel 20 by the value of the voltage Vdata in the data signal.

  In the present embodiment, the pixel circuit of the light emitting pixel 20 is not limited to having the three transistors 21, 22, and 23. For example, a configuration having a switching transistor and a driving transistor (a configuration having two transistors). ). In addition, a transistor included in the pixel circuit may be an n-channel transistor, a p-channel transistor, or may include both an n-channel transistor and a p-channel transistor. The transistor constituting the pixel circuit of the light emitting pixel 20 may be a MOS transistor having an active layer on a semiconductor substrate, a thin film transistor, or a field effect transistor.

Further, the arrangement of the lighting control lines 13 and the power supply lines 14 which are signal lines other than the scanning lines 11 and the data lines 12 depends on the arrangement of the transistors and the storage capacitors 24, and is not limited thereto.
In the present embodiment, a MOS transistor having an active layer on a semiconductor substrate is employed as the transistor constituting the pixel circuit of the light emitting pixel 20.

"Luminescent Pixel"
Next, an outline of the light emitting pixel 20 will be described with reference to FIG.
As shown in FIG. 3, the light emitting pixel 20 includes a power line 14, an optical distance adjustment layer 28, a pixel electrode 31, and a dielectric film 29 arranged (laminated) in the Z (+) direction. ing.
The power supply line 14 is provided on substantially the entire surface of the display region E, and has a first opening CT1 for each light emitting pixel 20. A second opening CT2 is provided inside the first opening CT1. Although details will be described later, the power supply line 14 is made of a light-reflective conductive material and functions as a light-reflecting film.
The power supply line 14 is an example of the “conductive layer” in the present invention.

  The optical distance adjustment layer 28 is provided so as to cover the power supply line 14. The pixel electrode 31 is disposed to face the power supply line 14 with the optical distance adjustment layer 28 interposed therebetween. The pixel electrode 31 has a rectangular shape elongated in the Y direction, and is provided so as to cover the first opening CT1 in plan view. The dielectric film 29 is provided so as to cover the peripheral edge of the pixel electrode 31. The dielectric film 29 has openings 29B, 29G, and 29R that expose a part of the pixel electrode 31. Similarly to the pixel electrode 31, the openings 29B, 29G, and 29R have a rectangular shape that is elongated in the Y direction.

  The part of the pixel electrode 31 where the dielectric film 29 is not provided, that is, the pixel electrode 31 exposed through the openings 29B, 29G, and 29R is in contact with the light emitting functional layer 32 and supplies a current to the light emitting functional layer 32. 32 is caused to emit light. For this reason, the openings 29B, 29G, and 29R provided in the dielectric film 29 become light emitting regions of the light emitting pixels 20B, 20G, and 20R. As described above, the dielectric film 29 defines the light emitting region of the light emitting pixel 20 and has a role of electrically insulating the adjacent pixel electrodes 31 from each other.

  Although the details will be described later, the first opening CT1 and the second opening CT2 are components of a pixel contact that electrically connects the third transistor 23 and the pixel electrode 31. Pixel contacts (first opening CT 1, second opening CT 2, etc.) are provided in the non-light emitting region of the light emitting pixel 20. In order to provide a brighter display, the area of the light emitting region (openings 29B, 29G, and 29R) is increased, and the area of the non-light emitting region, that is, the pixel contact (first opening CT1, second opening CT2). ) Area needs to be reduced. The present embodiment has a configuration suitable for reducing the area of the pixel contact (first opening CT1, second opening CT2, etc.), and details thereof will be described below.

"Cross-sectional structure of organic EL device"
First, the cross-sectional structure of the organic EL device 100 will be described with reference to FIGS. 4 and 5.
FIG. 4 is a schematic cross-sectional view along the line AA ′ in FIG. 3, that is, a schematic cross-sectional view of the light emitting region. FIG. 5 is a schematic cross-sectional view taken along line BB ′ of FIG. 3, that is, a schematic cross-sectional view of a region where a pixel contact is provided.
FIG. 4 shows the first transistor 21 and the second transistor 22 in the pixel circuit, wirings related to the first transistor 21 and the second transistor 22, and the like, and the illustration of the third transistor 23 is omitted. . FIG. 5 shows the third transistor 23, wirings related to the third transistor 23, and the like, and the illustration of the first transistor 21 and the second transistor 22 is omitted. Further, FIG. 5 shows a cross-sectional view along BB ′ and an enlarged view of the pixel contact.

First, the cross-sectional structure of the light emitting region will be described with reference to FIG.
As illustrated in FIG. 4, the organic EL device 100 includes an element substrate 10, a sealing substrate 70, a resin layer 71 sandwiched between the element substrate 10 and the sealing substrate 70, and the like.

  The resin layer 71 has a role of bonding the element substrate 10 and the sealing substrate 70, and for example, an epoxy resin or an acrylic resin can be used.

  The element substrate 10 is provided with a pixel circuit (first transistor 21, second transistor 22, third transistor 23, storage capacitor 24, organic EL element 30), sealing layer 40, color filter 50, and the like.

  The light emitted from the light emitting pixels 20 passes through the color filter 50 and is emitted from the sealing substrate 70 side. That is, the organic EL device 100 has a top emission structure. Since the organic EL device 100 has a top emission structure, an opaque ceramic substrate or semiconductor substrate can be used as the base material 10s of the element substrate 10 in addition to a transparent quartz substrate or glass substrate. In the present embodiment, a silicon substrate (an opaque semiconductor substrate) is used as the base material 10s.

In the base material 10s, an ion implantation which is an active layer formed by injecting into the well 10w a well portion 10w formed by implanting ions into the semiconductor substrate, and ions of a type different from the well 10w. 10d. The well portion 10 w functions as a channel for the transistors 21, 22, and 23 in the light emitting pixel 20. The ion implantation part 10 d functions as a part of the source / drain of the transistors 21, 22, and 23 and the wiring in the light emitting pixel 20.
The base material 10s provided with the well portion 10w functioning as a channel is an example of the “base material provided with a transistor” in the present invention. The surface 10f of the base material 10s provided with the well portion 10w functioning as a channel is an example of the “first surface” in the present invention, and is hereinafter referred to as the surface 10f of the base material 10s.

  An insulating film 10a is provided so as to cover the surface 10f of the base material 10s. The insulating film 10a functions as a gate insulating film of the transistors 21, 22, and 23. On the insulating film 10a, for example, a gate electrode 22g made of a conductive film such as polysilicon is provided. The gate electrode 22g is disposed so as to face the well portion 10w that functions as a channel of the second transistor 22. The other first transistor 21 and third transistor 23 are similarly provided with gate electrodes.

  A first interlayer insulating film 15 is provided so as to cover the gate electrode 22g. In the first interlayer insulating film 15, for example, contact holes reaching the drain of the first transistor 21 and the gate electrode 22 g of the second transistor 22 are provided. A conductive film that covers at least the inside of the contact hole and covers the surface of the first interlayer insulating film 15 is formed. By patterning the conductive film, for example, the drain electrode 21d of the first transistor 21 and the gate electrode of the second transistor 22 are formed. Wiring connected to 22g is provided.

  Next, a second interlayer insulating film 16 is provided so as to cover the first interlayer insulating film 15 and the wiring on the first interlayer insulating film 15. The second interlayer insulating film 16 is provided with a contact hole reaching the wiring provided on the first interlayer insulating film 15. A conductive film (for example, a three-layer film of titanium nitride, aluminum, and titanium nitride) covering at least the inside of the contact hole and covering the surface of the second interlayer insulating film 16 is formed, and by patterning this, for example, A contact portion for electrically connecting one electrode 24 a of the storage capacitor 24 and the gate electrode 22 g of the second transistor 22 is provided. Further, the data line 12 and the first relay electrode 7 (see FIG. 5) are provided in the same layer as the one electrode 24a of the storage capacitor 24. The data line 12 is connected to the source of the first transistor 21 by a relay electrode (wiring) not shown in FIG.

A capacitor insulating film 24 c is provided so as to cover one electrode 24 a of the storage capacitor 24. The other electrode 24b of the storage capacitor 24 is provided to face one electrode 24a of the storage capacitor 24 with the capacitor insulating film 24c interposed therebetween. A storage capacitor 24 is formed by the pair of electrodes 24a and 24b and the capacitor insulating film 24c.
The capacitive insulating film 24c is made of, for example, silicon nitride and has a film thickness of approximately 30 nm to 60 nm. The other electrode 24b of the storage capacitor 24 is made of, for example, titanium nitride.

  A third interlayer insulating film 17 is provided so as to cover the storage capacitor 24. The third interlayer insulating film 17 is made of silicon oxide and has a thickness of approximately 80 nm. The capacitor insulating film 24c and the third interlayer insulating film 17 constitute an interlayer insulating layer 25. The film thickness of the interlayer insulating layer 25 is approximately 850 nm. In other words, the data line 12 and the first relay electrode 7 (see FIG. 5) provided on the second interlayer insulating film 16 are covered with the interlayer insulating layer 25. In the third interlayer insulating film 17, for example, a contact hole reaching the wiring formed on the other electrode 24 b of the storage capacitor 24 and the second interlayer insulating film 16 is provided. A conductive film that covers at least the inside of the contact hole and covers the surface of the third interlayer insulating film 17 (interlayer insulating layer 25) is formed, and the power line 14 is provided by patterning the conductive film.

The power line 14 is made of a light-reflective conductive material such as aluminum or aluminum alloy. The film thickness of the power supply line 14 is approximately 100 nm.
As described above, the power supply line 14 is provided over substantially the entire surface of the display region E, and is disposed so as to face the pixel electrode 31. The power supply line 14 also has a role as a light reflection layer that reflects light emitted from the light emitting regions (openings 29B, 29G, and 29R). The first insulating film 1 is made of silicon nitride, covers the power supply line 14, and is provided over substantially the entire display area E.

An optical distance adjustment layer 28 is provided between the power supply line 14 and the pixel electrode 31. The optical distance adjustment layer 28 is laminated in order along the Z (+) direction from the power supply line 14 side, the first insulating film 1, the first silicon oxide film 3, and the second silicon oxide film. 4 and. The first insulating film 1, the first silicon oxide film 3, and the second silicon oxide film 4 are insulating materials having optical transparency. The first insulating film 1 is made of silicon nitride. The film thickness of the first insulating film 1 is approximately 50 nm. The film thicknesses of the first silicon oxide film 3 and the second silicon oxide film 4 are approximately 60 nm to 70 nm.
The first silicon oxide film 3 is an example of the “third insulating film” in the present invention, and the second silicon oxide film 4 is an example of the “fourth insulating film” in the present invention.

The optical distance adjustment layer 28 of the light emitting pixel 20B (first region 28B) is composed of the first insulating film 1 and has a film thickness Bd1. The optical distance adjustment layer 28 of the light emitting pixel 20G (second region 28G) is composed of the first insulating film 1 and the second silicon oxide film 4, and has a film thickness Gd1. The optical distance adjustment layer 28 of the light emitting pixel 20R (third region 28R) is composed of the first insulating film 1, the first silicon oxide film 3, and the second silicon oxide film 4, and has a film thickness Rd1. Have. The film thickness Bd1 of the optical distance adjusting layer 28 of the light emitting pixel 20B (first region 28B) is approximately 50 nm, and the film thickness Gd1 of the optical distance adjusting layer 28 of the light emitting pixel 20G (second region 28G) is approximately. The thickness Rd1 of the optical distance adjustment layer 28 of the light emitting pixel 20R (third region 28R) is approximately 170 nm.
The film thickness Bd1 is an example of the “first layer thickness” in the present invention, the film thickness Gd1 is an example of the “second layer thickness” in the present invention, and the film thickness Rd1 is the “third layer thickness” in the present invention. Is an example.

  The pixel electrode 31 is provided in an island shape on the optical distance adjustment layer 28. Specifically, the pixel electrode 31B is provided in an island shape on the optical distance adjustment layer 28 having a film thickness Bd1, and the pixel electrode 31G is provided in an island shape on the optical distance adjustment layer 28 having a film thickness Gd1. The electrode 31R is provided in an island shape on the optical distance adjustment layer 28 having a film thickness Rd1. The pixel electrode 31 is light transmissive and is formed of a light transmissive material such as ITO (Indium Tin Oxide), for example, and serves as an electrode for supplying holes to the light emitting functional layer 32. The film thickness of the pixel electrode 31 is approximately 100 nm.

  A dielectric film 29 is provided so as to cover the peripheral edge of the pixel electrode 31. The dielectric film 29 is made of, for example, silicon oxide and insulates each of the pixel electrodes 31B, 31G, and 31R. The film thickness of the dielectric film 29 is approximately 60 nm. The dielectric film 29 is provided with openings 29B, 29G, and 29R. As described above, the region where the openings 29B, 29G, and 29R are provided is the light emitting region of the light emitting pixel 20. The dielectric film 29 may be formed using an organic material such as an acrylic photosensitive resin.

  The light emitting functional layer 32, the counter electrode 33, and the sealing layer 40 are sequentially stacked along the Z (+) direction so as to cover the pixel electrode 31 and the dielectric film 29.

  The light emitting functional layer 32 includes a hole injection layer, a hole transport layer, an organic light emitting layer, an electron transport layer, and the like, which are sequentially stacked from the pixel electrode 31 side along the Z (+) direction. In the organic light emitting layer, excitons (excitons; a state where electrons and holes are bound to each other by Coulomb force) are formed by the holes supplied from the pixel electrode 31 and the electrons supplied from the counter electrode 33. When excitons (excitons) disappear (electrons and holes recombine), part of the energy is emitted as fluorescence or phosphorescence. That is, the light emitting functional layer 32 emits light (emits light). The film thickness of the light emitting functional layer 32 is approximately 110 nm.

  The organic light emitting layer emits light having red, green, and blue light components. The organic light emitting layer may be composed of a single layer, or a plurality of layers (for example, a blue light emitting layer that emits mainly blue light when current flows, and yellow light that emits light including red and green when current flows) Layer).

  The counter electrode 33 is a common electrode for supplying electrons to the light emitting functional layer 32. The counter electrode 33 is provided so as to cover the light emitting functional layer 32 and is made of, for example, an alloy of Mg and Ag, and has light transmittance and light reflectivity. The thickness of the counter electrode 33 is approximately 10 nm to 30 nm. By reducing the thickness of the constituent material of the counter electrode 33 (such as an alloy of Mg and Ag), a light transmissive function can be imparted in addition to a light reflective function.

  A sealing layer 40 is disposed on the counter electrode 33. The sealing layer 40 is a passivation film that suppresses deterioration of the light emitting functional layer 32 and the counter electrode 33 due to moisture, oxygen, and the like, and suppresses intrusion of water and oxygen into the light emitting functional layer 32 and the counter electrode 33. The sealing layer 40 includes a first sealing layer 41, a buffer layer 42, and a second sealing layer 43 that are sequentially stacked from the counter electrode 33 side, and covers the organic EL element 30 (display region E). It is provided on substantially the entire surface of the element substrate 10. The sealing layer 40 is provided with an opening (not shown) for exposing the external connection terminal 103 (see FIG. 1).

  The first sealing layer 41 is made of silicon oxynitride formed using, for example, a known plasma CVD (Chemical Vapor Deposition) method, and has a high barrier property against moisture and oxygen. The film thickness of the first sealing layer 41 is approximately 200 nm to 400 nm. In addition to the silicon oxynitride described above, a metal oxide such as silicon oxide, silicon nitride, and titanium oxide can be used as the material constituting the first sealing layer 41.

  The buffer layer 42 is made of, for example, an epoxy resin or a coating-type inorganic material (silicon oxide or the like) excellent in thermal stability. The film thickness of the buffer layer 42 is larger than the film thickness of the first sealing layer 41 and is approximately 1000 nm to 5000 nm. The buffer layer 42 covers defects (pinholes, cracks), foreign matters, and the like of the first sealing layer 41 to form a flat surface.

  The second sealing layer 43 is made of silicon oxynitride formed using, for example, a known technique such as plasma CVD. The film thickness of the second sealing layer 43 is approximately 300 nm to 700 nm. The second sealing layer 43 is made of the same material as the first sealing layer 41 and has a high barrier property against moisture and oxygen.

  On the sealing layer 40, colored layers 50B, 50G, and 50R corresponding to the light emitting pixels 20B, 20G, and 20R are provided. In other words, the color filter 50 including the colored layers 50B, 50G, and 50R is provided on the sealing layer 40.

  Next, the cross-sectional structure of the pixel contact will be described with reference to FIG.

  As shown in FIG. 5, the base 10 s is formed by injecting into the well 10 w a well portion 10 w formed by implanting ions into the semiconductor substrate, and ions different from the well 10 w. And an ion implantation portion 10d. The ion implanter 10 d functions as the source of the third transistor 23.

  An insulating film 10a and a first interlayer insulating film 15 are provided so as to cover the surface 10f of the base material 10s. The first interlayer insulating film 15 and the insulating film 10a are provided with contact holes reaching the ion implantation part 10d of the third transistor 23. A conductive film that covers at least the inside of the contact hole and covers the surface of the first interlayer insulating film 15 is formed, and is patterned to be connected to the source electrode 23s of the third transistor 23 and the source electrode 23s. Wiring is provided.

  The wiring connected to the first interlayer insulating film 15 and the source electrode 23 s is covered with the second interlayer insulating film 16. The second interlayer insulating film 16 is provided with a contact hole that reaches the wiring connected to the source electrode 23s. A conductive film (for example, a three-layer film of titanium nitride, aluminum, and titanium nitride) that covers at least the inside of the contact hole and covers the surface of the second interlayer insulating film 16 is formed and patterned to form a first layer A first relay electrode 7 is provided on the two-layer insulating film 16. As described above, the first relay electrode 7, the data line 12, and one electrode 24 a (FIG. 4) of the storage capacitor 24 are formed in the same process.

  The first relay electrode 7 is covered with an interlayer insulating layer 25 composed of a capacitive insulating film 24 c and a third interlayer insulating film 17. On the interlayer insulating layer 25, the power supply line 14 and the first insulating film 1 are laminated.

  The power line 14 and the first insulating film 1 are provided with a first opening CT1 that penetrates the power line 14 and the first insulating film 1. The first opening CT1 is configured by a wall surface CT1a along the Z (+) direction. A second insulating film 2 is provided so as to cover the wall surface CT1a. The second insulating film 2 is made of silicon nitride. The second opening CT2 includes a first wall surface CT2a along the Z (+) direction provided on the second insulating film 2 side and a Z (+) direction provided on the interlayer insulating layer 25 side. And the second wall surface CT2b along. In other words, the second opening CT2 includes the first portion (first wall surface CT2a) formed inside the first opening CT1 with the second insulating film 2 interposed therebetween, and the first portion. A second portion (second wall surface CT2b) formed continuously from (first wall surface CT2a) and reaching the first relay electrode 7 is formed. That is, the second opening CT2 is a contact hole that penetrates the second insulating film 2 and the interlayer insulating layer 25 and exposes the first relay electrode 7.

  As described above, the film thickness (Z-direction dimension) of the first insulating film 1 is approximately 50 nm, and the film thickness (Z-direction dimension) of the power supply line 14 is approximately 100 nm. The film thickness (dimension in the Z direction) and the depth of the first opening CT1 (dimension in the Z direction) are approximately 150 nm. The X-direction dimension W1 of the first opening CT1 (hereinafter referred to as the opening dimension W1) is approximately 500 nm.

  Since the thickness of the second insulating film 2 is approximately 150 nm and the thickness of the interlayer insulating layer 25 is approximately 850 nm, the depth (dimension in the Z direction) of the second opening CT2 is approximately 1000 nm. The X-direction dimension W2 (hereinafter referred to as the opening dimension W2) of the second opening CT2 is approximately 300 nm.

  The second relay electrode 8 that covers the inside of the second opening CT2, the surface of the first relay electrode 7 exposed at the second opening CT2, and a part of the surface of the first insulating film 1 Is provided. As a constituent material of the second relay electrode 8, a barrier metal such as tungsten nitride, an alloy of tungsten and titanium, tantalum nitride, titanium nitride, or the like can be used. Since titanium nitride is superior in workability compared to other barrier metals, titanium nitride is used for the second relay electrode 8 in this embodiment. The film thickness of the second relay electrode 8 is approximately 50 nm. Thus, the second relay electrode 8 is provided so as to cover at least the inside of the second opening CT2. The second relay electrode 8 is formed in a concave shape reflecting the shape of the second opening CT2.

  A conductive material 9 is filled on the inner surface side of the second relay electrode 8 formed in a concave shape. As a constituent material of the conductive material 9, for example, a refractory metal such as tungsten, molybdenum, tantalum, titanium, or nickel can be used. Tungsten is superior to other refractory metals in terms of workability (easiness of film formation and etching) and heat resistance. Therefore, in this embodiment, tungsten is used for the conductive material 9.

  The second relay electrode 8 is provided wider than the first opening CT1 so as to cover the first opening CT1 in plan view. With this configuration, light emitted from the light emitting functional layer 32 is shielded by the second relay electrode 8 so as not to pass through the first opening CT1 and enter the transistors 21, 22, and 23. That is, the second relay electrode 8 has a role of blocking light incident on the light emitting functional layer 32 and suppressing malfunction of the transistors 21, 22, and 23.

  In the light emitting pixel 20 </ b> B, the pixel electrode 31 </ b> B is provided so as to cover the conductive material 9 and the second relay electrode 8. That is, the pixel electrode 31 </ b> B is in contact with the conductive material 9 and the second relay electrode 8, and is electrically connected to the first relay electrode 7 via the conductive material 9 and the second relay electrode 8.

  In the light emitting pixel 20 </ b> G, the second silicon oxide film 4 covering the conductive material 9 and the second relay electrode 8 is provided. The second silicon oxide film 4 is provided with a contact hole CTG1 through which the conductive material 9 and the second relay electrode 8 are exposed. The pixel electrode 31G is provided on the first silicon oxide film 3 so as to cover the conductive material 9 and the second relay electrode 8 (first opening CT1), and the conductive material 9 via the contact hole CTG1. And electrically connected to the second relay electrode 8. That is, the pixel electrode 31G is electrically connected to the first relay electrode 7 via the conductive material 9 and the second relay electrode 8.

  In the light emitting pixel 20R, a first silicon oxide film 3 and a second silicon oxide film 4 that cover the conductive material 9 and the second relay electrode 8 are sequentially provided. The first silicon oxide film 3 and the second silicon oxide film 4 are provided with a contact hole CTR1 through which the conductive material 9 and the second relay electrode 8 are exposed. The pixel electrode 31R is provided on the first silicon oxide film 3 so as to cover the conductive material 9 and the second relay electrode 8 (first opening CT1), and the conductive material 9 is interposed via the contact hole CTR1. And electrically connected to the second relay electrode 8. That is, the pixel electrode 31 </ b> R is electrically connected to the first relay electrode 7 via the conductive material 9 and the second relay electrode 8.

  Thus, the pixel electrode 31 is electrically connected to the first relay electrode 7 via the conductive material 9 and the second relay electrode 8. Note that in the light emitting pixel 20G and the light emitting pixel 20R, the contact holes CTG1 and CTR1 are made small, and only the conductive material 9 is exposed through the contact holes CTG1 and CTR1, and the pixel electrodes 31G and 31R and the conductive material 9 are electrically connected. It may be a configuration. In the present embodiment, the pixel electrode 31 has a configuration in contact with both the conductive material 9 and the second relay electrode 8. Compared with the configuration in which the pixel electrode 31 is in contact with only the conductive material 9, the pixel electrode 31 and the second relay electrode 8 are in contact with each other. The resistance to one relay electrode 7 can be reduced.

  In the pixel contact, the source electrode 23s of the third transistor 23 is electrically connected to the source electrode 23s, the first relay electrode 7 electrically connected to the wire, and the second contact. The pixel electrode 31 is electrically connected via the relay electrode 8 and the conductive material 9.

"Optical resonance structure"
In the light emitting region (openings 29B, 29G, 29R), along the Z (+) direction, the power supply line 14 as the light reflecting layer, the optical distance adjusting layer 28, the pixel electrode 31, the light emitting functional layer 32, A counter electrode 33 having light reflectivity and light transmissivity is sequentially laminated (see FIG. 4). With this configuration, the light emitted from the light emitting functional layer 32 is reciprocated between the power supply line 14 and the counter electrode 33 to resonate (amplify) light having a specific wavelength. Light of a specific wavelength is emitted from the sealing substrate 70 as display light in the Z (+) direction. Thus, the organic EL device 100 has an optical resonance structure that selectively amplifies light of a specific wavelength.
The outline of the optical resonant structure will be described below.

The optical distance adjustment layer 28 has a role of adjusting the optical path length (optical distance) between the power supply line 14 and the counter electrode 33, and the resonance wavelength varies depending on the film thickness of the optical distance adjustment layer 28. It is going to change. Specifically, the optical distance from the power supply line 14 to the counter electrode 33 is D, the phase shift in reflection at the reflection layer is φL, the phase shift in reflection at the counter electrode 33 is φU, and the peak wavelength of the standing wave is λ. When the integer is m, the optical distance D satisfies the following formula (1).
D = {(2πm + φL + φU) / 4π} λ (1)

  The optical distance D in the optical resonance structure of the light emitting pixels 20B, 20G, and 20R increases in the order of the light emitting pixel 20B, the light emitting pixel 20G, and the light emitting pixel 20R, and the optical disposed between the power supply line 14 and the pixel electrode 31. It is adjusted by making the film thickness of the target distance adjusting layer 28 different.

  As described above, in the light emitting pixel 20B, the optical distance adjustment layer 28 disposed between the power supply line 14 and the pixel electrode 31B has the film thickness Bd1. In the light emitting pixel 20G, the optical distance adjustment layer 28 disposed between the power supply line 14 and the pixel electrode 31G has a film thickness Gd1. In the light emitting pixel 20R, the optical distance adjustment layer 28 disposed between the power supply line 14 and the pixel electrode 31R has a film thickness Rd1. For this reason, the film thickness of the optical distance adjustment layer 28 increases in the order of the light emitting pixel 20B (film thickness Bd1) <the light emitting pixel 20G (film thickness Gd1) <the light emitting pixel 20R (film thickness Rd1). The optical distance D also increases in the order of the light emitting pixel 20B <the light emitting pixel 20G <the light emitting pixel 20R.

  In the light emitting pixel 20R, the optical distance D is set so that the resonance wavelength (the peak wavelength at which the luminance is maximum) is 610 nm. Similarly, in the light emitting pixel 20G, the optical distance D is set so that the resonance wavelength (peak wavelength at which the luminance is maximum) is 540 nm. In the light emitting pixel 20B, the optical distance D is set so that the resonance wavelength (the peak wavelength at which the luminance is maximum) is 470 nm.

  In order to realize the peak wavelength, the film thickness of the pixel electrodes 31B, 31G, and 31R made of a transparent conductive film such as ITO is approximately 100 nm, the film thickness of the light emitting functional layer 32 is approximately 110 nm, and m in the above formula (1). When the film thickness of the optical distance adjustment layer 28 between the reflective layer and the counter electrode 33 is calculated as = 1, the thickness is 170 nm for the light emitting pixel 20R, 115 nm for the light emitting pixel 20G, and 50 nm for the light emitting pixel 20B. That is, the film thickness Rd1 of the optical distance adjustment layer 28 in the light emitting pixel 20R (third region 28R) is approximately 170 nm, and the film thickness Gd1 of the optical distance adjustment layer 28 in the light emission pixel 20G (second region 28G) is approximately. The film thickness Bd1 of the optical distance adjusting layer 28 in the light-emitting pixel 20B (first region 28B) is 115 nm and is approximately 50 nm. The film thicknesses of the first insulating film 1, the first silicon oxide film 3, and the second silicon oxide film 4 are adjusted so that the optical distance adjusting layer 28 is formed.

As a result, red (R) light having a peak wavelength of 610 nm is emitted from the light emitting pixel 20R, green (G) light having a peak wavelength of 540 nm is emitted from the light emitting pixel 20G, and peak is 470 nm from the light emitting pixel 20B. Blue (B) light having a wavelength is emitted.
As described above, in the organic EL device 100 according to this embodiment, the color purity of the light emitted from the light emitting pixels 20 can be increased by the above-described optical resonance structure, and a vivid display can be provided.

"Method for manufacturing organic EL device"
Next, a method for manufacturing the organic EL device 100 will be described with reference to FIGS. FIG. 6 is a process flow showing a method for manufacturing an organic EL device. 7 and 8 are schematic cross-sectional views corresponding to FIG. 5 and showing the state of the organic EL device after the respective steps shown in FIG. 7 and 8, illustration of pixel circuits and wirings provided below the power supply line 14 in the element substrate 10 is omitted.

  As shown in FIG. 6, the process of manufacturing the organic EL device 100 includes a power line 14 as a light reflection layer and a first insulating film 1 that covers the power line 14 (step S <b> 1), A step of forming the opening CT1 (step S2), a step of depositing the second insulating film 2 (step S3), a step of forming the second opening CT2 (step S4), and forming a titanium nitride film. A step of performing (Step S5), a step of filling a conductive material (Step S6), a step of etching the titanium nitride film (Step S7), a step of forming the first silicon oxide film 3 (Step S8), It includes a step of forming the second silicon oxide film 4 (step S9) and a step of forming the pixel electrode 31 (step S10).

  In step S1, as shown in FIG. 7A, the power supply line 14 is formed on the interlayer insulating layer 25 by forming an aluminum film having a thickness of about 100 nm by using, for example, a sputtering method. The first insulating film 1 is formed by forming a titanium nitride film with a thickness of approximately 200 nm using a method. That is, the thickness of the power supply line 14 in the Z (−) direction is 100 nm, and the thickness of the first insulating film 1 in the Z (−) direction is 200 nm.

  In step S 2, as shown in FIG. 7B, the first insulating film 1 and the power supply line 14 are made Z by a dry etching method using a capacitively coupled dry etching apparatus such as an RIE (Reactive Ionic Etching) apparatus. An anisotropic etching in the (−) direction is performed to form the first opening CT1. Specifically, after the first insulating film 1 is etched in the Z (−) direction by a dry etching method using a fluorine-based gas, the power line 14 is moved in the Z (−) direction by a dry etching method using a chlorine-based gas. Etch. As a result, the first insulating film 1 and the power supply line 14 are formed with the first opening CT1 constituted by the wall surface CT1a along the Z (−) direction. The opening dimension W1 of the first opening CT1 is approximately 500 nm. The depth of the first opening (the length in the Z (−) direction of the wall surface CT1a) is a dimension obtained by adding the film thickness (100 nm) of the power supply line 14 and the film thickness (200 nm) of the first insulating film 1. (Approximately 300 nm).

  In other words, in step S2, anisotropic etching in the Z (−) direction is performed on the power supply line 14 and the first insulating film 1, and the etching surface (wall surface CT1a) of the power supply line 14 and the first insulating film 1 is applied. ) And the first opening CT1 in which the wall surface CT1a along the Z (−) direction reaches the interlayer insulating layer 25 is formed.

  In step S3, as shown in FIG. 7C, the second insulating film 2 is formed by depositing silicon nitride having a thickness of approximately 100 nm by using, for example, a plasma CVD method. Silicon nitride using a plasma CVD method has excellent step coverage, and the first opening CT1 is covered with silicon nitride (second insulating film 2) having substantially the same thickness. That is, the dimension (film thickness) in the Z (−) direction of the second insulating film 2 covering the surface of the interlayer insulating layer 25 and the dimension (film thickness) in the X direction of the second insulating film 2 covering the wall surface CT1a. The dimension (film thickness) in the Z (−) direction of the second insulating film 2 covering the surface of the first insulating film 1 is substantially the same, and is approximately 100 nm.

The second insulating film 2 includes a first portion 2-1 that covers the surface of the interlayer insulating layer 25, a second portion 2-2 that covers the wall surface CT1a, and a third portion that covers the surface of the first insulating film 1. And part 2-3. The film thickness in the Z (−) direction of the second insulating film 2 in the first part 2-1 and the third part 2-3 is approximately 100 nm. Furthermore, the dimension in the Z (−) direction of the second insulating film 2 in the second portion 2-2 is the same as the film thickness (100 nm) in the Z (−) direction of the power line 14 and the first insulating film 1. The dimension (approximately 400 nm) is obtained by adding the film thickness (200 nm) in the Z (−) direction and the film thickness (100 nm) of the second insulating film 2 in the third portion 2-3. The film thickness in the X direction of the second insulating film 2 in the second portion 2-2 is approximately 100 nm.
As described above, the second insulating film 2 includes a portion (first portion 2-1 and third portion 2-3) whose thickness in the Z (−) direction is 100 nm, and a portion in the Z (−) direction. And a portion having a thickness of 400 nm (second portion 2-2).

  In step S4, as shown in FIG. 7D, the second insulating film 2 and the interlayer insulating layer 25 are formed by a dry etching method using a capacitively coupled dry etching apparatus such as an RIE apparatus and a fluorine-based gas. An anisotropic etching in the Z (−) direction is performed to form the second opening CT2. In step S4, anisotropic etching in the Z (−) direction is performed without forming a new etching mask such as a photoresist.

  The second insulating film 2 in the first portion 2-1 and the third portion 2-3 is removed by anisotropic etching in the Z (−) direction. At this time, the film thickness in the Z (−) direction of the second insulating film 2 of the second part 2-2 is the second insulating film 2 of the first part 2-1 and the third part 2-3. Since the thickness of the second insulating film 2 in the second portion 2-2 is partially etched, the second insulating film in the second portion 2-2 is etched. Many of the two remain.

  When the second insulating film 2 of the first portion 2-1 and the third portion 2-3 is removed by anisotropic etching in the Z (−) direction, the first insulating film 1 and the interlayer insulating layer 25 are removed. Since the third interlayer insulating film 17 is exposed, the third interlayer insulating film 17 of the interlayer insulating layer 25 is subsequently subjected to anisotropic etching in the Z (−) direction. The first insulating film 1 and the second insulating film 2 are made of silicon nitride, and the third interlayer insulating film 17 of the interlayer insulating layer 25 is made of silicon oxide. In dry etching (anisotropic etching) using fluorine gas, for example, if the etching rate of silicon nitride is 1, the silicon oxide etching rate is 10 or more, and high etching selectivity is realized. Therefore, in the anisotropic etching of the third interlayer insulating film 17 in the Z (−) direction, the etching of the first insulating film 1 and the second insulating film 2 in the Z (−) direction is suppressed.

  When the third interlayer insulating film 17 of the interlayer insulating layer 25 is removed by anisotropic etching in the Z (−) direction, the capacitor insulating film 24c of the interlayer insulating layer 25 is exposed, so that the capacitor insulating film of the interlayer insulating layer 25 continues. 24c is anisotropically etched in the Z (-) direction. Since the capacitor insulating film 24c is made of silicon nitride, the anisotropic insulating etching of the capacitor insulating film 24c in the Z (−) direction also causes the first insulating film 1 and the second insulating film 2 to be the capacitor insulating film 24c. Etching in the Z (−) direction is approximately the same as Since the thickness of the capacitive insulating film 24c is as thin as approximately 30 nm to 60 nm, in the anisotropic etching in the Z (−) direction of the capacitive insulating film 24c, the first insulating film 1 and the second insulating film 2 (second A portion of the portion 2-2) is etched, and most of the first insulating film 1 and the second insulating film 2 (second portion 2-2) remain.

  On the other hand, in the anisotropic etching in the Z (−) direction, etching in the direction intersecting the Z (−) direction (X direction, Y direction) is suppressed. Therefore, in the anisotropic etching in the Z (−) direction, the etching in the X direction and the Y direction of the second insulating film 2 of the second portion 2-2 is suppressed, and the second portion 2-2 is secondly etched. The thickness of the insulating film 2 in the X direction hardly changes, and the state of approximately 100 nm is maintained.

  As described above, in step S4, the second insulating film 2 of the first portion 2-1 and the interlayer insulating layer 25 are etched using the second insulating film 2 of the second portion 2-2 as an etching mask. In this step, the second opening CT2 is formed. The second opening CT2 includes the first wall surface CT2a that is an etching surface along the Z (−) direction of the second insulating film 2 of the second portion 2-2, and the Z (−) of the interlayer insulating layer 25. ) And a second wall surface CT2b which is an etching surface along the direction.

  In other words, in step S4, anisotropic etching in the Z (−) direction is performed on the second insulating film 2 and the interlayer insulating layer 25, and the second insulating film is within the first opening CT1. From the portion where the second etching surface reaches the interlayer insulating layer 25 (first wall surface CT2a) and the portion which continues to the first wall surface CT2a and reaches the first relay electrode 7 (second wall surface CT2b). This is a step of forming the second opening CT2.

  The second opening CT2 is formed inside the first opening CT1 by anisotropic etching in the Z (−) direction in step S4. Further, the second insulating film 2 of the second portion 2-2 is interposed between the first opening CT1 and the second opening CT2, and the first opening CT1 and the second opening CT2. Is the dimension in the X direction of the second insulating film 2 of the second portion 2-2, that is, approximately 100 nm. For this reason, since the opening dimension W1 of the first opening CT1 is approximately 500 nm, the opening dimension W2 of the second opening CT2 is approximately 300 nm.

  As described above, in step S4, the second opening CT2 is formed inside the first opening CT1 using the second insulating film 2 of the second portion 2-2 as an etching mask without using the photolithography process. Form. In other words, the second opening CT2 is formed in a self-aligned manner without using a photolithography process. For this reason, the smaller second opening CT2 can be formed with high precision inside the first opening CT1 without being affected by the alignment error caused by the photolithography process. Further, the opening dimension W2 of the second opening CT2 is equal to the opening dimension W1 of the first opening CT1 and the X-direction dimension of the second insulating film 2 of the second portion (that is, the second dimension in step S3). The film thickness of the insulating film 2). For this reason, when the opening dimension W1 of the first opening CT1 is further reduced or the second insulating film 2 is further thickened, the opening dimension W2 of the second opening CT2 can be further reduced.

  In step S4, the photolithographic process is omitted and is not affected by alignment errors and the like, so that the pixel contact (second opening CT2) is made smaller and the organic EL device 100 is compared with the case where the photolithographic process is used. Can increase productivity.

  In step S5, as shown in FIG. 7E, titanium nitride having a thickness of about 50 nm is formed by sputtering, for example, and the surfaces of the first insulating film 1 and the second insulating film 2 and the second opening are formed. A titanium nitride film 8a is formed to cover the inside of CT2. At this time, in the titanium nitride film 8a, a recess reflecting the concave shape of the second opening CT2 is formed inside the second opening CT2.

  In step S6, as shown in FIG. 7E, tungsten is deposited by the CVD method, and tungsten is filled in the concave portion of the titanium nitride film 8a described above. Tungsten is formed other than the concave portion of the titanium nitride film 8a, such as a flat portion (surface) of the titanium nitride film 8a, so unnecessary tungsten is removed by a known technique (for example, dry etching using a fluorine-based gas). Then, the conductive material 9 filled in the concave portion of the titanium nitride film 8a is formed.

In step S7, as shown in FIG. 8A, the titanium nitride film 8a is etched in the Z (−) direction by a dry etching method using, for example, a chlorine-based gas, and the inside of the second opening CT2 is formed. A second relay electrode 8 that covers and is wider than the first opening CT1 in plan view is formed.
When etching of the titanium nitride film 8a in the Z (−) direction proceeds and the first insulating film 1 of the base film is exposed, the thickness of the exposed first insulating film 1 becomes Bd1 (approximately 50 nm). The first insulating film 1 is also etched in the Z (−) direction. That is, in step S7, the titanium nitride film 8a is etched in an over-etched manner so that the first insulating film 1 is also etched, and when the titanium nitride film 8a is over-etched, the exposed portion of the first insulating film 1 ( The first insulating film 1 is etched so that the thickness of the portion of the first insulating film 1) not covered with the second relay electrode 8 becomes Bd1 (approximately 50 nm).

  In step S8, as shown in FIG. 8B, a silicon oxide film with a thickness of about 60 nm to 70 nm is formed by plasma CVD, and then Z (( The first silicon oxide film 3 is formed by etching in the-) direction. As described above, in the dry etching using a fluorine-based gas, the etching rate of silicon nitride is smaller than the etching rate of silicon oxide. Therefore, when the first insulating film 1 (silicon nitride) is exposed, Z ( -) Directional etching substantially stops. In step S8, the silicon oxide in the first region 28B and the second region 28G and the silicon oxide in the region corresponding to the contact hole CTR1 are removed, and the first hole having the contact hole CTR1 on the first insulating film 1 is removed. The silicon oxide film 3 is formed in the third region 28R. The second relay electrode 8 and the conductive material 9 are exposed through the contact hole CTR1.

  In step S9, as shown in FIG. 8C, a silicon oxide film having a thickness of about 60 nm to 70 nm is formed by plasma CVD, and then Z ( A second silicon oxide film 4 is formed by etching in the-) direction. As described above, when the silicon oxide is etched in the Z (−) direction, the etching in the Z (−) direction is substantially stopped when the first insulating film 1 (silicon nitride) is exposed. In step S9, the silicon oxide in the first region 28B, the silicon oxide in the region corresponding to the contact hole CTG1, and the silicon oxide in the region corresponding to the contact hole CTR1 are removed, and the first region in the second region 28G is removed. A second silicon oxide film 4 having a contact hole CTG1 or a contact hole CTR1 is formed to cover the insulating film 1 and the first silicon oxide film 3 in the third region 28R. The second relay electrode 8 and the conductive material 9 are exposed through the contact hole CTG1.

  In step S10, as shown in FIG. 8D, an ITO film having a thickness of approximately 100 nm is formed by sputtering, and this is patterned to cover at least the first opening CT1 in plan view, and at least conductive. A pixel electrode 31 in contact with the material 9 is formed. In the light emitting pixel 20B, a pixel electrode 31B in contact with the second relay electrode 8 and the conductive material 9 is formed. In the light emitting pixel 20G, the pixel electrode 31G in contact with the second relay electrode 8 and the conductive material 9 is formed through the contact hole CTG1. In the light emitting pixel 20R, a pixel electrode 31R that is in contact with the second relay electrode 8 and the conductive material 9 is formed through the contact hole CTR1.

Further, in the light emitting pixel 20B, an optical distance adjustment layer 28 having a film thickness Bd1 formed of the first insulating film 1 is formed between the power supply line 14 and the pixel electrode 31B. In the light emitting pixel 20G, an optical distance adjustment layer 28 having a film thickness Gd1 composed of the first insulating film 1 and the first silicon oxide film 3 is formed between the power supply line 14 and the pixel electrode 31G. . In the light emitting pixel 20R, an optical film having a film thickness Rd1 constituted by the first insulating film 1, the first silicon oxide film 3, and the second silicon oxide film 4 between the power supply line 14 and the pixel electrode 31R. A distance adjustment layer 28 is formed.
Thereafter, a step of forming a dielectric film 29 that defines a light emitting region of the light emitting pixel 20, a step of forming the light emitting functional layer 32, a step of forming the counter electrode 33, a step of forming the sealing layer 40, and the color filter 50 are performed. Forming.
The organic EL device 100 according to this embodiment can be stably manufactured by the above manufacturing method.

As described above, in the organic EL device 100 according to this embodiment, the following effects can be obtained.
(1) The organic EL device 100 according to this embodiment has an optical resonance structure, and in the light emitting pixel 20B, the optical distance adjustment layer 28 (first insulating film 1) having a film thickness Bd1 with a resonance wavelength of 470 nm. Is provided. In the light emitting pixel 20G, an optical distance adjustment layer 28 (first insulating film 1, first silicon oxide film 3) having a film thickness Gd1 having a resonance wavelength of 540 nm is provided. In the light emitting pixel 20R, an optical distance adjustment layer 28 (first insulating film 1, first silicon oxide film 3, and second silicon oxide film 4) having a film thickness Rd1 with a resonance wavelength of 610 nm is provided. . Therefore, blue (B) light having a peak wavelength of 470 nm is emitted from the light emitting pixel 20B, green (G) light having a peak wavelength of 540 nm is emitted from the light emitting pixel 20G, and a peak wavelength of 610 nm is emitted from the light emitting pixel 20R. A red (R) light is emitted. Therefore, in the organic EL device 100 according to the present embodiment, the color purity of the light emitted from the light emitting pixels 20 can be increased and a vivid display can be provided.

  (2) The pixel electrode 31 and the first relay electrode 7 are electrically connected via the second relay electrode 8 and the conductive material 9 disposed inside the second opening CT2. . Further, the second opening CT2 is formed in a self-aligned manner inside the first opening CT1 using the second insulating film 2 of the second portion 2-2 as an etching mask without using a photolithography process. It is not affected by alignment errors caused by the photolithography process. Therefore, compared with the case where it forms using a photolitho process, smaller 2nd opening part CT2 can be formed inside 1st opening part CT1 with high precision. That is, a smaller pixel contact can be formed. Therefore, the area of the non-light emitting region (pixel contact) in the light emitting pixel 20 can be reduced, and the area of the light emitting region (openings 29B, 29G, 29R) can be increased. Therefore, the organic EL device 100 according to this embodiment can provide a bright display with a wide light emitting area.

  (3) The first insulating film 1 is subjected to a film reduction process, and the first insulating film 1 forms a part of the constituent elements of the optical distance adjustment layer 28. Further, the photolithography process is omitted in the step of forming the second opening CT2. That is, the manufacturing process is simplified compared to the configuration in which the optical distance adjustment layer 28 is formed separately from the first insulating film 1 and the configuration in which the second opening CT2 is formed by using a photolithography process. The productivity of the EL device 100 can be increased.

(Embodiment 2)
"Outline of organic EL device"
FIG. 9 corresponds to FIG. 4 and is a schematic sectional view of a light emitting region of the organic EL device according to the second embodiment. FIG. 10 corresponds to FIG. 5 and is a schematic cross-sectional view of a pixel contact of the organic EL device according to the present embodiment. FIG. 11 is a process flow showing the method for manufacturing the organic EL device according to this embodiment. 12 and 13 correspond to FIGS. 7 and 8 and are schematic cross-sectional views showing the state of the organic EL device after the respective steps shown in FIG.
Hereinafter, an overview of the organic EL device 200 according to the present embodiment will be described with reference to FIGS. 9 to 13 focusing on differences from the first embodiment. In addition, about the component same as Embodiment 1, the same code | symbol is attached | subjected and the overlapping description is abbreviate | omitted.

  In the organic EL device 200 according to this embodiment, the shape of the first insulating film 1 and the configuration of the optical distance adjustment layer 28 are different from those of the first embodiment, and other configurations are the same as those of the first embodiment. Specifically, the first insulating film 1 according to the first embodiment is disposed in the pixel contact and display area E and forms a part of the optical distance adjustment layer 28. The first insulating film 1 of the present embodiment is disposed only at the pixel contact and does not become a component of the optical distance adjustment layer 28. For this reason, in the optical distance adjustment layer 28 of the present embodiment, a new film (silicon nitride film 5) is added in place of the first insulating film 1 of the first embodiment.

As shown in FIG. 9, an optical distance adjustment layer 28 is provided between the power supply line 14 and the pixel electrode 31. The optical distance adjustment layer 28 is laminated in order along the Z (+) direction from the power supply line 14 side, the silicon nitride film 5, the first silicon oxide film 3, the second silicon oxide film 4, and the like. Consists of. The film thickness of the silicon nitride film 5 is approximately 50 nm. The film thicknesses of the first silicon oxide film 3 and the second silicon oxide film 4 are approximately 60 nm to 70 nm.
The silicon nitride film 5 is an example of the “fifth insulating film” in the present invention, the first silicon oxide film 3 is an example of the “sixth insulating film” in the present invention, and the second silicon oxide film The film 4 is an example of the “seventh insulating film” in the present invention.

  The optical distance adjustment layer 28 of the light emitting pixel 20B (first region 28B) is composed of the silicon nitride film 5 and has a film thickness Bd1 (approximately 50 nm). The optical distance adjustment layer 28 of the light emitting pixel 20G (second region 28G) is composed of the silicon nitride film 5 and the second silicon oxide film 4, and has a film thickness Gd1 (approximately 115 nm). The optical distance adjustment layer 28 of the light emitting pixel 20R (third region 28R) is composed of the silicon nitride film 5, the first silicon oxide film 3, and the second silicon oxide film 4, and has a film thickness Rd1 (approximately 170 nm). )have.

  As shown in FIG. 10, the power line 14 and the first insulating film 1 are provided with a first opening CT <b> 1 that penetrates the power line 14 and the first insulating film 1. Inside the first opening CT1, a second opening CT2 penetrating the second insulating film 2 and the interlayer insulating layer 25 is provided. Further, a second relay electrode 8 that covers the inside of the second opening CT2, the first relay electrode 7 exposed at the second opening CT2, and a part of the surface of the first insulating film 1 is covered. Is provided. A conductive material 9 is filled on the inner surface side of the second relay electrode 8.

  The first insulating film 1 is disposed between the outer edge of the second relay electrode 8 and the first opening CT1 in plan view. That is, the first insulating film 1 is disposed so as not to protrude from between the power supply line 14 and the second relay electrode 8.

  In the light emitting pixel 20 </ b> B, the silicon nitride film 5 covering the conductive material 9 and the second relay electrode 8 is provided. The silicon nitride film 5 is provided with a contact hole CTB2 that exposes the conductive material 9 and the second relay electrode 8. The pixel electrode 31B is provided on the silicon nitride film 5, and is electrically connected to the conductive material 9 and the second relay electrode 8 through the contact hole CTB2.

  In the light emitting pixel 20G, a silicon nitride film 5 and a second silicon oxide film 4 that cover the conductive material 9 and the second relay electrode 8 are provided. The silicon nitride film 5 and the second silicon oxide film 4 are provided with a contact hole CTG2 through which the conductive material 9 and the second relay electrode 8 are exposed. The pixel electrode 31G is provided on the second silicon oxide film 4, and is electrically connected to the conductive material 9 and the second relay electrode 8 through the contact hole CTG2.

  In the light emitting pixel 20 </ b> R, a silicon nitride film 5, a first silicon oxide film 3, and a second silicon oxide film 4 are provided to cover the conductive material 9 and the second relay electrode 8. The silicon nitride film 5, the first silicon oxide film 3, and the second silicon oxide film 4 are provided with a contact hole CTR 2 that exposes the conductive material 9 and the second relay electrode 8. The pixel electrode 31R is provided on the second silicon oxide film 4, and is electrically connected to the conductive material 9 and the second relay electrode 8 through the contact hole CTR2.

"Method for manufacturing organic EL device"
Next, a method for manufacturing the organic EL device 200 will be described with reference to FIGS.
As shown in FIG. 11, the process of manufacturing the organic EL device 200 includes a process of forming the power supply line 14 as the light reflection layer and the first insulating film 1 covering the power supply line 14 (step S <b> 11), A step of forming the opening CT1 (step S12), a step of depositing the second insulating film 2 (step S13), a step of forming the second opening CT2 (step S14), and the titanium nitride film 8a. A step of forming (step S15), a step of filling the conductive material 9 (step S16), a step of etching the titanium nitride film 8a (step S17), and a step of etching the first insulating film 1 (step S18). A step of depositing the silicon nitride film 5 and the first silicon oxide film 3 (step S19), a step of etching the first silicon oxide film 3 (step S20), A step of forming a silicon oxide film 4 (step S21), and includes the step of etching the silicon nitride film 5 (the step S22), and a step (step S23) of forming a pixel electrode 31.

  Steps S11 to S17 in the present embodiment are the same as steps S1 to S7 in the first embodiment.

In step S17, as shown in FIG. 12A, the titanium nitride film 8a is etched in the Z (−) direction by a dry etching method using, for example, a chlorine-based gas, and the inside of the second opening CT2 is formed. A second relay electrode 8 that covers and is wider than the first opening CT1 in plan view is formed.
When the titanium nitride film 8a is over-etched, the portion of the first insulating film 1 that is not covered with the second relay electrode 8 is also etched in the Z (−) direction.

In step S18, as shown in FIG. 12B, the first insulating film 1 is etched in the Z (−) direction using the second relay electrode 8 as an etching mask, for example, by a dry etching method using a fluorine-based gas. Etching is performed to remove the first insulating film 1 protruding from between the second relay electrode 8 and the power supply line 14.
Even in step S17, the portion of the first insulating film 1 that is not covered with the second relay electrode 8 is etched in the Z (−) direction. However, since the etching rate of the first insulating film 1 is small, In S18, the first insulating film 1 is etched by switching the reaction gas from a chlorine-based gas to a fluorine-based gas.

  In step S19, as shown in FIG. 12C, the silicon nitride film 5 and the first silicon oxide film 3 covering the conductive material 9 and the second relay electrode 8 are sequentially deposited by using, for example, a plasma CVD method. To do. The film thickness of the silicon nitride film 5 is approximately 50 nm, and the film thickness of the first silicon oxide film 3 is approximately 60 nm to 70 nm.

  In step S20, as shown in FIG. 12D, the first silicon oxide film 3 is etched in the Z (−) direction using, for example, a dry etching method using a fluorine-based gas, and the first The first silicon oxide film 3 in the region 28B, the first silicon oxide film 3 in the second region 28G, and the first silicon oxide film 3 in the region corresponding to the contact hole CTR2 are removed. As described above, in the dry etching using a fluorine-based gas, the etching rate of silicon nitride is smaller than the etching rate of silicon oxide. Therefore, when the silicon nitride film 5 is exposed, etching in the Z (−) direction is substantially performed. Stop. As a result, the first silicon oxide film 3 having the contact hole CTR2 is formed in the third region 28R.

  In step S21, as shown in FIG. 13A, a silicon oxide film having a thickness of about 60 nm to 70 nm is formed by plasma CVD, and then the silicon oxide film is formed using a dry etching method using, for example, a fluorine-based gas. Is etched in the Z (−) direction to form the second silicon oxide film 4. Specifically, in step S20, the silicon oxide film in the first region 28B, the silicon oxide film in the region corresponding to the contact hole CTG2, and the silicon oxide film in the region corresponding to the contact hole CTR2 are removed, A second silicon oxide film 4 having a contact hole CTG2 or a contact hole CTR2 is formed to cover the silicon nitride film 5 in the second region 28G and the first silicon oxide film 3 in the third region 28R.

  In step S22, as shown in FIG. 13B, the silicon nitride film 5 in the region corresponding to the contact holes CTB2, CTG2, and CTR2 is removed by using, for example, a dry etching method using a fluorine-based gas, and the light emitting pixel. A contact hole CTB2 is formed in the silicon nitride film 5 of 20B, a contact hole CTG2 is formed in the silicon nitride film 5 of the light emitting pixel 20G, and a contact hole CTR2 is formed in the silicon nitride film 5 of the light emitting pixel 20R. Through the contact holes CTB2, CTG2, and CTR2 provided in the silicon nitride film 5, the second relay electrode 8 and the conductive material 9 are exposed.

  In step S23, as shown in FIG. 13C, an ITO film having a thickness of about 100 nm is formed by sputtering, and this is patterned to cover at least the first opening CT1 in plan view, and at least A pixel electrode 31 in contact with the conductive material 9 is formed. In the light emitting pixel 20B, the pixel electrode 31B in contact with the second relay electrode 8 and the conductive material 9 is formed through the contact hole CTB2. In the light emitting pixel 20G, the pixel electrode 31G in contact with the second relay electrode 8 and the conductive material 9 is formed through the contact hole CTG2. In the light emitting pixel 20R, a pixel electrode 31R that is in contact with the second relay electrode 8 and the conductive material 9 is formed through the contact hole CTR2.

  In the manufacturing method according to the first embodiment, the first insulating film 1 is subjected to film reduction processing (dry etching processing) in step S5 so that the film thickness Bd1 (50 nm) of the optical distance adjustment layer 28 is obtained. The insulating film 1 (silicon nitride film) was used as a part of the optical distance adjustment layer 28. That is, in the manufacturing method of the first embodiment, the film thickness Bd1 of the silicon nitride film (first insulating film 1) that forms part of the optical distance adjustment layer 28 is adjusted by dry etching.

  In the manufacturing method of this embodiment, the film thickness Bd1 of the silicon nitride film (silicon nitride film 5) forming a part of the optical distance adjustment layer 28 is adjusted only by film formation by plasma CVD. When the film thickness is adjusted by etching, the etching rate varies depending on the state of the etching apparatus, the state of the substrate, etc., and there is a possibility that the amount of film reduction varies. Therefore, compared with the manufacturing method of Embodiment 1 in which the film thickness is adjusted by etching, the manufacturing method of Embodiment 2 in which the film thickness is adjusted by film formation can stably obtain the target film thickness. That is, in the manufacturing method of the present embodiment, the silicon nitride film 5 having a film thickness Bd1 (50 nm) forming a part of the optical distance adjustment layer 28 is stably formed as compared with the manufacturing method of the first embodiment. Can do.

  As described above, the organic EL device 200 according to the present embodiment includes the first embodiment in which the portion (pixel contact) where the third transistor 23 (first relay electrode 7) and the pixel electrode 31 are connected is small. In addition to the same effect, the optical distance adjustment layer 28 can be formed with higher accuracy with respect to the target film thickness as compared with the organic EL device 100 according to the first embodiment. Light having a wavelength is emitted, and the color purity of the light emitted from the light emitting pixel 20 can be further increased, thereby providing a more vivid display.

  That is, the optical distance adjustment layer 28 includes the silicon nitride film 5, the first silicon oxide film 3, and the second silicon oxide film 4 that are sequentially stacked along the Z (+) direction. The portion of the optical distance adjustment layer 28 with the film thickness Bd1 is composed of the silicon nitride film 5, and the portion of the optical distance adjustment layer 28 with the film thickness Gd1 is composed of the silicon nitride film 5 and the second silicon oxide film 4. The thickness Rd1 portion of the optical distance adjusting layer 28 is preferably composed of the silicon nitride film 5, the first silicon oxide film 3, and the second silicon oxide film 4.

(Embodiment 3)
"Outline of organic EL device"
FIG. 14 corresponds to FIG. 9 and is a schematic cross-sectional view of the light emitting region of the organic EL device according to the third embodiment. FIG. 15 corresponds to FIG. 10 and is a schematic cross-sectional view of the pixel contact of the organic EL device according to the present embodiment. FIG. 16 is a process flow showing the method for manufacturing the organic EL device according to this embodiment. FIGS. 17 and 18 correspond to FIGS. 12 and 13 and are schematic cross-sectional views showing the state of the organic EL device after the respective steps shown in FIG.
Hereinafter, an outline of the organic EL device 300 according to the present embodiment will be described with reference to FIGS. 14 to 18 focusing on differences from the second embodiment.

  In the organic EL device 300 according to the present embodiment, the configuration of the optical distance adjustment layer 28 is different from that of the second embodiment, and other configurations are the same as those of the second embodiment. Specifically, the optical distance adjustment layer 28 according to the second embodiment includes the silicon nitride film 5, the first silicon oxide film 3, and the second silicon oxide film 4 that are sequentially stacked in the Z (+) direction. Is done. The optical distance adjustment layer 28 of the present embodiment includes a first silicon oxide film 3, a second silicon oxide film 4, and a silicon nitride film 5 that are sequentially stacked in the Z (+) direction. That is, the order in which the silicon nitride film 5, the first silicon oxide film 3, and the second silicon oxide film 4 constituting the optical distance adjustment layer 28 are stacked differs between the present embodiment and the second embodiment.

As shown in FIG. 14, an optical distance adjustment layer 28 is provided between the power supply line 14 and the pixel electrode 31. The optical distance adjustment layer 28 is laminated in order along the Z (+) direction from the power supply line 14 side, the first silicon oxide film 3, the second silicon oxide film 4, the silicon nitride film 5, and the like. Consists of. The film thicknesses of the first silicon oxide film 3 and the second silicon oxide film 4 are approximately 60 nm to 70 nm. The film thickness of the silicon nitride film 5 is approximately 50 nm.
The first silicon oxide film 3 is an example of the “eighth insulating film” in the present invention, and the second silicon oxide film 4 is an example of the “ninth insulating film” in the present invention. The film 5 is an example of the “tenth insulating film” in the present invention.

  The optical distance adjustment layer 28 of the light emitting pixel 20B (first region 28B) is composed of the silicon nitride film 5 and has a film thickness Bd1. The optical distance adjustment layer 28 of the light emitting pixel 20G (second region 28G) is composed of the second silicon oxide film 4 and the silicon nitride film 5 which are sequentially stacked along the Z (+) direction. It has Gd1. The optical distance adjustment layer 28 of the light emitting pixel 20R (third region 28R) includes a first silicon oxide film 3, a second silicon oxide film 4, and a silicon nitride film that are sequentially stacked along the Z (+) direction. 5 and has a film thickness Rd1. The film thickness Bd1 of the optical distance adjusting layer 28 of the light emitting pixel 20B (first region 28B) is approximately 50 nm, and the film thickness Gd1 of the optical distance adjusting layer 28 of the light emitting pixel 20G (second region 28G) is approximately. The thickness Rd1 of the optical distance adjustment layer 28 of the light emitting pixel 20R (third region 28R) is approximately 170 nm.

  As shown in FIG. 15, in the light emitting pixel 20B, a silicon nitride film 5 covering the conductive material 9 and the second relay electrode 8 is provided. The silicon nitride film 5 is provided with a contact hole CTB3 through which the conductive material 9 and the second relay electrode 8 are exposed. The pixel electrode 31B is provided on the silicon nitride film 5, and is electrically connected to the conductive material 9 and the second relay electrode 8 through the contact hole CTB3.

  In the light emitting pixel 20G, a second silicon oxide film 4 and a silicon nitride film 5 are provided to cover the conductive material 9 and the second relay electrode 8. The second silicon oxide film 4 and the silicon nitride film 5 are provided with a contact hole CTG3 that exposes the conductive material 9 and the second relay electrode 8. The pixel electrode 31G is provided on the silicon nitride film 5, and is electrically connected to the conductive material 9 and the second relay electrode 8 through the contact hole CTG3.

  In the light emitting pixel 20R, a first silicon oxide film 3, a second silicon oxide film 4, and a silicon nitride film 5 are provided to cover the conductive material 9 and the second relay electrode 8. The first silicon oxide film 3, the second silicon oxide film 4, and the silicon nitride film 5 are provided with a contact hole CTR 3 that exposes the conductive material 9 and the second relay electrode 8. The pixel electrode 31R is provided on the silicon nitride film 5, and is electrically connected to the conductive material 9 and the second relay electrode 8 through the contact hole CTR3.

"Method for manufacturing organic EL device"
Next, a method for manufacturing the organic EL device 300 will be described with reference to FIGS.

As shown in FIG. 16, the process of manufacturing the organic EL device 300 includes a process of forming the power supply line 14 as the light reflection layer and the first insulating film 1 covering the power supply line 14 (step S <b> 31), The step of forming the opening CT1 (step S32), the step of depositing the second insulating film 2 (step S33), the step of forming the second opening CT2 (step S34), and the titanium nitride film 8a. A step of forming (step S35), a step of filling a conductive material (step S36), a step of etching the titanium nitride film 8a (step S37), and a step of etching the first insulating film 1 (step S38). The step of forming the first silicon oxide film 3 (step S39), the step of forming the second silicon oxide film 4 (step S40), and the step of forming the silicon nitride film 5 And step S41), and includes a step (step S42) of forming a pixel electrode 31.
Steps S31 to S38 in the present embodiment are the same as steps S11 to S18 in the second embodiment.

  In step S38, as shown in FIG. 17A, the first insulating film 1 is etched in the Z (−) direction using the second relay electrode 8 as an etching mask, for example, by a dry etching method using a fluorine-based gas. Etching is performed to remove the first insulating film 1 protruding from between the second relay electrode 8 and the power supply line 14.

  In step S39, as shown in FIG. 17B, a silicon oxide film having a film thickness of approximately 60 nm to 70 nm is formed using, for example, a plasma CVD method, and then a dry etching method using, for example, a fluorine-based gas is performed. The first silicon oxide film 3 is formed by etching the silicon oxide film in the Z (−) direction. The first silicon oxide film 3 is disposed in the third region 28R and has a contact hole CTR3.

  In step S40, as shown in FIG. 17C, for example, a silicon oxide film having a film thickness of about 60 nm to 70 nm is formed using, for example, a plasma CVD method, and then, for example, a dry etching method using a fluorine-based gas is used. Then, the second silicon oxide film 4 is formed by etching the silicon oxide film in the Z (−) direction. The second silicon oxide film 4 is disposed in the second region 28G and the third region 28R, and has a contact hole CTG3 and a contact hole CTR3.

  In step S41, as shown in FIG. 18A, a silicon nitride film having a film thickness of approximately 50 nm is formed using, for example, a plasma CVD method, and then, for example, a dry etching method using a fluorine-based gas is used. Then, the silicon nitride film 5 is formed by etching the silicon nitride film in the Z (−) direction. The silicon nitride film 5 is disposed in the first region 28B, the second region 28G, and the third region 28R, and has a contact hole CTB3, a contact hole CTG3, and a contact hole CTR3.

  In step S42, as shown in FIG. 18B, an ITO film having a thickness of approximately 100 nm is formed by sputtering, and this is patterned to cover at least the first opening CT1 in plan view, and at least A pixel electrode 31 in contact with the conductive material 9 is formed. In the light emitting pixel 20B, the pixel electrode 31B in contact with the second relay electrode 8 and the conductive material 9 is formed through the contact hole CTB3. In the light emitting pixel 20G, the pixel electrode 31G in contact with the second relay electrode 8 and the conductive material 9 is formed through the contact hole CTG3. In the light emitting pixel 20R, the pixel electrode 31R in contact with the second relay electrode 8 and the conductive material 9 is formed through the contact hole CTR3.

  The difference between the manufacturing method of the second embodiment and the manufacturing method of the present embodiment is that the silicon nitride film 5 constituting the optical distance adjustment layer 28 is exposed to a plasma atmosphere for etching the silicon oxide films 3 and 4. It is in whether it is done. Specifically, in the manufacturing method of the second embodiment, the silicon nitride film 5 is exposed to a plasma atmosphere for etching the silicon oxide films 3 and 4. In the manufacturing method of the present embodiment, the silicon nitride film 5 is formed after the silicon oxide films 3 and 4 are formed. Therefore, the silicon nitride film 5 is not exposed to the plasma atmosphere for etching the silicon oxide films 3 and 4. This is the difference between the manufacturing method of the second embodiment and the manufacturing method of the present embodiment.

  In the manufacturing method of the present embodiment, since the silicon nitride film 5 is not exposed to the plasma atmosphere, the etching due to the exposure to the plasma atmosphere described above does not occur. Therefore, in the manufacturing method of the present embodiment, the film thickness of the silicon nitride film 5 is controlled (formed) with higher accuracy than the manufacturing method of the second embodiment so that the target film thickness (film thickness Bd1) is obtained. )can do.

  As described above, in the organic EL device 300 according to this embodiment, the portion where the third transistor 23 (first relay electrode 7) and the pixel electrode 31 are connected (pixel contact) is small, and In addition to the same effects as those of the second embodiment, the optical distance adjustment layer 28 can be formed with higher accuracy with respect to the target film thickness than the organic EL device 200 according to the second embodiment. Light having a target resonance wavelength is emitted, so that the color purity of the light emitted from the light emitting pixel 20 can be further increased and a more vivid display can be provided.

  That is, the optical distance adjustment layer 28 includes the first silicon oxide film 3, the second silicon oxide film 4, and the silicon nitride film 5 that are sequentially stacked along the Z (+) direction. The portion of the optical distance adjustment layer 28 with the film thickness Bd1 is composed of the silicon nitride film 5, and the portion of the optical distance adjustment layer 28 with the film thickness Gd1 is composed of the second silicon oxide film 4 and the silicon nitride film 5. The thickness Rd1 portion of the optical distance adjustment layer 28 is preferably composed of the first silicon oxide film 3, the second silicon oxide film 4, and the silicon nitride film 5.

(Embodiment 4)
"Electronics"
FIG. 19 is a schematic diagram of a head mounted display as an example of an electronic apparatus.
As shown in FIG. 19, the head mounted display 1000 has two display units 1001 provided corresponding to the left and right eyes. The observer M can see characters and images displayed on the display unit 1001 by wearing the head mounted display 1000 on the head like glasses. For example, if an image in consideration of parallax is displayed on the left and right display units 1001, a stereoscopic video can be viewed and enjoyed.

  Any one of the organic EL devices 100, 200, and 300 according to the above embodiment is mounted on the display unit 1001. In the organic EL devices 100, 200, and 300, the area of the non-light emitting region (pixel contact) can be reduced and the area of the light emitting region can be increased, so that a bright display is provided. Furthermore, since the organic EL devices 100, 200, and 300 have an optical resonance structure, the color purity of light emitted from the light emitting pixels 20 is increased, and a vivid display is provided. That is, the organic EL devices 100, 200, and 300 provide a bright and vivid display. Therefore, by mounting the organic EL device on the display portion 1001, a head-mounted display 1000 with a bright and vivid display can be provided.

  Note that the electronic device on which the organic EL device is mounted is not limited to the head mounted display 1000. For example, it may be mounted on an electronic device having a display unit such as a head-up display, an electronic viewfinder of a digital camera, a portable information terminal, or a navigator. Further, the present invention is not limited to the display unit, and the present invention can be applied to an illumination device and an exposure device.

The present invention is not limited to the above-described embodiment, and can be appropriately changed without departing from the spirit or idea of the invention that can be read from the claims and the entire specification. Electronic equipment equipped with the electro-optical device is also included in the technical scope of the present invention.
Various modifications other than the above embodiment are conceivable. Hereinafter, a modification will be described.

(Modification 1)
The electro-optical device according to the present invention is not limited to the organic EL devices 100, 200, and 300 described above, and may be a liquid crystal device, for example. That is, a reflective or transmissive liquid crystal device to which the pixel contact structure and the manufacturing method thereof according to the present invention are applied is also included in the technical scope of the present invention.

(Modification 2)
A MEMS (Micro Electro Mechanical Systems) for forming a sensor, an actuator, an electronic circuit or the like having a contact portion (pixel contact) formed by the manufacturing method according to the present invention on a semiconductor substrate or an insulating substrate, and a semiconductor device, It is included in the technical scope of the present invention.
That is, a small contact hole formed by the manufacturing method according to the present invention using the first relay electrode 7 as the first layer wiring, the power supply line 14 as the second layer wiring, and the pixel electrode 31 as the third layer wiring. A MEMS substrate or a semiconductor device having a contact portion that electrically connects the first-layer wiring and the third-layer wiring through (second opening CT2) is also included in the technical scope of the present invention. .

  CT1 ... first opening, CT1a ... wall surface, CT2 ... second opening, CT2a ... first wall surface, CT2b ... second wall surface, 1 ... first insulating film, 2 ... second insulating film, DESCRIPTION OF SYMBOLS 7 ... 1st relay electrode, 8 ... 2nd relay electrode, 9 ... Conductive material, 10 ... Element substrate, 10a ... Insulating film, 10f ... Surface, 10d ... Ion implantation part, 10s ... Base material, 10w ... Well part , 11 ... scanning line, 12 ... data line, 13 ... lighting control line, 14 ... power supply line, 15 ... first interlayer insulating film, 16 ... second interlayer insulating film, 17 ... third interlayer insulating film, 20, 20B, 20G, 20R: light-emitting pixels, 21: first transistor, 22: second transistor, 23: third transistor, 23g: gate electrode, 23s: source electrode, 24: storage capacitor, 24a: one electrode, 24b: other Electrode, 24c ... capacity insulating film, 25 ... interlayer Edge layer, 28 ... optical distance adjustment layer, 28B ... first region, 28G ... second region, 28R ... third region, 29 ... dielectric film, 29B, 29G, 29R ... opening, 30 ... organic EL element , 31, 31B, 31G, 31R ... pixel electrode, 32 ... light emitting functional layer, 33 ... counter electrode, 40 ... sealing layer, 41 ... first sealing layer, 42 ... buffer layer, 43 ... second sealing layer, 50 ... Color filter, 50B, 50G, 50R ... Colored layer, 71 ... Resin layer, 70 ... Sealing substrate, 100, 200, 300 ... Organic EL device, CTG, CTR ... Contact hole, W1, W2 ... Opening dimensions.

Claims (13)

An electro-optical device comprising: a base material provided with a transistor; and a display pixel electrode disposed on the first surface side of the base material and driven by the transistor,
A first relay electrode electrically connected to the transistor;
An interlayer insulating layer covering the first relay electrode;
A conductive layer provided in contact with the interlayer insulating layer between the interlayer insulating layer and the pixel electrode;
A first insulating film stacked on the pixel electrode side on the surface of the conductive layer;
A first opening having a wall surface along a first direction from the first surface toward the pixel electrode, and penetrating the first insulating film and the conductive film;
A second insulating film covering the wall surface;
A first portion formed inside the first opening with the second insulating film interposed therebetween, and a second portion formed continuously from the first portion and reaching the first relay electrode A second opening consisting of:
A second relay electrode covering at least the inside of the second opening;
A conductive material filled on the inner surface side of the second relay electrode;
With
The pixel electrode covers at least the first opening in plan view, and the first relay via the conductive material and the second relay electrode provided inside the second opening. An electro-optical device that is electrically connected to an electrode.   The electro-optical device according to claim 1, wherein the second relay electrode is provided wider than the first opening in a plan view. The conductive layer is made of a light reflective material,
The conductive layer, the optical distance adjustment layer, the pixel electrode, the light emitting functional layer, and the counter electrode are stacked in this order along the first direction on the first surface side of the base material. Light emitting area is arranged,
The optical distance adjusting layer includes a first layer thickness portion, a second layer thickness portion thicker than the first layer thickness portion, and a third layer thickness thicker than the second layer thickness portion. A layer thickness portion of, and
The pixel electrode includes a first pixel electrode provided in the first layer thickness portion, a second pixel electrode provided in the second layer thickness portion, and a third layer thickness The electro-optical device according to claim 1, further comprising a third pixel electrode provided in the portion.   4. The electro-optical device according to claim 3, wherein the first insulating film is provided over a region where the pixel electrode is disposed and forms a part of the optical distance adjustment layer.   4. The device according to claim 1, wherein the first insulating film is disposed between an outer edge of the second relay electrode and the first opening in a plan view. 5. The electro-optical device described. The optical distance adjustment layer includes the first insulating film, the third insulating film, and the fourth insulating film, which are sequentially stacked along the first direction.
The portion of the first layer thickness is composed of the first insulating film,
The portion of the second layer thickness is composed of the first insulating film and the fourth insulating film,
The third layer thickness portion includes the first insulating film, the third insulating film, and the fourth insulating film,
5. The electro-optical device according to claim 3, wherein the constituent material of the third insulating film and the constituent material of the fourth insulating film are silicon oxide. The optical distance adjustment layer includes a fifth insulating film, a sixth insulating film, and a seventh insulating film, which are sequentially stacked along the first direction.
The portion of the first layer thickness is composed of the fifth insulating film,
The portion of the second layer thickness is composed of the fifth insulating film and the seventh insulating film,
The third layer thickness portion includes the fifth insulating film, the sixth insulating film, and the seventh insulating film,
6. The electric material according to claim 3, wherein the constituent material of the fifth insulating film is silicon nitride, and the constituent material of the sixth insulating film and the seventh insulating film is silicon oxide. Optical device. The optical distance adjustment layer includes an eighth insulating film, a ninth insulating film, and a tenth insulating film, which are sequentially stacked along the first direction.
The portion of the first layer thickness is composed of the tenth insulating film,
The portion of the second layer thickness is composed of the ninth insulating film and the tenth insulating film,
The third layer thickness portion is composed of the eighth insulating film, the ninth insulating film, and the tenth insulating film,
6. The electric material according to claim 3, wherein the constituent material of the eighth insulating film and the ninth insulating film is silicon oxide, and the constituent material of the tenth insulating film is silicon nitride. Optical device.   9. The interlayer insulating layer includes at least a silicon oxide film, and a constituent material of the first insulating film and the second insulating film is silicon nitride. Electro-optic device.   The electro-optical device according to claim 1, wherein the conductive material is tungsten, and the second relay electrode is titanium nitride.   An electronic apparatus comprising the electro-optical device according to claim 1. A display device comprising: a base material provided with a transistor; and a display pixel electrode disposed on the first surface side of the base material and driven by the transistor,
A first relay electrode electrically connected to the transistor; an interlayer insulating layer covering the first relay electrode; and the interlayer insulating layer provided between the interlayer insulating layer and the pixel electrode. A conductive layer and a first insulating film in contact with the conductive layer;
The conductive layer and the first insulating film are subjected to anisotropic etching in a second direction from the pixel electrode toward the first surface, and the conductive layer and the first insulating film are etched surfaces. Forming a first opening in which a wall surface along the second direction reaches the interlayer insulating layer;
Forming a second insulating film having a portion covering the wall surface and a portion covering the surface of the interlayer insulating layer;
The second insulating film and the interlayer insulating layer are subjected to anisotropic etching in the second direction, and the etching surface of the second insulating film is in the interlayer insulating film in the first opening. Forming a second opening comprising a first portion extending to the first portion and a second portion having an etching surface of the interlayer insulating layer continuous to the first portion and reaching the first relay electrode And a process of
Covering the inside of the second opening and forming a second relay electrode wider than the first opening in plan view;
Filling the inner surface side of the second relay electrode with a conductive material;
Forming the pixel electrode covering at least the first opening in a plan view and in contact with at least the conductive material;
A method for manufacturing an electro-optical device.   13. The electro-optic according to claim 12, wherein in the step of forming the second relay electrode, the first insulating film protruding from between the second relay electrode and the conductive layer is also etched. Device manufacturing method.

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