KR101760521B1 - Liquid crystal display device - Google Patents

Abstract

The display device includes a PCB including a timing controller for generating a gate driving control signal, a display panel electrically connected to the PCB and including a display area and a non-display area surrounding the display area, and a gate built in the non- Block and a level shifter for generating a gate driving control voltage for supplying the gate driving control signal to the gate built-in block based on the gate driving control signal. The level shifter is electrically connected to one side of the display panel.

Description

Liquid crystal display device

The embodiment relates to a display device.

Various display devices capable of displaying information are being developed. The display device may be, for example, a liquid crystal display device, a plasma display panel device, an organic electro-luminescence display device, an electrophoretic display device, And a semiconductor light-emitting display device.

Among them, the liquid crystal display device is excellent in image quality, has advantages such as light weight, thinness, and low power consumption, and is popular as a representative display device. For example, liquid crystal displays are widely employed in mobile phones, navigation systems, notebooks, and televisions.

A display device including a liquid crystal display device has a schematic structure and includes a display panel for displaying information and a drive module for generating a signal to be provided to the display panel.

Since various signals are generated in the driving module and provided to the display panel, a plurality of signal lines for supplying various signals are formed in the connection portion between the driving module, the display panel itself, the driving module, and the display panel.

However, when a plurality of signal lines are formed in the driving module, signal distortion or signal loss may occur due to interference between signals flowing to the signal lines.

Further, due to the area occupied by the plurality of signal lines in the driving module and the connecting portion, the size of each of the driving module and the connecting portion increases, and there is a limitation in adding other signal lines to the driving module and the connecting portion.

The embodiment provides a display device capable of minimizing a signal line.

The embodiment provides a display device capable of improving image quality.

The embodiment provides a display device capable of maximizing the design margin.

According to an embodiment, the display device comprises: a PCB including a timing controller for generating a gate driving control signal; A display panel electrically connected to the PCB and including a display area and a non-display area surrounding the display area; A gate built-in block formed in the non-display area; And a level shifter for generating a gate driving control voltage for supplying to the gate built-in block based on the gate driving control signal, wherein the level shifter is electrically connected to one side of the display panel.

According to an embodiment, the display device comprises: a PCB including a timing controller for generating a gate driving control signal; A display panel electrically connected to the PCB and including a display area and a non-display area surrounding the display area; A gate built-in block formed in the non-display area; And a level shifter for generating a gate driving control voltage for supplying the gate driving control signal to the gate built-in block based on the gate driving control signal, wherein the level shifter is provided in the non-display area on one side of the display area with the gate built- Respectively.

According to an embodiment, the display device includes a PCB including a timing controller for generating first and second gate driving control signals; A display panel electrically connected to the PCB and including a display area and a non-display area surrounding the display area; A first gate built-in block formed in a non-display area on a first side of the display area; A second gate built-in block formed in a non-display area on a second side of the display area; A first level shifter for generating a first gate control voltage for supplying to the first gate built-in block based on the first gate driving control signal; And a second level shifter for generating a second gate driving control voltage for supplying to the second gate built-in block based on the second gate driving control signal, wherein the first and second level shifters are connected to the display panel As shown in FIG.

According to an embodiment, the display device includes a PCB including a timing controller for generating first and second gate driving control signals; A display panel electrically connected to the PCB and including a display area and a non-display area surrounding the display area; A first gate built-in block formed in a non-display area on a first side of the display area; A second gate built-in block formed in a non-display area on a second side of the display area; A first level shifter for generating a first gate control voltage for supplying to the first gate built-in block based on the first gate driving control signal; And a second level shifter for generating a second gate driving control voltage for supplying to the second gate built-in block based on the second gate driving control signal, wherein each of the first and second level shifters comprises: And is formed adjacent to the first and second gate built-in blocks in the non-display area of the first and second sides of the display area.

In an embodiment, a level shifter film including a level shifter IC may be connected to one side of a liquid crystal display panel, or a level shifter may be formed on a liquid crystal display panel. The level shifter IC outputs more signals to the output side than the input side, and many signal lines are required to accommodate these output signals. When the level shifter IC is formed on the main PCB, a number of signal lines must be formed in order to accommodate output signals of the level shifter IC in the main PCB, the connecting member, the data PCB, and the data TCP, . However, as in the embodiment, since the level shifter IC and the like are not mounted on the main PCB, many signal lines need not be formed in order to accommodate output signals of the level shifter IC in the main PCB, the connecting member, the data PCB, and the data TCP . Therefore, the design margin of the main PCB, the connection member, the data PCB, and the data TCP can be maximized, and the sizes of the main PCB, the connection member, the data PCB, and the data TCP can be minimized.

In the embodiment, since the level shifter IC or the level shifter is formed as close as possible to the gate built-in block formed in the non-display area of the liquid crystal display panel, the output signal of the level shifter IC or the level shifter can be supplied to the gate built- have. Therefore, the embodiment can prevent a malfunction due to the delay of the output signal, thereby improving the image quality.

A pair of gate built-in blocks capable of supplying a gate high voltage to both sides of the gate lines are formed so that gate high voltages are simultaneously supplied from both sides of the gate lines so that the signal delay of the gate high voltage And quality of image quality can be improved.

1 is a block diagram showing a liquid crystal display device according to a first embodiment of the present invention.
2 is a diagram showing an input / output waveform of a level shifter in the liquid crystal display of FIG.
3 is a block diagram showing a liquid crystal display device according to a second embodiment of the present invention.
4 is a block diagram showing a liquid crystal display device according to a third embodiment of the present invention.
5 is a block diagram showing a liquid crystal display device according to a fourth embodiment of the present invention.
6 is a graph showing an output characteristic of a level shifter in the liquid crystal display devices of the first to fourth embodiments.

In the description of the embodiments, it is to be understood that each layer (film), region, pattern or structure is formed "on" or "under" a substrate, each layer Where stated, the terms " on "and" under "include both the meaning of" directly "and" indirectly ". In addition, the criteria for above or below each layer will be described with reference to the drawings.

Hereinafter, embodiments will be described in detail with reference to the accompanying drawings.

However, the present invention is applicable to other display devices including a liquid crystal display device, for example, a plasma display device, an organic light emitting display device, an electrophoretic display device, and a semiconductor light emitting display device As shown in FIG.

FIG. 1 is a block diagram showing a liquid crystal display device according to a first embodiment of the present invention, and FIG. 2 is a diagram showing input and output waveforms of a level shifter in the liquid crystal display device of FIG.

1, the liquid crystal display device of the first embodiment may include a main PCB 10, a data PCB 30, a data TCP 40, a level shifter film 50, and a liquid crystal display panel 60 .

The main PCB 10 may include a timing controller 12. The timing controller 12 will be described later in detail.

The main PCB 10 and the data PCB 30 may be electrically connected to each other by a connecting member 20. The connecting member 20 may be, for example, a flexible flat cable (FFC) or a flexible printed circuit (FPC).

The connecting member 20 may include a plurality of signal lines electrically insulated from each other. The signal lines may be made of a metal material having an excellent electrical conductivity.

For example, the connecting member 20 may have a plurality of signal lines spaced from each other on a base flexible film, and an electrical insulating film may be formed between the signal lines and the signal lines. The insulating layer may be formed of a silicon-based inorganic insulating material or an organic insulating material such as BCB (Benzocyclo Butane).

The embodiment may include a plurality of data TCPs 40.

The data TCP 40 may include at least one data driver IC 42. The data TCP 40 may be electrically connected between the data PCB 30 and the liquid crystal display panel 60.

The data TCP 40 may include a plurality of signal lines for supplying a plurality of signals generated in the main PCB 10.

The level shifter film 50 may include at least one level shifter IC 52. The level shifter IC 52 and the level shifter film 50 may be referred to as a level shifter. The level shifter film 50 may be electrically connected to the liquid crystal display panel 60. For example, the level shifter film 50 may be electrically connected to one side of the liquid crystal display panel 60, for example, to the left side of the liquid crystal display panel 60. The level shifter film 50 may be electrically connected to the liquid crystal display panel 60 through a COF (Chip On Film) method or a COB (Chip On Board) method. For example, after an anisotropic conductive film (ACF) including a plurality of conductive balls is placed on the liquid crystal display panel 60 and the level shifter film 50 is placed on the anisotropic conductive film, Heat is applied to the display panel 60 while the level shifter film 50 is pressed. The input / output terminals of the level shifter film 50 are formed at the ends of the first and second line-on-glass (LOG) signal lines of the liquid crystal display panel 60 via the conductive balls of the anisotropic conductive film Terminals. ≪ / RTI >

The liquid crystal display panel 60 may include a display area DA including a plurality of pixels P for displaying information and a non-display area NA excluding the display area DA. For example, the non-display area NA may be defined to surround the display area DA.

In the display area DA, a plurality of gate lines GL1 to GLn and a plurality of data lines DL1 to DLm may be arranged to intersect with each other. A plurality of pixels P may be defined by the intersection of the gate lines GL1 ... GLn and the data lines DL1 ... DLm.

Each pixel P may include at least one thin film transistor. The thin film transistor may be formed by a semiconductor process.

The thin film transistor includes a gate electrode extended from the gate line and electrically connected to the gate line, a semiconductor layer forming a channel for current flow on the gate electrode, a source electrode spaced apart from the semiconductor layer, Drain electrode. The source electrode may extend from the data line and be electrically connected to the data line.

A gate insulating layer for electrical insulation may be formed between the gate electrode and the semiconductor layer.

The drain electrode may be electrically connected to the pixel electrode. The pixel electrode may be formed in each of the pixels P.

A passivation film for electrical insulation may be formed between the drain electrode and the pixel electrode. In this case, the pixel electrode may be electrically connected to the drain electrode through a contact hole formed in the passivation film corresponding to the drain electrode.

The data lines extend from the display area DA to the non-display area NA, specifically, the non-display area NA on the upper side of the display area DA, And may be electrically connected to the data driver IC 42. When the data TCP 40 is connected to the lower side of the liquid crystal display panel 60, the data lines may extend to the non-display area NA on the lower side of the display area DA. In other words, the extension direction of the data lines may be determined by the connection direction of the liquid crystal display panel 60 of the data TCP 40. [

The gate lines may extend from the display area DA to the non-display area NA, specifically, the non-display area NA of the left side of the display area DA.

The gate built-in block 70 may be formed on one side of the display area DA, for example, the non-display area NA on the left side of the display area DA. The gate built-in block 70 may be electrically connected to the level shifter IC 52 of the level shifter film 50.

When the level shifter film 50 is connected to the right side of the liquid crystal display panel 60, the gate built-in block 70 may be formed in the non-display area NA on the right side of the display area DA have.

The gate built-in block 70 may include a plurality of shift registers 72-1 to 72-n.

Each of the shift registers 72-1 ... 72-n may include a plurality of transistors. The transistors may have the same structure as the thin film transistors of the display area DA of the liquid crystal display panel 60 and may be formed by the same process, that is, by a semiconductor process. In other words, when forming the thin film transistors of the liquid crystal display panel 60, the transistors included in the shift registers 72-1 ... 72-n may be formed at the same time.

The input terminals of the shift registers 72-1 ... 72-n may be electrically connected to the level shifter IC 52 in common. Each output terminal of the shift registers 72-1 ... 72-n may be electrically connected to a corresponding gate line. The shifter registers 72-1 to 72-n may be cascade-connected to each other. For example, the output signal of the shift register of the previous stage, for example, the gate high voltage, may be supplied to the corresponding gate line and the current shift register. The gate high voltage may be one of the clock signals CLK1 to CLK8. The gate high voltage may be an analog voltage of 27V. Therefore, the gate high voltage may be a pulse having a high level of 27V. In one frame, a gate high voltage having a high level pulse is supplied to a specific gate line, and thereafter a gate low voltage having a low level, for example, a low level of -5V, may be supplied.

The output signal of the first shift register 72-1 may be supplied to the corresponding first gate line GL1 and the second shift register 72-2.

The timing controller 12 receives a vertical synchronizing signal Vsync, a horizontal synchronizing signal Hsync, a data clock signal Dclk and a data enable signal DE from a video card. Also, the timing controller 12 may receive a data signal including information from the video card.

The video card may be included in, for example, a cellular phone, a navigation system, a notebook or a television.

The timing controller 12 generates a gate driving control signal GDC and data GDC using the vertical synchronizing signal Vsync, the horizontal synchronizing signal Hsync, the data clock signal Dclk, and / or the data enable signal DE. The driving control signal DDC can be generated.

The gate driving control signal GDC and the data driving control signal DDC may be, for example, a digital signal between 0V and 3V.

The data driving control signal DDC may include a source start pulse signal SSP, a source shift clock signal SSC, a source output enable signal SOE and a polarity signal POL. The source start pulse signal SSP is a signal for controlling the timing of supplying data for the first time in one frame and the source shift clock signal SSC is a signal for controlling the timing of supplying data for one line, The output enable signal SOE is a signal for controlling the output of data for one line, and the polarity signal POL may be a signal for controlling the polarity inversion.

The gate driving control signal GDC may include a start signal VSTin, a rising time control signal GCLK, a polling time control signal MCLK, and a deterioration prevention signal E / O. The starting signal VSTin is a signal for controlling the start of one frame and the rising time control signal GCLK and the polling time control signal MCLK are a plurality of clock signals for driving a plurality of gate lines of the liquid crystal display panel. And the polling time may be a signal for controlling the rising time and the polling time, respectively. The deterioration preventing signal E / O may be a signal for controlling the deterioration of the level shifter.

The data driving control signal DDC may be supplied to the data driver IC 42 of the data TCP 40 via the connecting member 20 and the data PCB 30 together with a data signal. The data driver IC 42 converts the data signal into an analog data voltage according to the data driving control signal DDC and then outputs the analog data voltage to the data lines DL1 ... DLm of the liquid crystal display panel 60 Can supply.

The gate driving control signal GDC is supplied to the level shifter IC 52 of the level shift film 50 via the connecting member 20, the data PCB 30 and the data TCP 40 . At least one first line-on-glass (LOG) signal line for supplying a gate driving control signal (GDC) from the data TCP 40 to the level shifter film 50, May be formed in the region NA. The first LOG signal lines may be formed on the same layer with the same material as any one of the gate line, the data line, and the pixel electrode.

A plurality of signal lines for supplying the gate driving control signal GDC may be formed in the connecting member 20, the data PCB 30, and the data TCP 40, respectively. Signal lines for supplying the gate driving control signal GDC may be formed in any one of the plurality of data TCPs 40. The gate driving control signal GDC includes a start signal VSTin, a rising time control signal GCLK, a polling time control signal MCLK and an anti-degradation signal E / O, Line may be required. Thus, at least five signal lines may be formed on the connection member, the data PCB and the data PCB.

The level shifter film 50 may include at least one level shifter IC 52. The level shifter IC 52 may be mounted on the level shifter film 50 using a wire bonding method or a chip bonding method.

The level shifter IC 52 generates a gate start voltage GVST, a plurality of gate clock voltages CLK1 to CLK8, a deterioration prevention voltage Vdd_e / o, and a reset voltage Vcc based on the gate driving control signal GDC RESET). ≪ / RTI > The gate driving control voltage may be an analog voltage of -5V to 27V. That is, when the gate start voltage GVST, the gate clock voltages CLK1 to CLK8, the deterioration prevention voltage Vdd_e / o, and the reset voltage RESET are low, the analog voltage becomes -5 V, State, it can be an analog voltage of 27V.

The input / output waveform of the level shifter IC 52 is shown in Fig.

As shown in Fig. 2, the level shifter IC 52 can increase the potential of the start signal VSTin of 3V to generate a gate start voltage GVST having an analog voltage of 27V. The gate start voltage GVST may have the same width as the start signal VSTin or at least a large width.

The level shifter IC 52 may generate a plurality of gate clock voltages CLK1 to CLK8 based on the rising time control signal GCLK and the polling rising time control signal MCLK.

The rising time control signal GCLK controls a rising time of the gate clock voltages CLK1 to CLK8 and the polling time control signal MCLK controls a polling time of the gate clock voltages CLK1 to CLK8 can do.

The polling time control signal MCLK may have a temporal interval with the rising time control signal GCLK. That is, the first pulse of the polling time control signal MCLK may be generated at a time interval from the generation of the first pulse of the rising time control signal GCLK. The high-level width of each of the gate clock voltages CLK1 to CLK8 can be defined by such a time interval. This adjustment of the time interval allows two gate clock voltages CLK1 and CLK2, four gate clock voltages CLK1 to CLK4, six gate clock voltages CLK1 to CLK6 or eight gate clock voltages CLK1 to CLK8 may be generated.

The level shifter IC 52 can increase the potential of the deterioration preventing voltage (E / O) of 3V to generate the deterioration preventing voltage (Vdd_e / o) having an analog voltage of 27V. The deterioration preventing voltage Vdd_e / o may have the same width as the deterioration preventing voltage E / O or may have at least a large width.

On the other hand, the level shift IC 52 may generate a reset voltage RESET. The reset voltage RESET may be generated based on the start signal VSTin of 3V. In Fig. 2, the start signal VSTin is shown as having a pulse having one high level, but another pulse having a high level before this pulse can be generated. The reset voltage RESET can be generated in the level shifter IC 52 by this another pulse.

For example, the one pulse may be referred to as a first pulse, and the another pulse may be referred to as a second pulse.

The level shifter IC 52 may generate a gate start voltage GVST based on the first pulse and generate a reset voltage RESET based on the second pulse.

The reset voltage RESET may have the same width as the second pulse or at least a large width. The reset voltage RESET may be an analog voltage having a high level of 27V.

The reset voltage RESET may be generated any time during a vertical blank period of the vertical synchronization signal Vsync. For example, the reset voltage RESET may be generated at the start time of the vertical blank period, that is, at a high level to a low level.

The reset voltage RESET may initialize a plurality of shift registers 72-1 to 72-n of the gate built-in block 70. [ Accordingly, during the frame, the shift registers 72-1 ... 72-n of the gate built-in block 70 sequentially supply the output signals to the corresponding gate lines GL1 ... GLn, The shift registers 72-1 to 72-n of the gate built-in block 70 are reset by the reset voltage RESET during a vertical blank period of the vertical synchronization signal Vsync, Can be initialized. The reset voltage RESET may be synchronized to the start time of the vertical blank period, that is, the high-level polling time point. The vertical synchronization signal Vsync has a high level during a frame and can have a low level during a vertical blank interval between frames. Therefore, the reset voltage RESET can be synchronized at a polling time point falling from a high level to a low level in the vertical synchronization signal Vsync. For example, the reset voltage RESET may be a rising time point that is increased from a low level to a high level at a polling time falling from the high level to the low level. At this time, the polling time point of the reset voltage RESET may be set at any point in the vertical blank period of the vertical synchronization signal Vsync. The embodiment is not limited thereto. For example, the polling time point of the reset voltage RESET may be set to any of the following frames after the vertical blank period.

The shift registers 72-1 to 72-n of the gate built-in block 70 may be initialized after the rising time point of the reset voltage RESET.

A gate driving control voltage VLD including a gate start voltage GVST, a plurality of gate clock voltages CLK1 to CLK8, a deterioration prevention voltage Vdd_e / o, and a reset voltage RESET output from the level shifter IC 52, Can be supplied to the respective shift registers 72-1 ... 72-n of the gate built-in block 70.

A plurality of second line on glasses (not shown) are interposed between the level shift film 50 and the gate built-in block 70 so that the gate driving control voltage output from the level shifter film 50 is supplied to the gate built- (LOG) signal lines may be formed. In order to separately supply the gate start voltage GVST, the plurality of gate clock voltages CLK1 to CLK8, the deterioration prevention voltage Vdd_e / o, and the reset voltage RESET, at least 12 second line on- Signal lines can be formed.

Thus, the second line on glass (LOG) signal lines may have at least a greater number of lines than the first line on glass (LOG) signal lines. That is, at least more voltages than the signals input to the level shifter IC may be output from the level shifter IC 52.

If the level shifter IC is mounted on the main PCB or the source PCB, the connection member, the data PCB and / or the data TCP may be connected to the signal line corresponding to the voltages in order to supply many kinds of voltages of the level shifter IC. . Accordingly, a large number of signal lines, e.g., at least 12 signal lines, are formed in the connection member, the data PCB, and / or the data TCP. Due to the occupied area of these signal servants, it is not easy to form other signal lines in the connection member, the data PCB and / or the data TCP. In addition, as many signal lines are formed in the connection member, the data PCB, and / or the data TCP, the distance between the signal lines becomes narrow, so that interference between voltages supplied to adjacent signal lines occurs, Voltage distortion or voltage loss may occur.

The level shifter film 50 including the level shifter IC 52 is electrically connected to one side of the liquid crystal display panel 60 according to the embodiment, Driving control voltages may be supplied to the gate built-in block 70 through second line-on-glass (LOG) signal lines formed in the liquid crystal display panel 60. In other words, the twelve voltages output from the level shifter IC 52 do not pass through the connecting member 20, the data PCB 30 and / or the data TCP 40, ), The design margin of the data PCB 30 and / or other signal lines of the data TCP 40 can be maximized, and the possibility of interference between signals supplied to adjacent signal lines can be minimized.

On the other hand, in the embodiment, since the level shifter IC 52 of the level shifter film 50 is arranged very close to the gate built-in block, the gate driving control voltage outputted from the level shifter IC, for example, the gate start voltage GVST, The output characteristics of the output waveforms of the plurality of gate clock voltages CLK1 to CLK8, the deterioration preventing voltage Vdd_e / o, and the reset voltage RESET can be input to the gate built-in block 70 unchanged.

6, A is a graph showing the output waveform of the gate driving control voltage output from the level shifter IC input to the gate built-in block when the level shifter IC is disposed on the main PCB, Is a graph showing the output waveform of the gate driving control voltage outputted from the level shifter IC input to the gate built-in block when the level shifter IC is disposed adjacent to the liquid crystal display panel.

As shown in the graph of FIG. 2A, the gate driving control voltage inputted to the gate built-in block is the resistance component of the signal lines of the main PCB, the connecting member, the data PCB, and the data TCP, respectively, And the delay due to the capacitance component, the rising time interval and the polling time interval are delayed for a long time.

The gate driving control voltage input to the gate built-in block 70 passes through only the second line on glass (LOG) signal lines formed on the liquid crystal display panel 60, so that no signal delay occurs The rising time interval and the polling time interval are hardly generated.

Therefore, in the embodiment, since the level shifter film 50 including the level shifter IC 52 is disposed as close as possible to the liquid crystal display panel 60, the gate driving control voltage output from the level shifter IC 52 is the signal It is possible to directly input the signal to the gate built-in block 70 without delay, thereby preventing defects such as malfunction and improving the image quality.

3 is a block diagram showing a liquid crystal display device according to a second embodiment of the present invention.

The second embodiment is substantially the same as the first embodiment except that another level shifter film 57 and another gate built-in block 80 are added.

Therefore, in the second embodiment, the same reference numerals are given to the same constituent elements as those in the first embodiment, and a detailed description thereof will be omitted.

3, a first level shifter film 54 is electrically connected to a first side of the liquid crystal display panel 60 and a second level shifter film 57 (not shown) is formed on a second side of the liquid crystal display panel 60. [ Can be electrically connected. The second side may be the opposite side of the first side. For example, the first side may be the left side of the liquid crystal display panel 60, and the second side may be the right side of the liquid crystal display panel 60. The first level shifter film 54 may include a first level shifter IC 56 and the second level shifter film 57 may include a second level shifter IC 58.

The first gate built-in block 70 is formed in the non-display area NA on the left side of the display area DA of the liquid crystal display panel 60 and the right side of the display area DA of the liquid crystal display panel 60 The second gate built-in block 80 can be formed in the non-display area NA of the second gate built-in block 80. [

The first gate built-in block 70 includes a plurality of shift registers 72-1 to 72-n, and the second gate built-in block 80 includes a plurality of shift registers 74-1 to 74-n. ..., 74-n.

For example, the first gate line GL1 is connected to the first shift register 72-1 of the first gate built-in block 70 and the first shift register 74-1 of the second gate built- Can be connected.

The shift registers 72-1 to 72-n, 74-1 to 74-n may be cascade-connected to each other.

Display area NA of the liquid crystal display panel 60 between any one data TCP of the data TCP 40, for example, the first data TCP and the first level shifter film 54, Display area NA of the liquid crystal display panel 60 between the first level shifter film 54 and the first gate built-in block 70 is formed in the second line on glass (LOG) signal lines may be formed.

Display area NA of the liquid crystal display panel 60 between another data TCP of the data TCP 40, for example, the last data TCP and the second level shifter film 57, Display area NA of the liquid crystal display panel 60 between the second level shifter film 57 and the second gate built-in block 80 is formed in the fourth line on glass LOG) signal lines may be formed.

The timing controller 14 may generate the first and second gate driving control signals GDC and the data driving control signal DDC.

The data driving control signal DDC may be supplied to the data driver IC 42 of the data TCP 40 via the connection member 20 and the data PCB 30 together with the data signal.

The first gate driving control signal GDC passes through the connecting member 20, the data PCB 30 and the first data TCP 40 and is also supplied to the first line on glass (LOG) signal lines of the first level shifter film 54 to the first level shifter IC 56 of the first level shifter film 54. At the same time, the second gate driving control signal GDC is transmitted via the connecting member 20, the data PCB 30 and the last data TCP 40, May be supplied to the second level shifter IC (58) of the second level shifter film (57) via the LOG signal lines.

The first gate driving control signal GDC supplied to the first level shifter IC 56 and the second gate driving control signal supplied to the second level shifter IC 58 are the same. That is, they may be the same start signal VSTin, the same rising time control signal GCLK, the same polling time control signal MCLK, and the same deterioration preventing signal E / O. For example, the size and width of each signal can be the same.

The first level shifter IC 56 can generate a first gate driving control voltage which is an analog voltage of 27V from the first gate driving control signal GDC1. The first gate driving control voltage may be supplied to the first gate built-in block 70 via second line on glass (LOG) signal lines of the non-display area NA of the liquid crystal display panel 60 have.

The second level shifter IC 58 can generate a second gate driving control voltage which is an analog voltage of 27V from the second gate driving control signal GDC2. The second gate driving control voltage may be supplied to the second gate built-in block 80 via the fourth line on glass (LOG) signal lines of the non-display area NA of the liquid crystal display panel 60 have.

Therefore, the shift registers 72-1 to 72-n included in the first gate built-in block 70 and the shift registers 74-1 to 74-n included in the second gate built- The gate lines GL1 ... GLn of the display area DA of the liquid crystal display panel 60 can be sequentially driven by the scan lines 74-n. For example, the first gate line GL1 is connected to the output signal of the first shift register 72-1 of the first gate built-in block 70 and the output signal of the first shift register 74-1 of the second gate built- Can be driven simultaneously by the output signal of the inverter.

The thin film transistors of the pixels P electrically connected to the gate lines GL1 ... GLn are turned on by driving the gate lines GL1 ... GLn and the data lines DL1 ... DLm May be supplied to the pixel electrode via the thin film transistor.

A common electrode is formed opposite to the pixel electrode, and liquid crystals may be interposed between the pixel electrode and the common electrode. Accordingly, the liquid crystal is displaced by the data voltage applied to the pixel electrode and the common voltage applied to the common electrode, and the transmission / blocking of the light is controlled thereby to display the information.

4 is a block diagram showing a liquid crystal display device according to a third embodiment of the present invention.

The third embodiment is almost the same as the first embodiment except that the level shifter is directly embedded in the liquid crystal display panel.

Therefore, in the third embodiment, the same reference numerals are given to the same constituent elements as those in the first embodiment, and a detailed description thereof will be omitted.

Referring to FIG. 4, a level shifter 90 may be formed in the non-display area NA of the liquid crystal display panel 60.

The gate built-in block 70 may be formed on one side of the display area DA of the liquid crystal display panel 60, for example, on the left side. The gate built-in block 70 may include a plurality of shift registers 72-1 to 72-n. Each of the shift registers 72-1 to 72-n may be electrically connected to corresponding gate lines GL1 to GLn.

The output signals of the shift registers 72-1 to 72-n may be supplied to the corresponding gate lines GL1 to GLn. For example, the output signal output from the first shift register 72-1 may be supplied to the corresponding gate line GL1 and the second shift register 72-2. The output signal may be a gate high voltage having a high level pulse of 27V. The thin film transistor connected to the gate line may be turned on by the gate high voltage. In addition, the operation of the second shift register 72-2 can be started by the gate high voltage.

The first shift register 72-1 can be started by the gate start voltage GVST of the gate driving control voltage inputted from the level shifter 90

The level shifter 90 may be formed as close as possible to the gate built-in block 70. The level shifter 90 is formed so as to be as close as possible to the gate built-in block 70 so that the gate driving control voltage output from the level shifter 90 can be input to the gate built-in block 70 without any signal delay . Therefore, the embodiment does not cause a malfunction due to the signal delay and can improve the quality of image quality.

The level shifter 90 is connected to the non-display area NA of the liquid crystal display panel 60 between the gate built-in block 70 and the data TCP 40 such as the display area of the liquid crystal display panel 60 DA) on the left side of the non-display area NA. The data TCP 40 may be any one of a plurality of data TCPs of the embodiment. For example, the data TCP 40 may be the first data TCP among a plurality of data TCPs.

The level shifter 90 may include a plurality of transistors. The circuit configuration of the level shifter 90 composed of a plurality of transistors can be variously implemented. Therefore, the embodiment is not limited to the specific circuit configuration of the level shifter 90 and may be any circuit configuration having the same structure as the thin film transistor of each pixel P of the liquid crystal display panel 60, May also be included. The circuit structure of the level shifter 90 in the embodiment may be formed by a different semiconductor process having a different structure from the thin film transistor of each pixel P of the liquid crystal display panel 60. [

Therefore, the level shifter 90 can be formed directly on the liquid crystal display panel 60 by a semiconductor process, not by an IC (Integrated Circuit).

The level shifter 90 of the third embodiment differs from that of the liquid crystal display panel 60 in that the level shifter film including the level shifter IC is connected to one side of the liquid crystal display panel as in the first and second embodiments, Can be formed directly on the non-display area NA. Therefore, in the third embodiment, the level shifter 90 can be mounted on the non-display area NA of the liquid crystal display panel 60 without having to attach the level shifter film to one side of the liquid crystal display panel as in the first and second embodiments, The manufacturing process can be simplified and structurally simplified.

First line on glass (LOG) signal lines are formed in the non-display area NA of the liquid crystal display panel 60 between the level shifter 90 and the data TCP 40, And second line on glass (LOG) signal lines may be formed in the non-display area NA of the liquid crystal display panel 60 between the gate built-in block 70 and the gate built-

The gate driving control signal GDC outputted from the timing controller 12 of the main PCB 10 is transmitted to the liquid crystal display panel 60 via the connecting member 20, the data PCB 30 and the data TCP 40, May be input to the level shifter 90 through the first line on glass (LOG) signal lines formed in the non-display area NA of the display panel.

The gate driving control signal GDC may include a start signal VSTin, a rising time control signal GCLK, a polling time control signal MCLK, and a deterioration prevention signal E / O. Accordingly, the first line on glass (LOG) signal lines may have at least five lines to accommodate the gate driving control signal GDC.

The level shifter 90 may generate a gate driving control voltage based on the gate driving control signal GDC. The gate driving control voltage may include a gate start voltage GVST, a plurality of gate clock voltages CLK1 to CLK8, a deterioration prevention voltage Vdd_e / o, and a reset voltage RESET. Thus, the second line on glass (LOG) signal lines may have at least twelve lines to accommodate the gate driving control voltage.

The gate driving control voltage output from the level shifter 90 may be input to the gate built-in block 70 formed as close as possible to the level shifter 90.

The gate driving control voltage of the level shifter 90 may be supplied to the plurality of shift registers 72-1 to 72-n of the gate built-in block 70 in common.

Each of the shift registers 72-1 to 72-n outputs one of the clock voltages CLK1 to CLK2 of the gate driving control voltage as a gate high voltage to the corresponding gate line GL1 to GLn Can be output. In addition, the gate high voltage may be input to the next shift register to initiate operation of the next shift register.

The operation of the first shift register 72-1 can be started by the gate start voltage GVST of the gate driving control voltage.

All the shift registers 72-1 to 72-n of the gate built-in block 70 can be initialized by the reset voltage RESET of the gate driving control voltage.

A pair of transistors of the output buffers of the shift registers 72-1 to 72-n may alternately be used for each frame by the deterioration preventing voltage Vdd_e / o of the gate driving control voltage.

For example, each shift register 72-1 ... 72-n may have an output buffer comprising a pair of transistors. For example, the pair of transistors may be a pull-up transistor and a pull-down transistor.

For example, a pull-up transistor may be used during an odd frame and a pull-down transistor may not be used at this time. For example, a full-down transistor may be used during an even frame and a full-down transistor may not be used at this time. This is an example, and the embodiment is not limited thereto. For example, the pull-up transistor and the pull-down transistor can be used alternately at regular intervals. The period may be one frame, two frames, ten frames, and so on. Therefore, the pull-up transistor or the pull-down transistor is not used for a predetermined time, and the transistor is prevented from being deteriorated.

The level shifter 90 is not formed on the main PCB so that the signal lines corresponding to the output signal of the level shifter, i.e., the number of gate driving control voltages (at least 12), are connected to the main PCB, the connecting member, Data TCP need not be formed. The sizes of the main PCB 10, the connecting member 20, the data PCB 30 and the data TCP 40 can be minimized and the number of signal lines corresponding to the number of gate driving control voltages (at least 12) It is possible to maximize the design margin of the main PCB 10, the connecting member 20, the data PCB 30, and the data TCP 40 since other electronic components can be mounted on the occupied area.

5 is a block diagram showing a liquid crystal display device according to a fourth embodiment of the present invention.

The fourth embodiment is substantially the same as the third embodiment except that another level shifter 94 and another gate built-in block 80 are added.

Therefore, in the fourth embodiment, the same reference numerals are given to the same constituent elements as those in the third embodiment, and a detailed description thereof will be omitted.

5, the first gate built-in block 70 is formed on the first side of the display area DA of the liquid crystal display panel 60, for example, the non-display area NA on the left side of the display area DA The second gate built-in block 80 may be formed on the second side of the display area DA of the liquid crystal display panel 60, for example, the non-display area NA on the right side of the display area DA.

The first gate built-in block 70 includes a plurality of shift registers 72-1 to 72-n, and the second gate built-in block 80 includes a plurality of shift registers 74-1 to 74-n. ..., 74-n. The shift registers 72-1 ... 72-n of the first gate built-in block 70 and the shift registers 74-1 ... 74-n of the second gate built- May correspond to the gate lines GL1 ... GLn. For example, the first shift register 72-1 of the first gate built-in block 70 and the first shift register 74-1 of the second gate built-in block 80 are electrically connected to the first gate line GL1 Can be connected.

The first level shifter 92 is formed in the non-display area NA of the liquid crystal display panel 60 between the first gate built-in block 70 and the first data TCP 40, The second level shifter 94 may be formed in the non-display area NA of the liquid crystal display panel 60 between the first data line 80 and the last data TCP 40. [

The first level shifter 92 and the second level shifter 94 may include a plurality of transistors, respectively. The transistors may be formed by a semiconductor process together with a thin film transistor of each pixel P of the liquid crystal display panel 60.

First line on glass (LOG) signal lines are formed in the non-display area NA of the liquid crystal display panel 60 between the first level shifter 92 and the first data TCP 40, Second line on glass (LOG) signal lines may be formed in the non-display area NA of the liquid crystal display panel 60 between the one level shifter 92 and the first gate built-in block 70.

Third line on glass (LOG) signal lines are formed in the non-display area NA of the liquid crystal display panel 60 between the second level shifter 94 and the last data TCP 40, Fourth line on glass (LOG) signal lines may be formed in the non-display area NA of the liquid crystal display panel 60 between the level shifter 94 and the second gate built-

The first and second gate driving control signals GDC and the data driving control signal DDC may be generated from the timing controller 14. [

The first and second gate driving control signals GDC may be supplied to the first and second level shifters 92 and 94 at the same time. That is, the first gate driving control signal GDC of the timing controller 14 is transmitted to the liquid crystal display panel 60 via the connecting member 20, the data PCB 30 and the first data TCP 40. [ (LOG) signal lines formed in the non-display area NA of the first level shifter 92. The first level shifter 92 is connected to the first line-on-glass (LOG) signal lines. At the same time, the second gate driving control signal GDC of the timing controller 14 is transmitted to the liquid crystal display panel 60 via the connecting member 20, the data PCB 30 and the last data TCP 40 And may be supplied to the second level shifter 94 through third line on glass (LOG) signal lines formed in the non-display area NA.

The first level shifter 92 generates a first gate driving control voltage based on the first gate driving control signal GDC and the second level shifter 94 generates the second gate driving control signal GDC The second gate driving control voltage can be generated. The first and second gate driving control signals may be the same signals.

The first and second gate driving control signals GDC may include a start signal VSTin, a rising time control signal GCLK, a polling time control signal MCLK and an anti-degradation signal E / O .

The first and second gate driving control voltages may include a gate start voltage GVST, a plurality of clock voltages CLK1 to CLK8, a deterioration prevention voltage Vdd_e / o, and a reset voltage RESET.

The first gate driving control voltage of the first level shifter 92 may be supplied to the first gate built-in block 70 via the second line on glass (LOG) signal lines. At the same time, the second gate driving control voltage of the second level shifter 94 may be supplied to the second gate built-in block 80 via the fourth line on glass (LOG) signal lines.

The first and second gate driving control voltages are applied to all of the shift registers 72-1 to 72-n, 74-1 to 74-n of the first and second gate built-in blocks 70 and 80, n. < / RTI >

The shift registers of the first and second gate built-in blocks 70 and 80 disposed on both sides of the gate lines GL1 to GLn arranged in the display area DA of the liquid crystal display panel 60 72-1 ... 72-n, 74-1 ... 74-n may sequentially output the output signals. The output signal may be a gate high voltage having a high level pulse of 27V.

For example, the gate high voltage of the first shift register 72-1 of the first gate built-in block 70 and the gate high voltage of the second shift register 74-1 of the second gate built- And may be simultaneously supplied to both sides of the gate line GL1.

If the shift registers of the gate built-in block are disposed only on one side of the gate line (third embodiment), a gate high voltage is supplied to one side of the gate line, and the gate high voltage flows to the other side of the gate line through the gate line Goes. In the case of a large-sized liquid crystal display panel, the length of the gate line becomes long. In this case, a gate high voltage flowing to the other side of the gate line causes a signal delay due to a resistance component and a capacitance component of the gate line, The gate high voltage in the vicinity causes a delay in the rising time interval and the polling time interval. Such a signal delay causes a malfunction.

However, when the gate high voltage is simultaneously supplied from both sides of the gate lines GL1 to GLn as in the fourth embodiment, even if the gate lines GL1 to GLn are long, Is hardly generated. Therefore, the fourth embodiment can prevent a malfunction due to a signal delay and improve image quality.

The thin film transistors electrically connected to the gate lines GL1 ... GLn are turned on by the gate high voltage supplied to the gate lines GL1 ... GLn and the data of the data TCP 40 is turned on by the turn- The data voltages supplied to the data lines in the driver IC 42 may be applied to the pixel electrodes electrically connected to the thin film transistors via the thin film transistors. Accordingly, an electric field is generated by a data voltage applied to the pixel electrode and a common voltage applied to the common electrode facing the pixel electrode, and the liquid crystal is displaced by the electric field to control the transmittance of light, so that information can be displayed.

10: Main PCB
12, 14: Timing controller
20:
30: Data PCB
40: Data TCP
42: Data Driver IC
50, 54, 57: level shifter film
52, 56, 58: Level shifter IC
60: liquid crystal display panel
70, 80: Gate built-in block
72-1 ... 72-n, 74-1 ... 74-n:
90, 92, 94: level shifter
GL0 ... GLn: gate line
DL1 ... DLm: data line
DA: Display area
NA: non-display area

Claims (15)

A PCB including a timing controller for generating a gate driving control signal;
A display panel electrically connected to the PCB and including a display area and a non-display area surrounding the display area;
A gate built-in block formed in the non-display area; And
Level shifter IC generates a gate driving control voltage including a gate start voltage and a plurality of gate clock voltages based on the gate driving control signal, and supplies the gate driving control voltage to the gate built- To a level shifter,
And the level shifter is electrically connected to one side of the display panel. A PCB including a timing controller for generating a gate driving control signal;
A display panel electrically connected to the PCB and including a display area and a non-display area surrounding the display area;
A gate built-in block formed in the non-display area; And
And a level shifter for generating a gate driving control voltage based on the gate driving control signal and supplying the gate driving control voltage to the gate built-in block,
Wherein the level shifter is formed adjacent to the gate built-in block in a non-display area on one side of the display area. 3. The method according to claim 1 or 2,
Wherein the gate built-in block comprises a plurality of shift registers,
Wherein each shift register includes a plurality of transistors. The method of claim 3,
Wherein the transistors have the same structure as the thin film transistors in the display region. 3. The method of claim 2,
Wherein the level shifter includes a plurality of transistors. 6. The method of claim 5,
Wherein the transistors have the same structure as the thin film transistors in the display region. delete delete 3. The method according to claim 1 or 2,
Further comprising a plurality of data TCPs electrically connected between the PCB and the display panel,
And the data TCP includes a data driver IC. 10. The method of claim 9,
A plurality of first signal lines in a non-display area of the display panel between the data TCP and the level shifter; And
And a plurality of second signal lines in a non-display area of the display panel between the level shifter and the gate built-in block. 3. The method according to claim 1 or 2,
Wherein the gate driving control voltage includes a gate start voltage, a plurality of clock voltages, a deterioration prevention voltage, and a reset voltage. A PCB including a timing controller for generating first and second gate driving control signals;
A display panel electrically connected to the PCB and including a display area and a non-display area surrounding the display area;
A first gate built-in block formed in a non-display area on a first side of the display area;
A second gate built-in block formed in a non-display area on a second side of the display area;
Wherein the first level shifter IC generates a first gate driving control voltage including a gate start voltage and a plurality of gate clock voltages based on the first gate driving control signal, A first level shifter for supplying a gate driving control voltage to the first gate built-in block; And
Wherein the second level shifter IC generates a second gate driving control voltage including a gate start voltage and a plurality of gate clock voltages based on the second gate driving control signal, And a second level shifter for supplying a second gate driving control voltage to the second gate built-in block,
And the first and second level shifters are electrically connected to the first and second sides of the display panel. A PCB including a timing controller for generating first and second gate driving control signals;
A display panel electrically connected to the PCB and including a display area and a non-display area surrounding the display area;
A first gate built-in block formed in a non-display area on a first side of the display area;
A second gate built-in block formed in a non-display area on a second side of the display area;
A first level shifter for generating a first gate driving control voltage based on the first gate driving control signal and supplying the first gate driving control voltage to the first gate built-in block; And
And a second level shifter for generating a second gate driving control voltage based on the second gate driving control signal and supplying the second gate driving control voltage to the second gate built-
Wherein each of the first and second level shifters is formed adjacent to the first and second gate built-in blocks in the non-display area of the first and second sides of the display area. 13. The method of claim 12,
Wherein each of the first and second level shifters further includes a level shifter film. 15. The method of claim 14,
And the level shifter films of the first and second level shifts are electrically connected to the first and second sides of the non-display region of the display panel.

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