KR102016568B1 - Display device having narrow bezel and fabricating method thereof - Google Patents

Abstract

The present invention relates to a display device, wherein the vertical lines of the display device include vertical data lines supplied with a data voltage, vertical gate lines supplied with a gate pulse, and vertical common lines supplied with a common voltage. The horizontal lines of the display device may include horizontal gate lines connected to the vertical gate lines to receive the gate pulse through the vertical gate lines. The vertical gate lines and the horizontal gate lines are connected in the bezel area of the display panel.

Description

DISPLAY DEVICE HAVING NARROW BEZEL AND FABRICATING METHOD THEREOF}

The present invention relates to a display device having a narrow bezel and a method of manufacturing the same.

Flat display devices include Liquid Crystal Display Devices (LCDs), Plasma Display Panels (PDPs), Organic Light Emitting Display Devices (OLEDs), Electrophoretic Display Devices: EPD) and the like. The liquid crystal display displays an image by controlling an electric field applied to liquid crystal molecules according to the data voltage. Active matrix type liquid crystal display devices are widely used in almost all display devices, from small mobile devices to large televisions, due to the low price and high performance due to the development of process technology and driving technology.

Manufacturers of flat panel displays have made various attempts to implement narrow bezels. The narrow bezel technology may reduce the bezel in which an image is not displayed at the edge of the display panel, thereby relatively increasing the size of an effective screen on which an image is displayed on the same size display panel. In general, gate drive integrated circuits (ICs) are disposed at left and right edges of the display panel. Accordingly, the left and right edges of the display panel should have a region where the gate drive IC is bonded and a gate link region connecting the gate drive IC and the horizontal gate lines of the pixel array. Due to the structural problem of such a flat panel display device, it is difficult to implement a narrow bezel.

The flat panel display may include a transparent electrode which is commonly connected to pixels of a display screen and formed into a wide film. Indium Tin Oxide (ITO) is the most widely used transparent electrode. A pair of sustain electrodes to which a common voltage Vcom is supplied from a liquid crystal display (LCD) and a pixel electrode, an organic light emitting display (OLED), and a sustain signal are alternately applied to a plasma display panel (PDP). Etc. are formed of a transparent electrode material. The common electrode of the liquid crystal display (LCD) or the sustain electrode pair of the plasma display panel (PDP) are commonly connected to a plurality of pixels, thereby increasing the area thereof.

Since the transparent electrode material has a relatively high resistivity, when the screen of the display panel is enlarged, a voltage drop may occur, which may cause luminance uniformity between pixels. The resistance of the transparent electrode increases as the display panel increases.

As the display panel grows, a method of compensating for high resistivity of the transparent electrode by using a highly conductive metal in contact with the transparent electrode is used. However, most of the highly conductive metals are opaque metals, which lowers the aperture ratio of the pixels. The highly conductive metal may be connected to the transparent electrode every line of the pixel array. As the pixel per inch (PPI) of the display panel increases, the pixel size decreases, and thus the aperture ratio of the pixel is smaller due to the opaque metal contacting the transparent electrode every line of the pixel array.

The present invention provides a display device having a narrow bezel capable of minimizing bezel width and increasing pixel aperture ratio, and a method of manufacturing the same.

The display device of the present invention includes vertical lines and horizontal lines. The vertical lines include vertical data lines supplied with a data voltage, vertical gate lines supplied with a gate pulse, and vertical common lines supplied with a common voltage. The horizontal lines may include horizontal gate lines connected to the vertical gate lines to receive the gate pulse through the vertical gate lines. The vertical gate lines and the horizontal gate lines are connected in the bezel area of the display panel.

The method of manufacturing the display device may include forming horizontal gate lines on a substrate with first metal patterns; Forming a first insulating layer on the substrate, the first insulating layer covering the first metal patterns; Forming vertical data lines on the first insulating layer with second metal patterns; Forming a second insulating layer on the second metal patterns and the first insulating layer; And forming vertical common lines and vertical gate lines on the second insulating layer with third metal patterns.

The present invention can minimize the left and right bezel of the display panel by connecting the vertical gate line and the horizontal gate line and forming the display panel driving circuit in the upper or lower bezel of the display panel. Furthermore, the present invention forms a horizontal common line at the boundary between the display lines disposed in the center of the display panel and removes the horizontal gate line from the boundary. As a result, the present invention can increase the pixel aperture ratio of the display panel.

1 is a diagram illustrating a display device according to an exemplary embodiment of the present invention.
2 is a diagram illustrating a first embodiment of a display panel driving circuit.
FIG. 3 is an enlarged view of the COF shown in FIG. 2.
4 is a diagram illustrating a second embodiment of a display panel driver circuit.
FIG. 5 is an equivalent circuit diagram showing a portion of the pixel array shown in FIG. 1.
6 is a waveform diagram illustrating an example of a data voltage and a gate pulse applied to the pixel array of FIG. 5.
7 is a plan view showing a third metal pattern in the pixel array.
FIG. 8 is a plan view illustrating in detail the first pixel area P1 of FIG. 7.
FIG. 9 is a cross-sectional view illustrating a cross-sectional structure of the gate contact portion taken along the line "I-I '" in FIG. 8.
FIG. 10 is a cross-sectional view illustrating a cross-sectional structure of the gate contact portion taken along the line “II-II ′” in FIG. 8.
11 is a cross-sectional view showing the structure of a TFT of a gate pad, a data pad, a gate contact portion, and a pixel.
FIG. 12 is a plan view illustrating the second pixel area P2 in FIG. 7 in detail.
FIG. 13 is a plan view illustrating the third pixel area P3 in FIG. 7 in detail.
FIG. 14 is a cross-sectional view illustrating a cross-sectional structure of a central portion of a display panel in which horizontal common lines are formed by cutting along the line "III-III '" in FIG.
15A to 15G are cross-sectional views illustrating a method of manufacturing a TFT array substrate in a display device according to an exemplary embodiment of the present invention.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings. Like numbers refer to like elements throughout. In the following description, when it is determined that a detailed description of known functions or configurations related to the present invention may unnecessarily obscure the subject matter of the present invention, the detailed description thereof will be omitted.

The names of the components used in the following description are selected in consideration of the ease of preparation of the specification, and may be different from the names of the actual products.

The display device of the present invention may be manufactured based on a flat panel display device such as a liquid crystal display (LCD), a plasma display panel (PDP), an organic light emitting display (OLED), an electrophoretic display (EPD), and the like. Hereinafter, an example of the display device will be described based on the liquid crystal display device, but is not limited thereto. For example, the display device of the present invention may be made of any flat panel display device in which a data voltage and a gate voltage (or scan voltage) are applied to the pixels.

1 to 4, the display device of the present invention includes a display panel PNL, a display panel driving circuit 10, a timing controller (TCON) 12, and the like.

The display panel PNL may be implemented in a liquid crystal mode having any known structure such as twisted nematic (TN) mode, vertical alignment (VA) mode, in plane switching (IPS) mode, and fret field switching (FFS).

The display panel PNL includes an upper substrate and a lower substrate facing each other with the liquid crystal layer interposed therebetween in the liquid crystal display device. In the display panel PNL, image data is displayed on the pixel array PIXR in which pixels are arranged in a matrix form. The pixel array includes a thin film transistor (TFT) array formed on the lower substrate and a color filter array formed on the upper substrate. The bezel BZ outside the pixel array PIXR is a non-display area.

The TFT array includes vertical lines and horizontal lines. The vertical lines are formed along the vertical direction (y-axis direction) of the display panel PNL. The horizontal lines are formed along the horizontal direction (x-axis direction) of the display panel PNL to be perpendicular to the vertical lines. The vertical lines and the horizontal lines may be formed of an opaque metal having high conductivity. The vertical lines include vertical data lines VD, vertical gate lines VG, and vertical common lines VC. Data voltages are supplied to the vertical data lines VD, and gate pulses synchronized with the data voltages are supplied to the vertical gate lines VG. The common voltage Vcom is supplied to the vertical common lines VC from a power supply circuit (not shown).

The horizontal lines include horizontal gate lines HG that receive gate pulses through the vertical gate lines VG. The horizontal lines may further include a horizontal common line HC as shown in FIG. 7. The horizontal gate lines HG are connected to the vertical gate lines VG to receive gate pulses through the vertical gate lines VG. The horizontal gate lines HG may be connected to the vertical gate lines VG at the bezel BZ on the left or right side of the display panel PNL as shown in FIG. 2.

The common voltage Vcom is supplied to the horizontal common line HC from a power supply circuit (not shown). The horizontal common line HC may not be formed at every line of the display panel PNL, but may be formed to cross horizontally between pixels in a central horizontal line of the display panel PNL.

Gate electrodes and the like of the TFTs connected to the vertical gate lines VG and the horizontal gate lines HG are formed on the substrate in first metal patterns. The vertical data lines VD, the source electrode of the TFT, and the drain electrode of the TFT are formed on the substrate in second metal patterns. Vertical common lines VC, vertical gate lines VG, and horizontal common line HC are formed on the substrate in third metal patterns. The first insulating layer is formed between the first metal pattern and the second metal pattern. A second insulating layer is formed between the second metal pattern and the third metal pattern.

In the TFT array, TFTs are formed at the intersections of the vertical data lines VD and the horizontal gate lines HG. The TFT supplies the data voltage from the vertical data line VD to the pixel electrode 1 of the liquid crystal cell Clc in response to the gate pulse from the horizontal gate line HG. Each of the liquid crystal cells Clc is driven by the voltage difference between the pixel electrode 1 charging the data voltage through the TFT and the common electrode 2 to which the common voltage Vcom is applied. The common voltage Vcom is applied to the common electrode 2 of all the pixels through the vertical common lines VC. The common electrode 2 of the pixels is connected to the vertical common lines VC. In addition, the common electrode 2 of the pixels may be connected to the horizontal common line HC to receive the common voltage Vcom through the horizontal common line HC. The common electrode 2 and the pixel electrode 1 are formed of a transparent electrode such as ITO. The storage capacitor Cst is connected to the pixel electrode 1 of the liquid crystal cell Clc to maintain the voltage of the liquid crystal cell Clc for one frame period. The color filter array includes a color filter and a black matrix. Polarizing plates are attached to each of the upper and lower glass substrates of the display panel PNL, and an alignment layer for setting the pre-tilt angle of the liquid crystal is formed.

The display panel driver circuit 10 includes a source drive IC (SIC) for outputting a data voltage and a gate drive IC (GIC) for outputting a gate pulse.

The display panel driver circuit 10 includes a source drive IC (SIC) and a gate drive IC (GIC). The source drive IC (SIC) and the gate drive IC (GIC) may be mounted together on a flexible circuit board such as a chip on film (COF) as shown in FIG. 3. The input terminal of the COF is bonded to a printed circuit board (PCB), and the output terminal of the COF is bonded to a TFT array substrate of the display panel PNL. In the COF, an insulating layer is provided between the wires connected to the source drive IC (SIC) (FIG. 3, dotted line) and the wires connected to the gate drive IC (GIC) (FIG. 3, solid line) so as to be electrically separated. Is formed. The source drive IC SIC and the gate drive IC GIC may be separately disposed on the upper bezel and the lower bezel of the display panel PNL as shown in FIG. 4. The source drive IC (SIC) and the gate drive IC (GIC) may be directly bonded on the substrate of the display panel PNL by a chip on glass (COG) process. In this case, the source drive IC SIC may be bonded to the substrate in the lower bezel area disposed outside the lower side of the pixel array area PIXR as shown in FIG. 4. The gate drive IC GIC may be bonded to the substrate in an upper bezel area disposed outside the pixel array area PIXR.

The source drive IC (SIC) samples the digital video data of the input image under the control of the timing controller 12 and then latches and converts the digital video data into data of a parallel data system. The source drive IC (SIC) generates a data voltage by converting the digital video data into an analog gamma compensation voltage using a digital to analog converter (ADC) under the control of the timing controller 12. Supply to vertical data lines VD. The gate drive IC GIC sequentially supplies a gate pulse (or scan pulse) synchronized with the data voltage from the first vertical gate line to the nth vertical gate line under the control of the timing controller 12.

The source drive IC SIC and the gate drive IC GIC are disposed above or below the display panel PNL. For this reason, the gate drive IC GIC does not need to be bonded or embedded in the left and right bezel regions of the display panel PNL, and the gate link line connects the horizontal gate lines HG and the gate drive IC GIC. There is no need. Therefore, the widths of the display panel PNL of the present invention are reduced by removing the junction region and the gate link region of the gate drive IC GIC from the left and right bezels BZ.

Gate contact portions GC that connect the vertical gate lines and the horizontal gate lines are formed on the left bezel BS or the right bezel BZ of the display panel PNL of the present invention. Although the left and right bezels BZ of the display panel PNL include the gate contact parts GC, their widths are 1.5 mm or less and are equal to or greater than the horizontal length of the gate contact part. Accordingly, the present invention can minimize the left bezel BZ and the right bezel BZ of the display panel.

The timing controller 12 transmits digital video data of the input image received from the host system 14 to the source drive ICs SIC. The timing controller 12 receives timing signals such as a vertical synchronization signal Vsync, a horizontal synchronization signal Hsync, a data enable signal Data Enable, DE, and a main clock CLK from the host system 14. These timing signals are synchronized with the digital video data of the input image. The timing controller 12 uses the timing signals Vsync, Hsync, DE, and CLK to control the operation timing of the source drive ICs SIC and the operation timing of the gate drive ICs GIC. A gate timing control signal for controlling the signal is generated.

The host system 14 may be implemented as one of a television system, a set top box, a navigation system, a DVD player, a Blu-ray player, a personal computer (PC), a home theater system, and a phone system. have. The host system 14 converts the digital video data RGB of the input image into a format suitable for the display panel PNL. The host system 14 transmits the timing signals Vsync, Hsync, DE, and MCLK together with the digital video data of the input image to the timing controller 12.

The pixel array may be implemented in various structures. For example, the pixel array may be implemented as shown in FIG. 5.

Referring to FIG. 5, the pixels may include an R (red) sub pixel, a G (green) sub pixel, and a B (blue) sub pixel.

The pixels arranged on the odd horizontal lines include the TFT T1 disposed between the left vertical data lines VD1 to VD5 and the horizontal gate lines HG1 to HG4, and the pixel electrode PIX1 connected to the TFT T1. It includes. The pixels arranged on the even-numbered horizontal line include the TFT T2 disposed between the right vertical data lines VD2 to VD6 and the horizontal gate lines HG1 to HG4, and the pixel electrode PIX2 connected to the TFT T2. It includes.

The vertical gate lines VG1 to VG3 are connected to the horizontal gate lines HG1 to HG3 through gate contact portions GC formed in the left or right bezel BZ of the display panel PNL. The vertical gate lines VG1 to VG3 are patterned in an L shape along the vertical data lines VD2, VD4 and VD5 and the horizontal gate lines HG1 to HG3 to form horizontal gate lines through the gate contact parts GC. 1 to 1 (HG1 to HG3). For example, the first vertical gate lines VG1 are patterned in an L shape bent along the second vertical data line VD2 and the first horizontal gate line HG1 to form a gate contact portion GC in the bezel BZ. ) Is connected to the first horizontal gate line HG1. The second vertical gate lines VG2 are patterned in an L shape that is bent along the fourth vertical data line VD4 and the second horizontal gate line HG2 to be formed through the gate contact portion GC in the bezel BZ. 2 is connected to the horizontal gate line HG2. The third vertical gate line VG3 is patterned in an L shape bent along the sixth data line D4 and the third horizontal gate line HG3 to form a third horizontal gate line through the gate contact portion GC in the bezel BZ. It is connected to the gate line HG1. The gate pulse is sequentially applied to the vertical gate lines VG1 to VG3 in the order of the first vertical gate line VG1, the second vertical gate line VG2, and the third vertical gate line VG3.

The present invention overlaps the vertical gate lines VG1 to VG3 and the vertical common lines VC with the vertical data lines VD1 to VD6 and the horizontal gate lines HG1 to HG4 with an insulating layer therebetween. As a result, the aperture ratio of the pixels does not decrease due to the vertical gate lines VG1 to VG3 and the vertical common lines VC. The vertical common lines VC, the common electrode, the storage capacitor, and the like are omitted in FIG. 5.

The vertical gate lines VG1 to VG3 and the vertical common lines VC should not be short circuited with the vertical data lines VD1 to VD6 and the horizontal gate lines HG1 to HG4. To this end, the vertical gate lines VG1 to VG3 and the vertical common lines VC are formed in a separate metal pattern separated from the vertical data lines VD1 to VD6 and the horizontal gate lines HG1 to HG4. Can be. For example, the horizontal gate lines HG1 to HG4 are formed in the first metal pattern. The vertical data lines VD1 to VD6 are formed in a second metal pattern separated from the first metal pattern with the first insulating layer interposed therebetween. The vertical gate lines VG1 to VG3 and the vertical common lines VC are formed of a third metal pattern separated from the second metal pattern with the second insulating layer interposed therebetween.

The pixel array having the structure as shown in FIG. 5 allows the data voltages having the same polarity to be output to the vertical data lines VD for one frame period, thereby reducing power consumption and heat generation of the source drive IC SIC and improving dot inversion in the pixel array. The picture quality can be improved. For example, the positive data voltage is supplied to the odd vertical data lines VD1 and VD3 as shown in FIG. 6 during the Nth (N is positive integer) frame period, and the negative data voltage is supplied during the Nth frame period. It is supplied to even-numbered vertical data lines VD2 and VD4. In the pixel array structure of FIG. 5, data voltages of different polarities are charged to upper and lower neighboring pixels, and data voltages of different polarities are charged to neighboring pixels from side to side. Therefore, the source drive IC (SIC) is driven in the form of column inversion which outputs the data voltage of the same polarity for one frame period, and the pixel array charges the data voltage whose polarity is reversed by the dot inversion.

7 is a plan view showing a third metal pattern in the pixel array.

Referring to FIG. 7, a gate pulse is supplied to the vertical gate lines VG, while a common voltage Vcom, which is a DC voltage, is supplied to the vertical common lines VC. The vertical gate lines VG and the vertical common lines VC are separated from the same metal layer. In other words, the third metal pattern is divided into vertical gate lines VG and vertical common lines VC. Vertical common lines VC may be disposed between the vertical gate lines VG. Vertical common lines VC may be disposed in the central portion of the pixel array region without vertical gate lines VG.

The vertical common lines VC may be connected to the horizontal common line HC crossing the central portion of the display panel PNL. The common voltage Vcom may be applied to the vertical common lines VC and the horizontal common line HC in the up, down, left, and right directions of the display panel PNL. The vertical common lines VC and the horizontal common line HC are connected to the common electrode 2 to supply the common voltage Vcom to the common electrode 2.

FIG. 8 is a plan view illustrating in detail a first pixel area P1 positioned at an upper left edge of the display panel PNL in FIG. 7. FIG. 9 is a cross-sectional view illustrating the cross-sectional structure of the gate contact portion VG taken along the line "I-I '" in FIG. 8. FIG. 10 is a cross-sectional view illustrating the cross-sectional structure of the gate contact portion VG taken along the line “II-II ′” in FIG. 8. FIG. 11 is a cross-sectional view illustrating the structure of a gate pad GP, a data pad DP, a gate contact part GC, and a TFT of a pixel. 8 to 11 illustrate an example of the structure of the LCD panel in the FFS mode. In FIG. 8, VC1 to VC4 are vertical common lines.

8 and 9, the gate contact parts GC may include a horizontal gate electrode contact part HGP and a vertical gate electrode contact part VGP connected to the first transparent electrode pattern ITO1. The horizontal gate electrode contact portion HGP is formed of a first metal in the left or right bezel BZ of the display panel PNL and is connected 1: 1 to the horizontal gate electrodes HG1 to HG4. The vertical gate electrode contact portion VGP is formed of a third metal in the left or right bezel BZ of the display panel PNL, and is connected 1: 1 to the vertical gate electrodes VG1 to VG4.

As shown in FIG. 9, a first metal pattern is formed on the substrate SUBS, and the gate insulating layer GI, the first passivation layer Pas1, the organic protective layer PAC, the third metal pattern are sequentially formed thereon. The second and third passivation layers Pas2 and Pas3 and the first transparent electrode pattern ITO1 are stacked. The horizontal gate electrode contact portion HGP is formed in the first metal pattern, and the vertical gate electrode contact portion VGP is formed in the third metal pattern. Therefore, an insulating material such as a gate insulating film GI, a first passivation layer Pas1, and an organic protective layer PAC exists between the horizontal gate electrode contact portion HGP and the vertical gate electrode contact portion VGP.

The first transparent electrode pattern pattern ITO1 is in contact with the vertical gate electrode contact portion VGP through the first contact hole C1 passing through the second and third passivation layers Pas1, and includes a gate insulating layer GI, The horizontal gate electrode contact portion HGP is contacted through the second contact hole C1 passing through the first passivation layer Pas1 and the organic passivation layer PAC. Therefore, the vertical gate electrode contact portion VGP and the horizontal gate electrode contact portion HGP are connected to the first transparent electrode pattern ITO1 through the contact holes C1 and C2.

8 and 10, a TFT includes a gate electrode GE, a gate insulating film GI covering a gate electrode GE, an active layer ACT and an active layer ACT formed on the gate insulating film GI. And a source electrode SE and a drain electrode DE formed thereon. The active layer ACT is formed of a semiconductor. The first passivation layer Pas1 and the organic passivation film PAC cover the TFTs. Second and third passivation layers Pas2 and Pas3 are stacked on the organic passivation layer PAC. The source electrode SE is connected to the pixel electrode ITO (PXL) formed on the third passivation layer Pas3 through the third contact hole C3. The third contact hole C3 passes through the first passivation layer Pas1, the organic passivation layer PAC, and the second and third passivation layers Pas2 and Pas3 to expose the source electrode SE of the TFT. The drain electrode DE is connected to the vertical data lines VD1 to VD8.

The gate electrode GE is formed of a first metal. The source electrode SE and the drain electrode DE are formed of a second metal. The pixel electrode ITO (PXL) and the common electrode ITO (com) are formed of a transparent electrode. The common electrode ITO (com) is formed between the second passivation layer Pas2 and the third passivation layer Pas3. The liquid crystal molecules are driven by an electric field applied between the pixel electrode ITO (PXL) and the common electrode ITO (com).

The gate drive IC GIC supplies gate pulses to the vertical gate lines VG1 to VG4 through the gate pad GP. The gate pad GP is formed in the upper or lower bezel of the display panel PNL and is connected 1: 1 to the vertical gate lines VG1 to VG4. The source drive IC SIC supplies a data voltage to the vertical data lines VD1 to VD8 through the data pad DP. The data pad DP is connected 1: 1 to the vertical data lines VD1 to VD8.

As described above, the vertical gate lines VG1 to VG4 and the vertical common lines VC1 to VC8 are formed in a third metal pattern. In contrast, the vertical data lines VD1 to VD8 are formed in the second metal pattern. Insulation layers Pas1 and PAC are present between the second metal pattern and the third metal pattern.

The gate pad GP and the data pad DP have the same structure as shown in FIG. 11. The gate pad GP and the data pad DP are connected to the pad electrode GM through the pad electrode GM and the fourth contact hole C4 formed on the substrate SUBS, and the second transparent electrode pattern ITO2. It includes. The fourth contact hole C4 penetrates through insulating layers such as the gate insulating layer GI, the first passivation layer Pas1, the organic passivation layer PAC, and the second and third passivation layers Pas2 and Pas3. GM). The pad electrode GM of the gate pad GP is connected 1: 1 to the vertical gate lines VG1 to VG4 formed of the third metal pattern through a gate link pattern (not shown). The first metal pattern GM1 of the data pad DP is connected 1: 1 to the vertical data lines VD1 to VD8 formed of the second metal pattern through a data link pattern (not shown).

9 to 11, the first to third metals may be formed of opaque metals having high conductivity. The transparent electrode patterns ITO1, ITO2, ITO (Vcom), and ITO (PXL) may be formed of ITO.

FIG. 12 is a plan view illustrating the second pixel area P2 in FIG. 7 in detail. FIG. 13 is a plan view illustrating the third pixel area P3 in FIG. 7 in detail. FIG. 14 is a cross-sectional view of the horizontal common line taken along the line "III-III '" in FIG. 12.

12 and 13, vertical gate lines VGn−1 to VGn + 2 and vertical common lines VCn−1 in the second pixel area P2 formed on the left or right side of the display panel PNL. VCn + 2) is crossed. Vertical common lines VCn-1 to VCn + 2 are disposed in the third pixel area P3 formed at the center of the display panel PNL without the vertical gate lines VGn−1 to VGn + 2. The vertical gate lines VGn-1 to VGn + 2 and the vertical common lines VCn-1 to VCn + 2 are formed in a third metal pattern and separated as described above.

A horizontal common line HC is formed on a line that horizontally crosses the center of the display panel PNL. When the nth (n is a positive integer of 2 or more) display line and the n + 1th display line are formed in the center of the display panel PNL, the horizontal common line HC is the nth display line and the n + 1th line. It is formed along the horizontal direction x at the boundary between the display lines. The horizontal gate line is not formed at the boundary between the pixels on which the horizontal common line HC is formed. The pixels disposed in the upper half of the display panel PNL and the pixels disposed in the lower half of the display panel PNL may be formed in a vertically symmetrical structure. In this case, the gate pulse from the upper horizontal gate line is applied to the pixel disposed in the upper half. On the other hand, the gate pulse from the lower horizontal gate line is applied to the pixel disposed in the lower half. For example, the nth pixel PIXn disposed on the nth display line charges the data voltage in response to a gate pulse from the nth horizontal gate line HGn disposed above the pixel PIXn. The n-th horizontal gate line HGn is formed at a boundary between the n-th pixel PIXn-1 and the n-th pixel PIXn. An n + 1th pixel PIXn + 1 disposed on an n + 1th display line responds to a gate pulse from an n + 1th horizontal gate line HGn + 1 disposed below the pixel PIXn + 1 To charge the data voltage. The n + 1th horizontal gate line HGn + 1 is formed at a boundary between the n + 1th pixel PIXn + 1 and the n + 2th pixel PIXn + 2.

The cross-sectional structure of the third pixel region P3 includes vertical data lines VD6 to VD8, a horizontal common line HC, and a common electrode ITO (Vcom) as shown in FIG. 14. There is no horizontal gate line HG in the cross section of the third pixel region P3. The vertical data lines VD6 to VD8 are formed in the second metal pattern. The horizontal common line HC is formed of a third metal pattern disposed on the second metal pattern. An insulating layer including a gate insulating layer GI and a first passivation layer Pas1 is formed between the vertical data lines VD6 to VD8 and the substrate SUBS. The organic passivation film PAC is an insulating layer formed between the vertical data lines VD6 to VD8 and the horizontal common line HC. The second passivation layer Pas2 is formed between the horizontal common line HC and the common electrode ITO (Vcom). The third passivation layer Pas3 covers the common electrode ITO (Vcom).

The horizontal common line HC is connected to the vertical common lines VCn and VCn + 1 as shown in FIGS. 7 and 12. The third transparent electrode pattern ITO3 is in contact with the horizontal common line HC through the fifth contact hole C5 and is in contact with the common electrode ITO (Vcom) through the sixth contact hole C6. The line HC is connected to the common electrode ITO (Vcom). The fifth contact hole C5 passes through the second and third passivation layers Pas2 and Pas3 to expose the horizontal common line HC. The sixth contact hole C6 passes through the third passivation layer Pas3 to expose the common electrode ITO (Vcom).

15A to 15G are cross-sectional views illustrating a method of manufacturing a TFT array substrate in a display device according to an exemplary embodiment of the present invention. 15A to 15G illustrate the TFT array substrate structure of the FFS mode, it should be noted that the display device of the present invention is not limited to the FFS mode because the display device of the present invention can be implemented in any liquid crystal mode as described above.

Referring to FIG. 15A, the present invention performs a first photo mask process to form first metal patterns on a substrate SUBS. The first metal patterns include horizontal gate lines HG, a horizontal gate electrode contact portion HGP connected to the horizontal gate lines HC, a gate electrode GE of a TFT connected to the horizontal gate lines HG, and a data pad. And a pad electrode GM of the gate pad GP and the like. In the first photo mask process, a first metal is deposited on a substrate SUBS, a photolithography process, and a wet etching process of the first metal are patterned. The first metal may be at least one metal of copper (Cu), aluminum (Al), molybdenum (Mo), or a double metal layer of Cu / MoTi. The photolithography process includes applying a photoresist on the first metal and then aligning, exposing and developing the first photo mask thereon. After the first metal is etched, the strip process removes the residual photoresist pattern. Next, the present invention deposits a gate insulating film GI on the substrate. The gate insulating layer GI may be deposited with silicon nitride (SiNx) and cover the first metal patterns.

Referring to FIG. 15B, the present invention performs a second photo mask process. In the second photo mask process, a semiconductor layer and a second metal are successively deposited on the gate insulating layer GI, and a photolithography process is performed. The second metal may be formed of at least one metal of copper (Cu), aluminum (Al), and molybdenum (Mo). The photolithography process includes applying a photoresist on the second metal and then aligning, exposing and developing a second photo mask, which is a halftone mask thereon. In this photolithography process, the exposure amount is partially different due to the halftone mask to form a photoresist pattern having a step difference. In the photolithography process, the second metal patterns are stacked on the active pattern ACT by wet etching the second metal and dry etching the semiconductor layer below the photoresist pattern as a mask. The second metal patterns include the vertical data lines VD, the drain electrode DE of the TFT connected to the vertical data lines VD, the source electrode SE of the TFT, and the like. Subsequently, the second photo mask process ashes the photoresist pattern to expose the semiconductor channel region of the TFT and then dry etches to remove the ohmic contact layer exposed in the semiconductor channel region of the TFT.

Referring to FIG. 15C, in the third photo mask process, silicon nitride (SiNx) is deposited and photo-acryl is applied, followed by a photolithography process. The photolithography process includes a process of aligning, exposing and developing the third photo mask on the photo acrylic. As a result of the third photo mask process, a first passivation layer Pas1 made of silicon nitride (SiNx) and an organic passivation film PAC made of photo acryl are formed. Contact holes are formed on the organic passivation layer PAC to partially expose the first passivation layer Pas1.

Referring to FIG. 15D, a fourth photo mask process may deposit a third metal on an organic passivation layer (PAC) and perform a photolithography process. The third metal may be formed of at least one metal of copper (Cu), aluminum (Al), and molybdenum (Mo). The photolithography process forms a photoresist pattern on the third metal by applying a photoresist on the third metal and then performing a process of aligning, exposing and developing the fourth photo mask thereon. The photolithography process wet-etches the third metal using the photoresist pattern as a mask and then removes the residual photoresist pattern by a strip process. The third metal patterns include vertical gate lines VG, a vertical gate electrode contact portion VGP connected to the vertical gate lines VG, a vertical common line VC, a horizontal common line VC, and the like. Subsequently, in the fourth photo mask process, silicon nitride (SiNx) is deposited to cover the third metal patterns to form a second passivation layer Pas2.

Referring to FIG. 15E, the fifth photo mask process deposits a transparent electrode material such as ITO on the second passivation layer Pas2 and performs a photolithography process. In the photolithography process, after the photoresist is applied on the transparent electrode material layer, a process of aligning, exposing and developing the fifth photo mask is performed thereon to form a photoresist pattern on the second passivation layer Pas2. In the fifth photo mask process, the transparent electrode material layer is wet-etched through the photoresist pattern and a strip process is performed to remove the residual photoresist pattern. As a result, the common electrode ITO (Vcom) is formed as a transparent electrode.

Referring to FIG. 15F, in a sixth photo mask process, a third passivation layer Pas2 is formed by depositing silicon nitride (SiNx) with a common electrode ITO (Vcom) and a second passivation layer Pas2, and a photolithography process. Is carried out. In the photolithography process, after applying the photoresist on the second passivation layer Pas3, the photoresist pattern is formed by aligning, exposing and developing the sixth photo mask thereon. In the sixth photo mask process, the third passivation layer Pas3 is dry-etched through the photoresist pattern and a strip process is performed. As a result, the first and fifth contact holes C1 and C5 exposing a part of the third metal pattern, the second and fourth contact holes C2 and C4 exposing a part of the first metal pattern, and the second Contact holes such as a third contact hole C3 exposing a part of the metal pattern and a sixth contact hole C6 exposing a part of the common electrode ITO (Vcom) are formed.

Referring to FIG. 15G, a seventh photo mask process may deposit a transparent electrode material such as ITO on a third passivation layer Pas3 and perform a photolithography process. In the photolithography process, after the photoresist is applied on the transparent electrode material layer, a photoresist pattern is formed on the third passivation layer Pas3 by aligning, exposing and developing the seventh photo mask thereon. In the seventh photo mask process, the transparent electrode material layer is wet-etched through the photoresist pattern and a strip process is performed to remove the residual photoresist pattern. As a result, transparent electrode patterns ITO (PIX), ITO1, ITO2, and ITO3 are formed in the pixel, the pad units GP and DP, and the horizontal common line HC.

Those skilled in the art will appreciate that various changes and modifications can be made without departing from the spirit of the present invention. Therefore, the present invention should not be limited to the details described in the detailed description but should be defined by the claims.

PNL: Display panel 10: Display panel drive circuit
12: timing controller 14: host system
VD: vertical data line VG: vertical gate line
VC: vertical common line HG: horizontal gate line
HC: horizontal common line

Claims (12)

A display panel in which vertical lines and horizontal lines are formed and including pixels, the display panel comprising:
The vertical lines include vertical data lines supplied with a data voltage, vertical gate lines supplied with a gate pulse, and vertical common lines supplied with a common voltage,
The horizontal lines include horizontal gate lines connected to the vertical gate lines to receive the gate pulse through the vertical gate lines,
The vertical gate lines and the horizontal gate lines are connected to each other through a first transparent electrode pattern connected to the vertical gate lines and the horizontal gate lines in the bezel area of the display panel. Display having a. The method of claim 1,
And the vertical gate lines are formed in a metal pattern having an 'L' shape bent along the vertical data lines and the horizontal gate lines. The method of claim 2,
And the vertical gate lines overlap the vertical data lines and the horizontal gate lines. The method of claim 1,
The horizontal wires,
And a horizontal common line to which the common voltage is supplied. The method of claim 4, wherein
And the horizontal common line is formed between display lines passing through the center of the display panel. The method of claim 5,
And the horizontal common line is connected to the vertical common lines. The method of claim 6,
The horizontal gate lines and a gate electrode of a TFT connected to the horizontal gate lines are formed on a substrate in first metal patterns,
The vertical data lines, the source electrode of the TFT, and the drain electrode of the TFT are formed on a substrate with second metal patterns,
The vertical common lines, the vertical gate lines, and the horizontal common line are formed on a substrate with third metal patterns;
A first insulating layer is formed between the first metal pattern and the second metal pattern,
And a second insulating layer is formed between the second metal pattern and the third metal pattern. The method of claim 7, wherein
The pixel electrode and the common electrode of the pixel are formed of a transparent electrode material,
And the vertical common lines and the horizontal common line are in contact with the common electrode. In the method of manufacturing a display panel in which vertical lines and horizontal lines are formed and include pixels,
Forming horizontal gate lines on the substrate with first metal patterns;
Forming a first insulating layer on the substrate, the first insulating layer covering the first metal patterns;
Forming vertical data lines on the first insulating layer with second metal patterns;
Forming a second insulating layer on the second metal patterns and the first insulating layer; And
Forming vertical common lines and vertical gate lines on the second insulating layer with third metal patterns,
A data voltage is supplied to the vertical data lines,
A gate pulse is supplied to the vertical gate lines,
A common voltage is supplied to the vertical common lines,
The horizontal gate lines receive the gate pulse through the vertical gate lines,
And the vertical gate lines and the horizontal gate lines are connected in a bezel area of the display panel. The method of claim 9,
Forming vertical common lines and vertical gate lines on the substrate with third metal patterns may include:
Forming the third metal patterns simultaneously with the vertical common lines and the vertical gate lines;
And a horizontal common line is formed between the display lines passing through the center of the display panel and connected to the vertical common lines. The method of claim 10,
The pixel electrode and the common electrode of the pixel are formed of a transparent electrode material,
And the vertical common lines and the horizontal common line are in contact with the common electrode. The method of claim 2,
And the vertical common lines overlap the vertical data lines and the horizontal gate lines.

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