CN101750809B - Liquid crystal display panel - Google Patents
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- CN101750809B CN101750809B CN2008100440487A CN200810044048A CN101750809B CN 101750809 B CN101750809 B CN 101750809B CN 2008100440487 A CN2008100440487 A CN 2008100440487A CN 200810044048 A CN200810044048 A CN 200810044048A CN 101750809 B CN101750809 B CN 101750809B
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- 239000004973 liquid crystal related substance Substances 0.000 title claims abstract description 18
- 239000010409 thin film Substances 0.000 claims abstract description 70
- 239000000758 substrate Substances 0.000 claims abstract description 16
- 230000003071 parasitic effect Effects 0.000 abstract 1
- 238000010586 diagram Methods 0.000 description 6
- 238000005516 engineering process Methods 0.000 description 6
- 238000004519 manufacturing process Methods 0.000 description 6
- 238000012986 modification Methods 0.000 description 6
- 230000004048 modification Effects 0.000 description 6
- 238000000034 method Methods 0.000 description 5
- 239000002184 metal Substances 0.000 description 4
- 239000010408 film Substances 0.000 description 2
- 238000000059 patterning Methods 0.000 description 2
- 230000002159 abnormal effect Effects 0.000 description 1
- 238000013459 approach Methods 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 238000010276 construction Methods 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 238000003780 insertion Methods 0.000 description 1
- 230000037431 insertion Effects 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 238000012545 processing Methods 0.000 description 1
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Abstract
The invention relates to a liquid crystal display panel, which comprises an upper substrate, a lower substrate opposite to the upper substrate, and a liquid crystal layer sandwiched between the upper substrate and the lower substrate, wherein a plurality of scan lines and a plurality of data lines are arranged on the lower substrate which are vertical to each other to form a plurality of pixels, and each row of pixels are controlled by at least two scan lines; signals are input to each column of pixels by a data line, and thin film transistors are formed in the pixels; and each thin film transistor comprises a grid, a source and a drain, wherein in each pixel, the parasitic capacitance generated by the overlapping of the grid and the drain of the thin film transistor is same. The liquid crystal display panel can eliminate the phenomenon of uneven screen brightness caused by different jump voltages generated by the thin film transistors in the different pixels.
Description
Technical field
The present invention relates to a kind of display panels, particularly a kind of display quality is good, charging ability display panels well and cheaply.
Background technology
Because advantages such as liquid crystal display panel of thin film transistor (TFT-LCD) has gently, approaches, power consumption is little are widely used in present information equipment such as TV, notebook computer, mobile phone, personal digital assistant.At present, the application of display panels on market is more and more important.
Shown in Figure 1 is the structural representation of existing display panels, as shown in Figure 1, and display panels comprises infrabasal plate 100 and upper substrate 200.Usually be provided with colored filter (not shown) on the upper substrate 200; Be integrated with thin film transistor (TFT) (not shown) on the infrabasal plate 100; Sandwich liquid crystal layer 400 between upper substrate 200 and the infrabasal plate 100, according to the display mode of display panels, liquid crystal layer 400 is made up of the corresponding liquid crystal material.Upper substrate 200 and infrabasal plate 100 side of liquid crystal layer 400 dorsad are pasted with polaroid 300 and following polaroid 300 ' respectively.
Shown in Figure 2 is the structural representation of the infrabasal plate 100 of existing display panels.As shown in Figure 2, many data lines 121 and multi-strip scanning line 111 are set on the infrabasal plate 100, the setting that is perpendicular to one another of many data lines 121 and multi-strip scanning line 111 intersects to form a plurality of pixels.Each pixel comprises thin film transistor (TFT) 130 and pixel electrode 140; Each pixel electrode 140 corresponding thin film transistor (TFT) 130; When sweep trace 111 input scan signals, thin film transistor (TFT) 130 is opened, and shows signal sends pixel electrode 140 to through data line 121.All data lines 121 data-driven integrated circuit (driver IC) 120 outside with being positioned at display panels links to each other; All sweep traces 111 turntable driving integrated circuit (gate IC) 110 outside with being positioned at display panels links to each other.
For reducing the cost of display panels, industry has been developed double grid line display panels, and shown in Figure 3 is the synoptic diagram of the infrabasal plate 500 of existing double grid line display panels.As shown in Figure 3; Multi-strip scanning line 511-1,511-2,511-3,511-4 are set on the infrabasal plate 500 ... And many data lines 521 are set, sweep trace 511-1,511-2,511-3,511-4 ... The setting that is perpendicular to one another with data line 521 intersects to form a plurality of pixel regions; The corresponding one-row pixels of wherein per two sweep traces, and every data lines is connected with two adjacent row pixels.For example, first corresponding sweep trace 511-1 of row pixel and the 511-2, and the thin film transistor (TFT) 530 of odd number of pixels links to each other with sweep trace 511-1, and the thin film transistor (TFT) 530 of even number pixel links to each other with sweep trace 511-2.Multi-strip scanning line 511-1,511-2,511-3,511-4 ... Outside with being positioned at display panels respectively turntable driving integrated circuit (not shown) links to each other, and many outside with the being positioned at display panels respectively data-driven integrated circuits (not shown) of data line 521 link to each other.Because the cost of turntable driving integrated circuit is lower than the cost of data-driven integrated circuit, and the turntable driving integrated circuit can also be integrated on the infrabasal plate 500 with thin film transistor (TFT), so double grid line display panels can reduce cost greatly.
Fig. 4 is a double grid line liquid crystal display panel pixel structure synoptic diagram as shown in Figure 3.As shown in Figure 4, sweep trace 511-3 and sweep trace 511-4 and data line 521 intersect to form two pixel P1 and P2, and promptly data line 521 left sides form pixel P1, and the right side forms pixel P2, and existing pixel P1 with data line 521 left sides is that example describes dot structure.Pixel P1 comprises thin film transistor (TFT) 530 and pixel electrode 540.Thin film transistor (TFT) 530 comprises grid 1, source electrode 2 and drain electrode 3, and wherein grid 1 links to each other with sweep trace 511-3, and source electrode 2 links to each other with data line 521, and drains and 3 pass through via hole 4 and link to each other with pixel electrode 540.When sweep trace 511-3 input scan signal, the grid 1 of thin film transistor (TFT) 530 is opened, and the signal of data line 521 is input to pixel electrode 540 through the source electrode 2 of thin film transistor (TFT) 530 with drain electrode 3.Pixel P2 links to each other with sweep trace 511-4 with the different grids 1 of thin film transistor (TFT) 530 that are of pixel P1, all the other structures are all identical, repeat no more at this.
In thin film transistor (TFT) 530,, can therefore produce a stray capacitance Cgd, and stray capacitance Cgd can produce bigger influence to the leaping voltage △ Vp of pixel because gate metal layer and drain metal layer overlap each other.The computing formula of leaping voltage △ Vp is following:
△Vp＝{Cgd/(Clc+Cst+Cgd)}*Vg
Wherein, Clc is the electric capacity that liquid crystal produces, and Cst is a MM CAP, and Cgd is a stray capacitance, and Vg is a sweep trace voltage.
As shown in Figure 4; The stray capacitance that pixel P1 produces is represented with CgdL1; The stray capacitance that pixel P2 produces representes with CgdR1, under desirable manufacturing condition, among the pixel P1 among the overlapping area of the grid 1 of thin film transistor (TFT) 530 and drain electrode 3 and the pixel P2 grid 1 of thin film transistor (TFT) 530 equate with 3 the overlapping area of draining; Thereby can realize that the pixel P1 of data line 521 both sides and the stray capacitance among the pixel P2 equate, i.e. CgdL1=CgdR1.
Pixel structure of liquid crystal display panel synoptic diagram for actual production under the existing technology shown in Figure 5.In existing processes was produced, grid was made up of the different layers metal with drain electrode, in the different process steps of front and back, forms, yet just has the problem of contraposition deviation in the forming process of different layers structure.Particularly; The formation of grid and drain electrode need use different mask plates that metal level is carried out etching and forms corresponding pattern (pattern); Yet the deviation that all can have the aligning accuracy of certain limit in the common production technology, there is the contraposition deviation in the placement that promptly forms the mask plate of grid with the placement that forms the mask plate that drains.As shown in Figure 5; In existing double grid line display panels; Because the existence of this contraposition deviation, can cause with pixel P1 and pixel P2 that same data lines 521 ' links to each other in, the grid 1 ' of thin film transistor (TFT) 530 ' is different with the overlapping area that drains between 3 '; Be CgdL2 ≠ CgdR2, it is different to make thin film transistor (TFT) among pixel P1 and the pixel P2 produce leaping voltage △ Vp.The leaping voltage of adjacent two unit sub-pixels can be variant, and display frame occurs unusual.
The difference of leaping voltage △ Vp in the neighbor can directly cause abnormal show; And the uneven phenomenon of display frame light and shade of neighbor; Thereby the display quality to display panels causes very big influence; Especially in small-medium size double grid line display panels, this problem is especially serious.
For addressing the above problem, the inventor is devoted to develop a kind of double grid line display panels with good display quality, to remedy the display defect that exists in the existing double grid line display panels.
Summary of the invention
The present invention proposes in order to solve the problems of the technologies described above; Purpose is to provide a kind of display panels; Can when reducing this display panels cost, effectively solve the uneven phenomenon of display frame light and shade reducing data-driven integrated circuit, improve display quality.
Another object of the present invention is to increase pixel aperture ratio, improves the breadth length ratio of thin film transistor (TFT) in the display panels, to guarantee the charging ability of thin film transistor (TFT), to optimize display effect.
To achieve these goals, display panels of the present invention, comprise upper substrate, the infrabasal plate relative with said upper substrate and be sandwiched in said upper substrate and said infrabasal plate between liquid crystal layer; Multi-strip scanning line and many data lines are set on the said infrabasal plate, and said multi-strip scanning line and said many data lines are perpendicular to one another and form a plurality of pixels, and each row pixel controlled by at least two sweep traces, and each row pixel is by a data lines input signal; Form thin film transistor (TFT) in the said pixel, said thin film transistor (TFT) comprises grid, source electrode and drain electrode, and wherein, in each pixel, the stray capacitance that produces owing to the overlapping of the grid of thin film transistor (TFT) and drain electrode is identical.
As preferred version of the present invention, in the thin film transistor (TFT) of each pixel, with respect to said grid, said drain electrode all is positioned at the same side.
As another preferred version of the present invention, in the thin film transistor (TFT) of each pixel, with respect to said grid, said drain electrode all is positioned at the left side.
As another preferred version of the present invention, in the thin film transistor (TFT) of each pixel, with respect to said grid, said drain electrode all is positioned at the right side.
As another preferred version of the present invention, said thin film transistor (TFT) is a U type thin film transistor (TFT).
As a preferred version more of the present invention, adjacent two data lines are electrically connected to each other, and link to each other with drive integrated circult through same lead-in wire.
As another preferred version of the present invention, adjacent two data lines are electrically connected to each other at the upside of the first row pixel of said display panels, and said adjacent two data lines are electrically connected to each other at the downside of last column pixel of said display panels.
As another preferred version of the present invention, said drive integrated circult is integrated with scanning line driving integrated circuit and data line drive integrated circult.
Display panels of the present invention can be avoided owing to the different uneven phenomenons of picture light and shade that cause of the leaping voltage of thin film transistor (TFT) generation in the different pixels; Simultaneously can be through reducing the cost that data-driven integrated circuit reduces display panels greatly; And can promote the display quality of display panels through increasing the breadth length ratio of thin film transistor (TFT).
Description of drawings
Shown in Figure 1 is the structural representation of existing display panels.
Shown in Figure 2 is the structural representation of the infrabasal plate 100 of existing display panels.
Shown in Figure 3 is the synoptic diagram of the infrabasal plate 500 of existing double grid line display panels.
Fig. 4 is a double grid line liquid crystal display panel pixel structure synoptic diagram as shown in Figure 3.
Pixel structure of liquid crystal display panel synoptic diagram for actual production under the existing technology shown in Figure 5.
Shown in Figure 6 is structural representation according to the infrabasal plate 600 of the double grid line display panels of embodiment of the present invention.
Fig. 7 is the structural representation of adjacent two pixels of the infrabasal plate 600 of double grid line display panels shown in Figure 6.
Embodiment
Specify embodiment of the present invention with reference to the accompanying drawings.
Shown in Figure 6 is structural representation according to the infrabasal plate 600 of the double grid line display panels of embodiment of the present invention.As shown in Figure 6; Display panels 600 comprises multi-strip scanning line 611-1,611-2,611-3,611-4 ... And multi-group data line 621-1 and 621-2, multi-strip scanning line and multi-group data line intersect to form a plurality of pixels, corresponding two sweep traces of every capable pixel.Multi-strip scanning line 611-1,611-2,611-3,611-4 ..., and multi-group data line 621-1 links to each other with drive integrated circult 650 respectively with 621-2.In this embodiment; Sweep trace 611-1,611-2,611-3,611-4 ... Both sides along liquid crystal panel link to each other with drive integrated circult 650 respectively; And sweep trace 611-1,611-2,611-3,611-4 ..., and multi-group data line 621-1 links to each other with same drive integrated circult 650 with 621-2.This connected mode is merely and illustrates; All sweep traces link to each other with drive integrated circult 650 along the same side of display panels; Perhaps sweep trace 611-1,611-2,611-3,611-4 ... Link to each other with the scanning line driving integrated circuit respectively, multi-group data line 621-1 links to each other also passable respectively with 621-2 with the data line drive integrated circult.
Be the connected mode that example describes infrabasal plate 600 with the first row pixel below, the first row pixel links to each other with sweep trace 611-2 with sweep trace 611-1 respectively, and wherein odd number of pixels links to each other with sweep trace 611-2, and the even number pixel links to each other with sweep trace 611-1.Two adjacent pixels respectively with every group of data line in data line 621-1 or data line 621-2 link to each other, for example first row first pixel in the pixel links to each other with data line 621-1, second pixel links to each other with data line 621-2.Data line 621-1 and data line 621-2 are electrically connected to each other, and link to each other with the drive integrated circult 650 of outside jointly.
Because data line 621-1 and data line 621-2 are electrically connected to each other; Link to each other with the drive integrated circult 650 of outside jointly; Therefore can be through the signal frequency of control with every capable pixel corresponding scanning line; Utilize same lead-in wire to be respectively the pixel input data signal that links to each other with data line 621-2 with data line 621-1, save the external data drive integrated circult, and reduce the purpose of display panels cost widely thereby can reach.
Fig. 7 is the structural representation of adjacent two pixels of the infrabasal plate 600 of double grid line display panels shown in Figure 6.As shown in Figure 7, sweep trace 611-1 and sweep trace 611-2 and data line 621-1 and data line 621-2 intersect and constitute pixel P3 and pixel P4.Each pixel comprises thin film transistor (TFT) 630 and pixel electrode 640, and wherein thin film transistor (TFT) 630 comprises grid 61, source electrode 62 and drains 63.
In pixel P3, the grid 61 of thin film transistor (TFT) 630 links to each other with sweep trace 611-2, and the source electrode 62 of thin film transistor (TFT) 630 links to each other with data line 621-1, and the drain electrode 63 of thin film transistor (TFT) 630 links to each other with pixel electrode 640 through via hole 64.When sweep trace 611-2 input signal, the grid 61 of thin film transistor (TFT) 630 is opened, and the signal of data line 621-1 is through the source electrode 62 and drain electrode 63 input pixel electrodes 640 of thin film transistor (TFT) 630.In pixel P4, the grid 61 of thin film transistor (TFT) 630 links to each other with sweep trace 611-1, and the source electrode 62 of thin film transistor (TFT) 630 links to each other with data line 621-2, and the drain electrode 63 of thin film transistor (TFT) 630 links to each other with pixel electrode 640 through via hole 64.When sweep trace 611-1 input signal, the grid 61 of thin film transistor (TFT) 630 is opened, and the signal of data line 621-2 is through the source electrode 62 and drain electrode 63 input pixel electrodes 640 of thin film transistor (TFT) 630.
In this embodiment; Thin film transistor (TFT) 630 is connected with one of data line 621-2 with every group of data line 621-1, and is positioned at the right side of the data line that is connected with this thin film transistor (TFT) 630, and as shown in Figure 7; Thin film transistor (TFT) 630 is a U type thin film transistor (TFT); Wherein the source electrode 62 of thin film transistor (TFT) 630 is the U type, and in the opening of the U type of the end insertion source electrode 62 of drain electrode 63, the other end of drain electrode 63 is electrically connected with pixel electrode 640 through via hole.And the U type opening of the source electrode 62 of thin film transistor (TFT) 630 is all towards right.Among the present invention; In each pixel; Thin film transistor (TFT) 630 is positioned at the right side of data line 621-1 or data line 621-2, and the U type opening of the source electrode 62 of thin film transistor (TFT) 630 is towards the right side, and drain 63 all be positioned at grid 61 the right side; These all are merely and illustrate, and are paired in restriction of the present invention inadequately.
In carrying out production run, the grid 61 of patterned film transistor 630 at first is then at the source electrode 62 and drain electrode 63 of patterned film transistor 630 thereafter.Between the step and the patterned source 62 of patterning grid 61 and 63 the step of draining, also have other processing steps, repeat no more at this.
Under existing production technology situation; Though mask plate and patterned source 62 that patterning grid 61 is used and drain and have the contraposition deviation between the different layers pattern between the 63 used mask plates; But structure and method to set up owing to thin film transistor (TFT) 630 in the invention described above; In different pixels, difference can not take place in the grid 61 of thin film transistor (TFT) 630 and the overlapping area that drains between 63, thereby guarantees that the stray capacitance Cgd in each pixel is identical; And according under show formula, in the thin film transistor (TFT) 630 of each pixel, produce identical leaping voltage △ Vp.
△Vp＝{Cgd/(Clc+Cst+Cgd)}*Vg
Wherein, Clc is the electric capacity that liquid crystal produces, and Cst is a MM CAP, and Cgd is a stray capacitance, and Vg is a sweep trace voltage.When stray capacitance Cgd changes owing to the contraposition deviation of the pattern between the different layers mask plate; The present invention can guarantee that this is changed to unanimity; Promptly increase same amount simultaneously or reduce same amount simultaneously; Thereby the increase that leaping voltage △ Vp also can be consistent thereupon perhaps reduces; Thereby the uneven phenomenon of light and shade can not take place owing to the difference of leaping voltage △ Vp in the pixel in the picture of the double grid line display panels of making according to the present invention, has guaranteed display quality greatly, has improved image quality.
Below with reference to the driving method of Fig. 6 and Fig. 7 brief description double grid line of the present invention display panels.With the first row pixel is that example describes, and when sweep trace 611-2 input scan signal, the odd number of pixels in the first row pixel is opened, and this moment, data line 621-1 input data signal was for the odd pixel charging in first row; When sweep trace 611-1 input scan signal, the even number pixel in the first row pixel is opened, and this moment, data line 621-2 input data signal charged for the even number pixel in first row, and the rest may be inferred.Sweep trace is with the frequency input scan signal of 120Hz among the present invention, and every group of data line is followed successively by the pixel input data signal that links to each other with one of this group data line, thereby realizes showing.
According to double grid line display panels of the present invention; Can be in the cost that reduces the data line drive integrated circult; Guarantee in each pixel, to produce essentially identical leaping voltage; Thereby avoided the uneven phenomenon of light and shade that occurs in the existing double grid line display panels, improved the display quality of double grid line display panels greatly.
On the other hand; The source electrode of the thin film transistor (TFT) of double grid line display panels of the present invention is the U-shaped structure; This structure can be when guaranteeing pixel aperture ratio; Make thin film transistor (TFT) that enough big breadth length ratio arranged, guaranteed the charging ability of thin film transistor (TFT), guarantee the display quality of double grid line display panels.Certainly, the present invention is not as limit, and is every according to panel construction of the present invention, can guarantee that the thin film transistor (TFT) that stray capacitance is identical in each pixel all can use, and the present invention is preferably U type thin film transistor (TFT).
Those skilled in the art all should be appreciated that, under the situation that does not break away from the spirit or scope of the present invention, can carry out various modifications and modification to the present invention.Thereby, if when any modification and modification fall in the protection domain of appended claims and equivalent thereof, think that the present invention contains these modifications and modification.
Claims (7)
1. display panels, comprise upper substrate, the infrabasal plate relative with said upper substrate and be sandwiched in said upper substrate and said infrabasal plate between liquid crystal layer,
Multi-strip scanning line and many data lines are set on the said infrabasal plate; Said multi-strip scanning line and said many data lines are perpendicular to one another and form a plurality of pixels; And each row pixel is controlled by at least two sweep traces, and each row pixel is by a data lines input signal, and adjacent two data lines are electrically connected to each other; And link to each other with drive integrated circult through same lead-in wire
Form thin film transistor (TFT) in the said pixel, said thin film transistor (TFT) comprises grid, source electrode and drain electrode,
Wherein, in each pixel, with respect to said grid, said drain electrode all is positioned at the same side, and the stray capacitance that produces owing to the overlapping of the grid of thin film transistor (TFT) and drain electrode is identical.
2. display panels according to claim 1, wherein in each pixel, the overlapping area of the grid of said thin film transistor (TFT) and drain electrode equates.
3. display panels according to claim 2, wherein in the thin film transistor (TFT) of each pixel, with respect to said grid, said drain electrode all is positioned at the left side.
4. display panels according to claim 2, wherein in the thin film transistor (TFT) of each pixel, with respect to said grid, said drain electrode all is positioned at the right side.
5. display panels according to claim 2, wherein said thin film transistor (TFT) are U type thin film transistor (TFT).
6. display panels according to claim 1; Wherein adjacent two data lines are electrically connected to each other at the upside of the first row pixel of said display panels, and said adjacent two data lines are electrically connected to each other at the downside of last column pixel of said display panels.
7. display panels according to claim 1, wherein said drive integrated circult is integrated with turntable driving integrated circuit and data-driven integrated circuit.
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| CN2008100440487A CN101750809B (en) | 2008-12-03 | 2008-12-03 | Liquid crystal display panel |
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| CN2008100440487A CN101750809B (en) | 2008-12-03 | 2008-12-03 | Liquid crystal display panel |
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| CN101750809B true CN101750809B (en) | 2012-02-22 |
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Families Citing this family (10)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| TWI491966B (en) | 2010-12-28 | 2015-07-11 | Au Optronics Corp | Liquid crystal display panel and liquid crystal display array substrate |
| US9406702B2 (en) | 2013-03-27 | 2016-08-02 | Beijing Boe Optoelectronics Technology Co., Ltd. | Array substrate, method for fabricating the same and display device |
| CN103186001B (en) * | 2013-03-27 | 2015-12-02 | 北京京东方光电科技有限公司 | A kind of array base palte and manufacture method, display device |
| CN103278990B (en) * | 2013-05-28 | 2017-08-25 | 京东方科技集团股份有限公司 | Dot structure and liquid crystal panel |
| CN108535929A (en) * | 2018-05-28 | 2018-09-14 | 京东方科技集团股份有限公司 | Display base plate and display device |
| CN109061971A (en) * | 2018-09-07 | 2018-12-21 | 京东方科技集团股份有限公司 | Array substrate and display panel |
| CN110931504A (en) * | 2019-09-17 | 2020-03-27 | 深圳市华星光电半导体显示技术有限公司 | Array substrate and display panel |
| CN111025804A (en) * | 2019-12-12 | 2020-04-17 | 深圳市华星光电半导体显示技术有限公司 | Liquid crystal display device having a plurality of pixel electrodes |
| CN111564132A (en) * | 2020-05-29 | 2020-08-21 | 厦门天马微电子有限公司 | Shift register, display panel and display device |
| CN113611699A (en) * | 2021-07-20 | 2021-11-05 | 深圳市华星光电半导体显示技术有限公司 | Display panel |
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