CN109061971A - Array substrate and display panel - Google Patents
Array substrate and display panel Download PDFInfo
- Publication number
- CN109061971A CN109061971A CN201811044238.9A CN201811044238A CN109061971A CN 109061971 A CN109061971 A CN 109061971A CN 201811044238 A CN201811044238 A CN 201811044238A CN 109061971 A CN109061971 A CN 109061971A
- Authority
- CN
- China
- Prior art keywords
- extension
- array substrate
- grid
- data line
- drain electrode
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000000758 substrate Substances 0.000 title claims abstract description 25
- 239000010409 thin film Substances 0.000 claims abstract description 14
- 238000010586 diagram Methods 0.000 description 3
- 230000007423 decrease Effects 0.000 description 2
- 238000009413 insulation Methods 0.000 description 1
- 239000004973 liquid crystal related substance Substances 0.000 description 1
- 238000000034 method Methods 0.000 description 1
- 230000003287 optical effect Effects 0.000 description 1
- 230000005855 radiation Effects 0.000 description 1
Classifications
-
- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
- G02F1/1362—Active matrix addressed cells
- G02F1/136286—Wiring, e.g. gate line, drain line
-
- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
- G02F1/1362—Active matrix addressed cells
- G02F1/136213—Storage capacitors associated with the pixel electrode
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/417—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions carrying the current to be rectified, amplified or switched
- H01L29/41725—Source or drain electrodes for field effect devices
- H01L29/41733—Source or drain electrodes for field effect devices for thin film transistors with insulated gate
Abstract
The invention discloses a kind of array substrate and display panels.Array substrate includes: grid line, data line, pixel electrode and thin film transistor (TFT).Grid line and data line, which intersect, to be arranged to define a pixel unit；Thin film transistor (TFT) is arranged in pixel unit.Thin film transistor (TFT) includes grid, active layer, drain electrode and source electrode；Grid and grid line are electrically connected；Active layer is arranged on grid；Drain electrode and source electrode are formed on active layer；Drain electrode is connect with pixel electrode；Source electrode is connect with data line.Drain electrode is in U-shape, the Liang Ge branch including interconnecting piece He the both ends that interconnecting piece is arranged in；Interconnecting piece is obliquely installed relative to grid line；Liang Ge branch is obliquely installed relative to data line.Source electrode includes the first extension and the second extension；First extension is connect with data line；Second extension from one end of the first extension obliquely, be outwardly directed to drain electrode extend between Liang Ge branch.
Description
Technical field
The present invention relates to field of display technology, more particularly to a kind of array substrate and display panel.
Background technique
The features such as Thin Film Transistor-LCD specific small size, low power consumption, no radiation, in current flat-panel monitor
Leading position is occupied in market.With the fast development of large scale, high-resolution liquid crystal display, signal delay had become system already
About large scale, high-resolution Thin Film Transistor-LCD an important factor for.
Summary of the invention
The embodiment of the present invention provides a kind of array substrate and display panel, can reduce signal delay.
The embodiment of the present invention provides a kind of array substrate, comprising: the grid line that is arranged along a first direction, along second direction
Data line, pixel electrode and the thin film transistor (TFT) of setting.Wherein, the grid line and the data line, which intersect, is arranged to define
One pixel unit；The thin film transistor (TFT) is arranged in the pixel unit.The thin film transistor (TFT) includes grid, active
Layer, drain electrode and source electrode；The grid and the grid line are electrically connected；The active layer is arranged on the grid；The drain electrode
It is formed on the active layer with the source electrode；The drain electrode is connect with the pixel electrode；The source electrode and the data line
Connection.The drain electrode is in U-shape, the Liang Ge branch including interconnecting piece He the both ends that the interconnecting piece is arranged in；The interconnecting piece phase
The grid line being arranged along the first direction is obliquely installed；Described two branches are relative to connecting with the source electrode
The data line is obliquely installed.The source electrode includes the first extension and the second extension；First extension is along described
First direction setting, and connect with the data line；Second extension from one end of first extension obliquely, to
It is outer to be extended between described two branches towards the drain electrode.
Optionally, the first direction is horizontal direction；The second direction is vertical direction.
Optionally, second extension and the interconnecting piece interval are arranged；And second extension and described two
A branch interval setting.
Optionally, second extension is parallel to described two branches.
Optionally, the width of second extension is less than the width of each in described two branches.
Optionally, described two branches are vertically disposed at the both ends of the interconnecting piece.
Optionally, the opening of the U-shaped is obliquely towards the data line connecting with the source electrode.
Optionally, the grid and the grid line are integrally formed；The drain electrode is connect by conductive structure with pixel electrode.
The embodiment of the present invention also provides a kind of display panel, including above-mentioned array substrate.
Array substrate in the embodiment of the present invention and the display panel using array substrate, by using the U being obliquely installed
The second extension being obliquely installed in the drain electrode of shape and source electrode matches, and the load capacitance of data line can effectively decline, thus
Signal delay can be slowed down and power consumption and drain drives chip (source IC) temperature is effectively reduced.
Detailed description of the invention
Technical solution in order to illustrate the embodiments of the present invention more clearly or in the related technology, below will be to embodiment or phase
Attached drawing needed in technical description is closed to be briefly described, it should be apparent that, the accompanying drawings in the following description is only this
Some embodiments of invention without any creative labor, may be used also for those of ordinary skill in the art
To obtain other drawings based on these drawings.
Fig. 1 is the structural schematic diagram of array substrate in the embodiment of the present invention；And
Fig. 2 is the overlapping area schematic diagram in array substrate shown in FIG. 1 between grid line and data line.
Specific embodiment
Below in conjunction with drawings and examples, specific embodiments of the present invention will be described in further detail.Following reality
Example is applied for illustrating the present invention, but is not intended to limit the scope of the invention.
Fig. 1 is the structural schematic diagram of array substrate in the embodiment of the present invention.As shown in Figure 1, array substrate 130 includes grid line
132, data line 134, pixel electrode 136 and thin film transistor (TFT) 138.
Wherein, grid line 132 and data line 134 intersect setting, to define a pixel unit.Each pixel unit
In a thin film transistor (TFT) 138 can be set.In the embodiment shown in fig. 1, grid line 132 D1 such as level side along a first direction
To setting, and data line 134 is arranged along second direction D2 such as vertical direction.
Wherein, thin film transistor (TFT) 138 includes grid 1382, gate insulation layer (not shown), active layer 1384, drain electrode
1386 and source electrode 1388.
Grid 1382 and grid line 132 are electrically connected.In one embodiment, grid 1382 and grid line 132 are integrally formed.
Active layer 1384 is arranged on grid 1382.Drain electrode 1386 and source electrode 1388 are formed on active layer 1384.Drain electrode
1386 can be connect by via hole 1389 with pixel electrode 136.Source electrode 1388 is connect with data line 134.
In the embodiment shown in fig. 1, drain electrode 1386 is substantially u-shaped, including interconnecting piece 13862 and Liang Ge branch 13864.
Liang Ge branch 13864 is vertically disposed at the both ends of interconnecting piece 13862, and extends in the same direction from the both ends of interconnecting piece 13862.It needs
Illustrate, " vertical " refers to that the angle between branch 13864 and interconnecting piece 13862 can be 90 degree or and phase quadrature herein
In a certain range as in 20%.The grid line 132 for example horizontally arranged relative to D1 along a first direction of interconnecting piece 13862 inclines
Tiltedly setting, that is, there are angles between interconnecting piece 13862 and along a first direction D1 such as horizontally arranged grid line 132.Two
Branch 13864 is obliquely installed relative to the data line 134 connecting with source electrode 1388, i.e., each branch 13864 and with source electrode 1388
Angle is formed between the data line 134 of connection.In other words, Liang Ge branch 13864 from the both ends of interconnecting piece 13862 towards and source electrode
The data line 134 of 1388 connections obliquely extends, i.e., the opening of U-shaped is obliquely towards the data line 134 connecting with source electrode 1388.
In the embodiment shown in fig. 1, source electrode 1388 includes the first extension 13882 and the second extension 13884.First
D1 is for example horizontally arranged along a first direction for extension 13882, and one end is connect with data line 134.Second extension 13884
From one end of the first extension 13882 obliquely, be outwardly directed to drain electrode 1386 and extend, and extend to inside U-shaped.Second extension
13884 are arranged with interconnecting piece 13862 and the interval of Liang Ge branch 13864.Second extension 13884 is parallel to Liang Ge branch 13864.
In one embodiment, the width of the second extension 13884 is less than the width of branch 13864.
The above-mentioned specific structure for the array substrate 130 in the embodiment of the present invention.Referring to fig. 2, grid line 132 and data line
Overlapping area between 134 is as shown in black shaded area in Fig. 2.As it can be seen that the overlapping face between grid line 132 and data line 134
Product is smaller, advantageously reduces the load capacitance of data line 134, and then slow down signal delay and be effectively reduced power consumption.
It by taking 23.6HD ADS product pixel size as an example, is loaded by software emulation, using the above-mentioned U-shaped being obliquely installed
The optical parameter for the display panel that the second extension 13884 for being obliquely installed matches in drain electrode 1386 and source electrode 1388 to it is related
Panel in technology is almost the same, and the load capacitance of data line 134 can decline 24%, so as to slow down signal delay, simultaneously
Power consumption and drain drives chip (source IC) temperature is effectively reduced.
A kind of display panel, including array substrate as described above are also provided in the embodiment of the present invention.
The above is only a preferred embodiment of the present invention, it is noted that for the ordinary skill people of the art
For member, without departing from the technical principles of the invention, several improvement and replacement can also be made, these are improved and replacement
Also it should be regarded as protection scope of the present invention.
Claims (9)
1. a kind of array substrate, comprising:
The grid line being arranged along a first direction；
The data line being arranged along second direction；
Pixel electrode；With
Thin film transistor (TFT)；
Wherein, the grid line and the data line, which intersect, is arranged to define a pixel unit；The thin film transistor (TFT) is set
It sets in the pixel unit；
The thin film transistor (TFT) includes grid, active layer, drain electrode and source electrode；The grid and the grid line are electrically connected；It is described
Active layer is arranged on the grid；The drain electrode and the source electrode are formed on the active layer；The drain electrode and the picture
Plain electrode connection；The source electrode is connect with the data line；
The drain electrode is in U-shape, the Liang Ge branch including interconnecting piece He the both ends that the interconnecting piece is arranged in；The interconnecting piece is opposite
It is obliquely installed in the grid line being arranged along the first direction；Described two branches are relative to the institute connecting with the source electrode
Data line is stated to be obliquely installed；
The source electrode includes the first extension and the second extension；First extension is arranged along the first direction, and
It is connect with the data line；Second extension from one end of first extension obliquely, be outwardly directed to the drain electrode
It extends between described two branches.
2. array substrate according to claim 1, which is characterized in that the first direction is horizontal direction；Described second
Direction is vertical direction.
3. array substrate according to claim 2, which is characterized in that second extension is set with the interconnecting piece interval
It sets；And second extension and described two branch intervals are arranged.
4. array substrate according to claim 3, which is characterized in that second extension is parallel to described two
Portion.
5. array substrate according to claim 4, which is characterized in that the width of second extension is less than described two
The width of each in branch.
6. array substrate according to claim 3, which is characterized in that described two branches are vertically disposed at the connection
The both ends in portion.
7. array substrate according to claim 6, which is characterized in that the opening of the U-shaped obliquely towards and the source
The data line of pole connection.
8. array substrate according to claim 1, which is characterized in that the grid and the grid line are integrally formed；It is described
Drain electrode is connect by conductive structure with the pixel electrode.
9. a kind of display panel, including according to claim 1 to array substrate described in any one of 8.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201811044238.9A CN109061971A (en) | 2018-09-07 | 2018-09-07 | Array substrate and display panel |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201811044238.9A CN109061971A (en) | 2018-09-07 | 2018-09-07 | Array substrate and display panel |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN109061971A true CN109061971A (en) | 2018-12-21 |
Family
ID=64760984
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201811044238.9A Pending CN109061971A (en) | 2018-09-07 | 2018-09-07 | Array substrate and display panel |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN109061971A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN114236932A (en) * | 2022-01-21 | 2022-03-25 | 厦门天马微电子有限公司 | Display panel and display device |
| CN115032842A (en) * | 2022-07-01 | 2022-09-09 | 武汉华星光电技术有限公司 | Display panel and display terminal |
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|---|---|---|---|---|
| US20030122990A1 (en) * | 2001-12-31 | 2003-07-03 | Kim Ik Soo | Array substrate for in-plane switching mode liquid crystal display device and method of fabricating the same |
| CN101030603A (en) * | 2006-03-03 | 2007-09-05 | 中华映管股份有限公司 | Thin-film transistor and thin-film transistor array base plate |
| CN101556959A (en) * | 2008-04-10 | 2009-10-14 | 北京京东方光电科技有限公司 | Array base plate and liquid crystal display unit |
| CN101750809A (en) * | 2008-12-03 | 2010-06-23 | 上海天马微电子有限公司 | Liquid crystal display panel |
| CN101750826A (en) * | 2009-12-28 | 2010-06-23 | 深超光电（深圳）有限公司 | Pixel structure |
| CN102156367A (en) * | 2010-08-04 | 2011-08-17 | 京东方科技集团股份有限公司 | Array substrate, liquid crystal panel and liquid crystal displayer |
| CN102520555A (en) * | 2011-12-02 | 2012-06-27 | 深圳市华星光电技术有限公司 | Pixel structure, array substrate and liquid crystal display device |
| CN107577097A (en) * | 2016-07-05 | 2018-01-12 | 三星显示有限公司 | Liquid crystal display |
| WO2018128107A1 (en) * | 2017-01-06 | 2018-07-12 | シャープ株式会社 | Curved display panel |
-
2018
- 2018-09-07 CN CN201811044238.9A patent/CN109061971A/en active Pending
Patent Citations (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20030122990A1 (en) * | 2001-12-31 | 2003-07-03 | Kim Ik Soo | Array substrate for in-plane switching mode liquid crystal display device and method of fabricating the same |
| CN101030603A (en) * | 2006-03-03 | 2007-09-05 | 中华映管股份有限公司 | Thin-film transistor and thin-film transistor array base plate |
| CN101556959A (en) * | 2008-04-10 | 2009-10-14 | 北京京东方光电科技有限公司 | Array base plate and liquid crystal display unit |
| CN101750809A (en) * | 2008-12-03 | 2010-06-23 | 上海天马微电子有限公司 | Liquid crystal display panel |
| CN101750826A (en) * | 2009-12-28 | 2010-06-23 | 深超光电（深圳）有限公司 | Pixel structure |
| CN102156367A (en) * | 2010-08-04 | 2011-08-17 | 京东方科技集团股份有限公司 | Array substrate, liquid crystal panel and liquid crystal displayer |
| CN102520555A (en) * | 2011-12-02 | 2012-06-27 | 深圳市华星光电技术有限公司 | Pixel structure, array substrate and liquid crystal display device |
| CN107577097A (en) * | 2016-07-05 | 2018-01-12 | 三星显示有限公司 | Liquid crystal display |
| WO2018128107A1 (en) * | 2017-01-06 | 2018-07-12 | シャープ株式会社 | Curved display panel |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN114236932A (en) * | 2022-01-21 | 2022-03-25 | 厦门天马微电子有限公司 | Display panel and display device |
| CN114236932B (en) * | 2022-01-21 | 2023-12-15 | 厦门天马微电子有限公司 | Display panel and display device |
| CN115032842A (en) * | 2022-07-01 | 2022-09-09 | 武汉华星光电技术有限公司 | Display panel and display terminal |
| CN115032842B (en) * | 2022-07-01 | 2023-11-28 | 武汉华星光电技术有限公司 | Display panel and display terminal |
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