CN101030603A - Thin-film transistor and thin-film transistor array base plate - Google Patents
Thin-film transistor and thin-film transistor array base plate Download PDFInfo
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- CN101030603A CN101030603A CN 200610057880 CN200610057880A CN101030603A CN 101030603 A CN101030603 A CN 101030603A CN 200610057880 CN200610057880 CN 200610057880 CN 200610057880 A CN200610057880 A CN 200610057880A CN 101030603 A CN101030603 A CN 101030603A
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Abstract
The invention is concerned with the thin film transistor, includes: the grid, the grid insolating layer, the path layer, the helix source electrode and the helix drain electrode. It is: the grid insolating layer covers the grid; the path layer sets on the grid insolating layer that is on top of the grid; the helix source electrode sets on the path layer that is on the top of the grid; the helix drain electrode sets on the path layer that is on the top of the grid; the helix source electrode and the helix drain electrode is set with the revolving state. The invention can improve the W/L ratio of the path, and reduce the parasitic capacitance Cgd of the source electrode and the drain electrode.
Description
Technical field
The present invention relates to a kind of thin-film transistor, and be particularly related to and a kind ofly can improve passage W/L ratio, and can reduce gate-to-drain parasitic capacitance C
Gd, and and then effectively reduce the thin-film transistor of feed-trough voltage (feedthrough voltage, Δ Vp).
Background technology
Display has become important man-machine communication interface, and the user can read the operation of information and then control device by display, wherein, is again the emphasis of development with the LCD.Generally speaking, LCD is made of thin-film transistor array base-plate, colored optical filtering substrates and the liquid crystal layer between two substrates.Wherein, (Thin FilmTransistor mainly is that the data that are used for controlling LCD write TFT) to thin-film transistor, and it has comprised grid (gate), channel layer (channel) and source/drain elements such as (source/drain).
Fig. 1 is the schematic top plan view of known thin-film transistor array base-plate.Please refer to Fig. 1, mainly be provided with a plurality of dot structures 110 on the thin-film transistor array base-plate 100 with arrayed.Wherein, each dot structure 110 is all formed by scan line (scan line) 112, data wire (dateline) 114, thin-film transistor 116 and with 118 of the pixel electrodes (pixel electrode) of thin-film transistor 116 corresponding settings.
Please continue with reference to Fig. 1, thin-film transistor 116 is intended for the switch element of dot structure 110, scan wiring 112 and data wiring 114 then are to be used to provide the suitable operating voltage of its selected dot structure 110, the display image to drive each dot structure 110 respectively.
It should be noted that this thin-film transistor 116 is to utilize the part of scan line 112 as grid 116a, and directly after forming semiconductor layer 116b on the scan line 112, go up in semiconductor layer 116b again and form source electrode 116c and drain electrode 116d.Source electrode 116c and the part semiconductor layer 116b of drain electrode between the 116d promptly are passages, this passage have channel width W (channelwidth, W) and passage length L (channel length, L).When channel width W broad and passage length L more in short-term, the service speed of thin-film transistor 116 is very fast.But,, therefore among limited area, be not easy to make channel width W to become big manufacturing because the channel layer 116b that is formed on the scan line 112 has only certain area.
In addition, please continue with reference to Fig. 1, when desiring to make display to show predetermined picture, must open thin-film transistor 116 and be applied to voltage on the pixel electrode 118, and then make and be positioned at liquid crystal molecule (not shown) deflection between common electrode (commonelectrode) (not shown) on pixel electrode 118 and the colored optical filtering substrates (not shown) with control.So, can change the polarization direction along with the deflection of liquid crystal molecule by the light of liquid crystal molecule, and the polarised light of part can penetrate the purpose that is arranged at the Polarizer on the colored filter and reaches demonstration.It should be noted that liquid crystal molecule will have liquid crystal capacitance C in the above-mentioned process that applies voltage
LC, this liquid crystal capacitance C
LCBe to be coupled to form by the common electrode (not shown) on pixel electrode 118 and the colored optical filtering substrates.
Hold above-mentioned, when thin-film transistor 116 cuts out, liquid crystal capacitance C
LCOn the voltage that applied still keep certain value, but, owing between the grid 116a of thin-film transistor 116 and the drain electrode 116d zone that overlaps each other is arranged, between grid 116a and drain electrode 116d, can there be gate-to-drain parasitic capacitance (parasitic capacitance) C
Gd, and because gate-to-drain parasitic capacitance C
GdExistence, make liquid crystal capacitance C
LCOn the voltage that kept will change and change to some extent along with the signal on the data wiring 114, thereby make liquid crystal capacitance C
LCOn the original value of setting of the voltage deviation that kept.This variation in voltage amount is called feed-trough voltage (feed-throughvoltage) Δ Vp, and it can be expressed as:
Wherein Δ Vg is the amplitude that puts on the pulse voltage on the scan wiring 112, and C
StBe storage capacitors (storage capacitance).
Therefore, if can reduce gate-to-drain parasitic capacitance C
Gd, just can reduce Δ Vp, just can reduce the variation of feed-trough voltage, so can make display frame occur showing that the situation of uneven (mura) or flicker (flicker) is improved.
Summary of the invention
In view of this, purpose of the present invention just provides a kind of thin-film transistor, and it can improve passage W/L ratio, and can reduce gate-to-drain parasitic capacitance C
Gd
A further object of the present invention provides a kind of thin-film transistor array base-plate, its comprised have can improve passage W/L than and can reduce gate-to-drain parasitic capacitance C
GdThin-film transistor.
Based on above-mentioned purpose or other purposes, the present invention proposes a kind of thin-film transistor, and it comprises grid, gate insulation layer, channel layer, helical form source electrode and helical form drain electrode.The gate insulation layer cover gate.Channel layer is arranged on the gate insulation layer of grid top.The helical form source electrode is arranged on the channel layer of grid top, and the helical form drain electrode is arranged on the channel layer of grid top, and wherein the drain electrode of helical form source electrode and helical form is to be provided with around the state that revolves mutually.
Based on above-mentioned purpose or other purposes, the present invention reintroduces a kind of thin-film transistor array base-plate, and it comprises substrate, scan line, data wire, thin-film transistor and pixel electrode.The multi-strip scanning line is arranged on the substrate.Many data wire is arranged on the substrate, and wherein scan line and data wire are divided into a plurality of pixel regions with substrate zone.A plurality of thin-film transistors are arranged on the substrate, and each thin-film transistor be positioned at pixel region one of them, and thin-film transistor is to drive by scan line and data wire, and wherein each thin-film transistor comprises grid, gate insulation layer, channel layer, helical form source electrode and helical form drain electrode.The gate insulation layer cover gate.Channel layer is arranged on the gate insulation layer of grid top.The helical form source electrode is arranged on the channel layer of grid top, and the helical form drain electrode is arranged on the channel layer of grid top, and wherein the drain electrode of helical form source electrode and helical form is to be provided with around the state that revolves mutually.Pixel electrode is arranged on the substrate, and each pixel electrode be positioned at pixel region one of them, and each pixel electrode and corresponding thin-film transistor are electrically connected.
In one embodiment of this invention, the drain electrode of above-mentioned helical form source electrode and helical form is to rotate in a counter-clockwise direction and be provided with.
In one embodiment of this invention, the drain electrode of above-mentioned helical form source electrode and helical form is to rotate in a clockwise direction and be provided with.
In one embodiment of this invention, above-mentioned grid and scan line are same metal levels.
In one embodiment of this invention, above-mentioned helical form source electrode and data wire one of them be electrically connected.
In one embodiment of this invention, one of them is electrically connected with pixel electrode in above-mentioned helical form drain electrode.
The present invention is because of adopting the design of helical form source electrode and helical form drain electrode, so on the channel layer of limited area, can be so that the channel width (W) between helical form source electrode and the helical form drain electrode broadens, and passage length (L) can almost remain unchanged, therefore, therefore the ratio of channel width and passage length (W/L) can become big.In addition, the design of this kind thin-film transistor can reduce gate-to-drain parasitic capacitance C
Gd, thereby reduce feed-trough voltage Δ Vp.So, this thin-film transistor is applied in the display floater, can be improved so that show uneven (mura) or flicker problems such as (flicker).
For above-mentioned and other purposes, feature and advantage of the present invention can be become apparent, preferred embodiment cited below particularly, and conjunction with figs. are described in detail below.
Description of drawings
Fig. 1 is the schematic top plan view of known thin-film transistor array base-plate.
Fig. 2 is the schematic top plan view of a kind of thin-film transistor in the preferred embodiment of the present invention.
Fig. 2 A is along the generalized section of A-A ' line among Fig. 2.
Fig. 3 is the schematic top plan view of another kind of thin-film transistor in the preferred embodiment of the present invention.
Fig. 4 is the schematic top plan view of a kind of thin-film transistor array base-plate in the preferred embodiment of the present invention.
The main element description of symbols
100,300: thin-film transistor array base-plate
110: dot structure
112,270: scan line
114,280: data wire
116,200: thin-film transistor
116a, 210: grid
116b: semiconductor layer
116c: source electrode
116d: drain electrode
118,290: pixel electrode
220: gate insulation layer
230: channel layer
240a, 240b: helical form source electrode
250a, 250b: helical form drain electrode
260: protective layer
262: opening
310: substrate
312: pixel region
A-A ': hatching
W: channel width
L: passage length
Embodiment
Fig. 2 is the schematic top plan view of a kind of thin-film transistor in the preferred embodiment of the present invention.Fig. 2 A is along the generalized section of A-A ' line among Fig. 2.
Please jointly with reference to Fig. 2 and Fig. 2 A, this thin-film transistor 200 comprises grid 210, gate insulation layer 220, channel layer 230, helical form source electrode 240a and helical form drain electrode 250a.Gate insulation layer 220 cover gate 210.Channel layer 230 is arranged on the gate insulation layer 220 of grid 210 tops.Helical form source electrode 240a is arranged on the channel layer 230 of grid 210 tops, and helical form drain electrode 250a is arranged on the channel layer 230 of grid 210 tops, and wherein helical form source electrode 240a and helical form drain electrode 250a is to be provided with around the state that revolves mutually.
Please refer to Fig. 2 and Fig. 2 A, thin-film transistor 200 constitutes dot structure with scan line 270, data wire 280, pixel electrode 290 etc.And, generally can on thin-film transistor 200, cover layer protective layer 260, and on protective layer 260, form opening 262, make pixel electrode 290 see through this opening 262 afterwards again and be electrically connected with thin-film transistor 200.
It should be noted that in one embodiment of this invention helical form source electrode 240a and helical form drain electrode 250a rotates in a counter-clockwise direction and is provided with, as shown in Figure 2.But in another embodiment of the present invention, helical form source electrode 240b and helical form drain electrode 250b rotates in a clockwise direction and is provided with, as shown in Figure 3.By Fig. 2 and Fig. 3 as can be known, because helical form source electrode 240a and helical form drain electrode 250a, and helical form source electrode 240b and helical form drain electrode 250b all is to be provided with around the mode of revolving mutually, so, even on the channel layer 230 of limited area, the present invention also can increase channel width W effectively, and passage length L is almost remained unchanged.Thus, just can increase the ratio (W/L) of channel width W and passage length L, it should be noted that the number of turns that the present invention more can utilize helical form source electrode 240a, 240b and helical form source electrode 250a, 250b to be reeled, and then suitably adjust the ratio of channel width W and passage length L.
Referring again to Fig. 2, in addition, because helical form source electrode 240a can form passage to the helical form of its both sides drain electrode 250a, so, can improve the service speed of thin-film transistor 200.Moreover, thin-film transistor 200 of the present invention, the profile of its helical form source electrode 240a, 240b and helical form drain electrode 250a, 250b is not limited to the square shown in Fig. 2 and Fig. 3, and it also can be circle, ellipse or polygon etc.
In addition, thin-film transistor 200 of the present invention can reduce the parasitic capacitance (below be called Cgd) between grid and drain electrode, cooperates the formula of feed-trough voltage (below be called Δ Vp),
Because Cgd has reduced, so Δ Vp also decreases.
For proving that further thin-film transistor 200 of the present invention has lower Cgd and Δ Vp, therefore, make the channel width W of thin-film transistor 200 of the present invention and the ratio (W/L) of passage length L, be close with the channel width W of known thin-film transistor 110 and the ratio (W/L) of passage length L, and both Cgd and Δ Vp relatively, result that can table 1.
Table 1
| Known thin-film transistor | Thin-film transistor of the present invention | |
| W/L | 35/3 | 36/3 |
| Cgd(F) | 2.04E-14 | 1.7E-14 |
| ΔVp(V) | 0.486 | 0.406 |
As shown in Table 1, the Cgd of thin-film transistor 200 of the present invention has reduced by 16.65% approximately, and Δ Vp has reduced by 16.48% approximately, and hence one can see that, and the design of helical form source electrode 240a of the present invention, 240b and helical form drain electrode 250a, 250b can reduce Cgd and Δ Vp really effectively.Below will illustrate and use thin-film transistor 200 of the present invention in an embodiment of thin-film transistor array base-plate.
Fig. 4 is shown the schematic top plan view of a kind of thin-film transistor array base-plate in the preferred embodiment of the present invention.Please be simultaneously with reference to Fig. 4 and Fig. 2 A, this thin-film transistor array base-plate 300 comprises substrate 310, scan line 270, data wire 280, thin-film transistor 200 and pixel electrode 290.Multi-strip scanning line 270 is arranged on the substrate 310.Many data wire 280 is arranged on the substrate 310, and wherein scan line 270 is divided into a plurality of pixel regions 312 with data wire 280 with substrate 310.A plurality of thin-film transistors 200 are arranged on the substrate 310, and each thin-film transistor 200 be positioned at pixel region 312 one of them, and thin-film transistor 200 is to drive by scan line 270 and data wire 280, wherein each thin-film transistor 200 in described in Fig. 2, Fig. 2 A or Fig. 3, will no longer be repeated at this.Pixel electrode 290 is arranged on the substrate 310, and each pixel electrode 290 be positioned at pixel region 312 one of them, and each pixel electrode 290 and corresponding thin-film transistor 200 are electrically connected.
Please continue with reference to Fig. 4 and Fig. 2 A, in one embodiment of this invention, grid 210 is same metal levels with scan line 270, that is to say, thin-film transistor 200 is to utilize scan line 270 metals own to be used as grid 210.In addition, one of them is electrically connected helical form source electrode 240a and data wire 280, and helical form drain electrode 250a and pixel electrode 290 one of them be electrically connected.
Hold above-mentioned, thin-film transistor array base-plate 300 with above-mentioned thin-film transistor 200, because the design of thin-film transistor 200 can reduce Cgd effectively, and then Δ Vp is reduced, so, this thin-film transistor array base-plate 300 has preferable operating characteristic, when being applied to display floater, can be improved by problems such as excessive caused demonstration inequality of feed-trough voltage Δ Vp or flickers.
In sum, thin-film transistor and thin-film transistor array base plate of the present invention has following advantage:
(1) the present invention is because of adopting the design of helical form source electrode and helical form drain electrode, so on the channel layer of limited area, can improve passage W/L ratio.
(2) because the helical form source electrode can all form passage to the drain electrode of the helical form of its both sides, so, the service speed of thin-film transistor can be improved.
(3) because thin-film transistor of the present invention can reduce the parasitic capacitance Cgd between grid and drain electrode effectively, therefore, and then can reduce feed-trough voltage Δ Vp.So, utilize the design of this thin-film transistor and be made into thin-film transistor array base-plate, and when being applied to display floater, can be improved by problems such as excessive caused demonstration inequality of feed-trough voltage Δ Vp or flickers.
Though the present invention discloses as above with preferred embodiment; right its is not in order to limit the present invention; any person of ordinary skill in the field; without departing from the spirit and scope of the present invention; when can doing a little change and improvement, so protection scope of the present invention is as the criterion when looking the claim person of defining.
Claims (9)
1. thin-film transistor is characterized in that comprising:
Grid;
Gate insulation layer covers this grid;
Channel layer is arranged on this gate insulation layer of this grid top;
The helical form source electrode is arranged on this channel layer of this grid top; And
The helical form drain electrode is arranged on this channel layer of this grid top, and wherein the drain electrode of this helical form source electrode and this helical form is to be provided with around the state that revolves mutually.
2. thin-film transistor according to claim 1 is characterized in that the drain electrode of this helical form source electrode and this helical form is to rotate in a counter-clockwise direction and be provided with.
3. thin-film transistor according to claim 1 is characterized in that the drain electrode of this helical form source electrode and this helical form is to rotate in a clockwise direction and be provided with.
4. thin-film transistor array base-plate is characterized in that comprising:
Substrate;
The multi-strip scanning line is arranged on this substrate;
Many data wires are arranged on this substrate, and wherein above-mentioned these scan lines and above-mentioned these data wires are divided into a plurality of pixel regions with this substrate zone;
A plurality of thin-film transistors, be arranged on this substrate, and each thin-film transistor be positioned at above-mentioned these pixel regions one of them, and above-mentioned these thin-film transistors are to drive by above-mentioned these scan lines and above-mentioned these data wires, wherein each thin-film transistor comprises:
Grid;
Gate insulation layer covers this grid;
Channel layer is arranged on this gate insulation layer of this grid top;
The helical form source electrode is arranged on this channel layer of this grid top;
The helical form drain electrode is arranged on this channel layer of grid top, and wherein, this helical form source electrode and the drain electrode of this helical form are to be provided with around the state that revolves mutually; And
A plurality of pixel electrodes are arranged on this substrate, and each pixel electrode be positioned at above-mentioned these pixel regions one of them, and each pixel electrode and corresponding this thin-film transistor are electrically connected.
5. thin-film transistor array base-plate according to claim 4 is characterized in that the drain electrode of this helical form source electrode and this helical form is to rotate in a counter-clockwise direction and be provided with.
6. thin-film transistor array base-plate according to claim 4 is characterized in that the drain electrode of this helical form source electrode and this helical form is to rotate in a clockwise direction and be provided with.
7. thin-film transistor array base-plate according to claim 4 is characterized in that this grid and this scan line are same metal levels.
8. thin-film transistor array base-plate according to claim 4, one of them is electrically connected to it is characterized in that this helical form source electrode and above-mentioned these data wires.
9. thin-film transistor array base-plate according to claim 4, one of them is electrically connected with above-mentioned these pixel electrodes to it is characterized in that this helical form drain electrode.
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| CN102315227A (en) * | 2010-06-30 | 2012-01-11 | 北京京东方光电科技有限公司 | Thin film transistor (TFT) array substrate and manufacturing method thereof and detection method |
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| CN103915509A (en) * | 2014-03-25 | 2014-07-09 | 京东方科技集团股份有限公司 | Membrane transistor, array substrate and display device |
| CN103995406A (en) * | 2013-02-19 | 2014-08-20 | 群创光电股份有限公司 | Liquid crystal display panel |
| CN104600124A (en) * | 2015-01-21 | 2015-05-06 | 重庆京东方光电科技有限公司 | Thin film transistor structure, manufacturing method thereof, array substrate and mask plate |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN102315227A (en) * | 2010-06-30 | 2012-01-11 | 北京京东方光电科技有限公司 | Thin film transistor (TFT) array substrate and manufacturing method thereof and detection method |
| CN102315227B (en) * | 2010-06-30 | 2013-04-03 | 北京京东方光电科技有限公司 | Thin film transistor (TFT) array substrate and manufacturing method thereof and detection method |
| CN102867853A (en) * | 2011-07-08 | 2013-01-09 | 新唐科技股份有限公司 | Metal Oxide Half Field Effect Transistor |
| CN102867853B (en) * | 2011-07-08 | 2015-09-23 | 新唐科技股份有限公司 | Metal Oxide Half Field Effect Transistor |
| US9269704B2 (en) | 2012-05-15 | 2016-02-23 | Nuvoton Technology Corporation | Semiconductor device with embedded silicon-controlled rectifier |
| CN103995406A (en) * | 2013-02-19 | 2014-08-20 | 群创光电股份有限公司 | Liquid crystal display panel |
| CN103915509A (en) * | 2014-03-25 | 2014-07-09 | 京东方科技集团股份有限公司 | Membrane transistor, array substrate and display device |
| CN104600124A (en) * | 2015-01-21 | 2015-05-06 | 重庆京东方光电科技有限公司 | Thin film transistor structure, manufacturing method thereof, array substrate and mask plate |
| WO2016115783A1 (en) * | 2015-01-21 | 2016-07-28 | 京东方科技集团股份有限公司 | Thin film transistor structure and preparation method therefor, array substrate and mask plate |
| CN109061971A (en) * | 2018-09-07 | 2018-12-21 | 京东方科技集团股份有限公司 | Array substrate and display panel |
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