KR101798868B1 - Liquid crystal display device and method for manufacturing the same - Google Patents

Abstract

The present invention relates to a liquid crystal display device, and more particularly to a liquid crystal display device which removes an active tail of a data line semiconductor layer formed at a lower end of a data line, And a protective film covering the data line and the data line semiconductor layer, and a method of manufacturing the same. To this end, the liquid crystal display according to the present invention includes a plurality of pixels formed by intersection of gate lines and data lines, and includes a plurality of pixels, each of which includes an end of a data line protective film covering each of the data lines, A liquid crystal panel in which a distance between pixel electrodes formed in the liquid crystal panel is constant; And a driving unit for driving the liquid crystal panel in a Z-inversion mode.

Description

TECHNICAL FIELD [0001] The present invention relates to a liquid crystal display (LCD)

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a liquid crystal display device, and more particularly to a liquid crystal display device using a Z-inversion method and a manufacturing method thereof.

The liquid crystal display device displays an image by adjusting the light transmittance of liquid crystal having dielectric anisotropy using an electric field.

To this end, a liquid crystal display device includes a liquid crystal panel in which liquid crystal cells are arranged in a matrix form, and a driving unit for driving the liquid crystal panel.

Such a liquid crystal display device drives the liquid crystal panel by an inversion driving method in order to prevent deterioration of liquid crystal and improve display quality. The inversion driving method includes a frame inversion system, a line inversion system, a column inversion system, a dot inversion system, or a Z-inversion system. (Z-Inversion System) system.

Among the inversion driving methods described above, the Z-inversion method is a method in which the thin film transistor TFT and the pixel electrode PXL are arranged in a staggered arrangement in which the left and right sides alternate along the data line DL A method of supplying a pixel signal in a column inversion manner to the lines. In other words, the Z-inversion method is an improved structure of a column-version method. In the circuit driving method, the column-inversion method is used. However, the direction of the thin film transistor (TFT) And the screen display is implemented in the same manner as the dot inversion system. Described in detail, the Z-inversion method is a method that can remarkably reduce power consumption while having an effect similar to the dot inversion method.

FIG. 1 is a view showing a part of a liquid crystal panel of a conventional liquid crystal display device using a Z-inversion method, and FIG. 2 is a cross-sectional view taken along line I-I ' Fig. FIG. 3 is a diagram illustrating waveforms of a parasitic capacitor formed between a data line and a pixel electrode in a conventional liquid crystal display device using a Z-inversion method. FIG. 3 shows waveforms of a parasitic capacitor Cdp The waveforms of the pixel of the odd-numbered data line and the pixel of the odd-numbered data line due to the asymmetry are shown.

1, the thin film transistor (TFT) 11 and the pixel electrode (PXL) 12, which are formed on the liquid crystal panel 10 of the liquid crystal display device using the Z-inversion method, The positions along the data lines DL are arranged in a zigzag shape alternating left and right sides. In other words, the thin film transistors (TFT) 11 and the pixel electrode (PXL) 12 included in the same column are alternately connected to the different data lines DL adjacent to each other on the horizontal line.

1, positive (+) or negative (-) polarity is generated by the parasitic capacitor Cdp formed between the data line DL and the pixel electrode PXL adjacent thereto. Therefore, in the liquid crystal panel 10, ) Occurs. Particularly, since the data line DL driven by the column-version method maintains the same polarity for one frame, the voltage deviation due to the parasitic capacitor Cdp also maintains the same polarity for one frame, The same failure occurs.

That is, the parasitic capacitor Cdp shown in FIG. 1 includes a first parasitic capacitor Cdp1 located between the data line DLk and the left pixel electrode P1 or P3, and a second parasitic capacitor Cdp1 between the data line DLk and the right The first and second parasitic capacitors Cdp1 and Cdp2 are connected between the data line DLk and the pixel electrode P 1 and the pixel electrode P 2 and P 4, , P2) are formed with a protective layer composed of an inorganic insulating film or an organic insulating film interposed therebetween.

Particularly, a capacitance deviation occurs between the first and second parasitic capacitors Cdp1 and Cdp2 as the left pixel electrode P1 of the data line DLk and the right pixel electrode P2 are charged with pixel signals of opposite polarities do. In other words, the voltage deviation between the data line DLk (-electrode) and the pixel electrode P1 (+ electrode) on the left side, which maintain the opposite polarities in FIG. 1, (- electrode) and the right pixel electrode P2 (- electrode). Therefore, since the first parasitic capacitor Cdp1 has a larger capacitance than the second parasitic capacitor Cdp1, a capacitance deviation occurs between the first and second parasitic capacitors Cdp1 and Cdp2.

The capacitance deviation between these parasitic capacitors Cdp1 and Cdp2 causes the data lines DLk to maintain the same polarity during one frame by the data lines DLk maintaining the same polarity for one frame, The pixel signal on the line DLk is distorted. That is, in the dot inversion method, the polarity of the data is changed during one frame, but since there is no change in the polarity of the data in the Z-inversion method, the bad phenomenon between the odd- It is getting worse.

The capacitance deviation between the parasitic capacitors Cdp1 and Cdp2 in the conventional liquid crystal display device described above is further increased by the overlay of the data line DLk and the pixel electrode PXL.

That is, in the ideal case, as shown in FIG. 2A, the data line DLk and the pixel electrodes P1 and P2 on both the left and right sides have the same interval, The capacitance variation of the parasitic capacitors caused by the parasitic capacitors does not occur.

However, in the conventional liquid crystal display device, since the data line DLk and the pixel electrodes P1 and P2 are formed using different masks in different layers, as shown in Fig. 2B, A distance difference is generated between the line and the pixel electrodes on both sides thereof, which causes a large capacitance variation of the parasitic capacitors on both the left and right sides.

In addition, the parasitic capacitors Cdp1 and Cdp2 in the conventional liquid crystal display device as described above are used as capacitors between the data lines and the pixel electrodes, or more specifically, active tails of the semiconductor layers formed at the lower ends of the data lines Capacitance between the left and right parasitic capacitors occurs due to the active tail of the semiconductor layer as a capacitor between the pixel electrode and the pixel electrode, and the aperture ratio is reduced by the active tail.

That is, in the conventional liquid crystal display device, the data line DLk is formed on the gate insulating layer on the lower substrate, and between the data line DLk and the gate insulating layer, the data line DLk The semiconductor layer ACT is formed along the length of the data line, which is generally longer than the width of the data line stacked thereon. Therefore, since the distance between the semiconductor layer ACT and the pixel electrode is smaller than the distance between the data line and the pixel electrode, and the substantial parasitic capacitor is formed between the end of the semiconductor layer (active tail) and the pixel electrode, The influence of the parasitic capacitor due to the distance between the semiconductor layer forming the smaller gap and the pixel electrode becomes larger.

In the conventional liquid crystal display device using the Z-inversion method as described above, the asymmetry of the parasitic capacitor Cdp occurs due to the overlay error between the data line and the pixel electrode, As shown in FIG. 3, there is a problem that a defect occurs due to the difference of Vrms between the odd-numbered pixel and the odd-numbered pixel on the same horizontal line. The active tail, There is a problem that the aperture ratio is reduced.

SUMMARY OF THE INVENTION The present invention has been made to solve the above-mentioned problems, and it is an object of the present invention to provide an organic light emitting display, which removes an active tail of a data line semiconductor layer formed at a lower end of a data line, And a protective film covering the data line and the data line semiconductor layer, and a method of manufacturing the same.

According to an aspect of the present invention, there is provided a liquid crystal display device including a plurality of pixels formed by intersection of gate lines and data lines, A liquid crystal panel in which intervals between pixel electrodes formed in left and right pixels of the data line are constant; And a driving unit for driving the liquid crystal panel in a Z-inversion mode.

According to an aspect of the present invention, there is provided a method of manufacturing a liquid crystal display device, including: forming a gate electrode and a common electrode on a substrate; Forming a semiconductor layer on top of the gate electrode with the gate insulating layer interposed therebetween; Forming a data line semiconductor layer on top of the common electrode with the gate insulating layer interposed therebetween; Forming a source electrode and a drain electrode on top of the semiconductor layer; Forming a data line on top of the data line semiconductor layer; Etching an end of the data line semiconductor layer to correspond to a position of an end of the data line; Forming a pixel electrode connected to the drain electrode with a protective layer interposed therebetween; And forming a data line protection film covering the data line and the data line semiconductor layer together with the pixel electrode.

According to the above-mentioned solution, the present invention provides the following effects.

That is, the present invention eliminates the active tail of the data line semiconductor layer formed at the lower end of the data line, and protects the data line and the data line, which are formed through the same process as the pixel electrode, By covering the semiconductor layer, it is possible to improve the defect caused by the difference of the parasitic capacitors in the odd-numbered pixels and the odd-numbered pixels in the same horizontal line, which may occur in the case of using the Z- .

Further, the present invention provides an effect of improving the aperture ratio by removing the active tail of the data line semiconductor layer deposited at the lower end of the data line.

FIG. 1 is a view showing a part of a liquid crystal panel of a conventional liquid crystal display device using a Z-inversion method. FIG.
FIG. 2 is an exemplary view for explaining a parasitic capacitor in a section cut along the line I-I 'shown in FIG. 1; FIG.
FIG. 3 is a diagram showing a waveform of a parasitic capacitor formed between a data line and a pixel electrode in a conventional liquid crystal display device using a Z-inversion method. FIG.
4 is an exemplary view showing a configuration of a liquid crystal display device according to the present invention.
5 is a view showing a part of a liquid crystal panel of a liquid crystal display device according to the present invention.
6 is a cross-sectional view taken along line A-A 'of FIG. 5;
7A to 7F are schematic cross-sectional views illustrating a method of manufacturing a liquid crystal display device according to the present invention.

Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings.

4 is an exemplary view showing a configuration of a liquid crystal display device according to the present invention. 5 is a view showing a part of a liquid crystal panel of a liquid crystal display device according to the present invention, and shows a part of a liquid crystal panel of a liquid crystal display device using a Z-inversion method as shown in Fig. 4 .

4, the liquid crystal display according to the present invention includes a liquid crystal panel 100 having a matrix of liquid crystal cells, a gate driver 200 for driving the gate lines GL1 to GLn of the liquid crystal panel, A data driver 300 for driving the data lines DL1 to DLm, and a timing controller 400 for controlling the gate driver and the data driver.

First, the liquid crystal panel 100 includes a thin film transistor TFT formed for each region defined by the intersection of the gate lines GL1 through GLn 110 and the data lines DL1 through DLm + 1 120, And a liquid crystal cell 140 including a liquid crystal cell (LCD).

The thin film transistor TFT supplies a pixel signal from the data lines DL1 to DLm 120 to the pixel electrode (PXL) 140 in response to a scan signal from the gate line (GL) The pixel electrode (PXL) 140 controls the transmittance of light by driving the liquid crystal located between the pixel electrode (PXL) 140 and the common electrode (BLSP) 150 in response to the pixel signal.

In particular, the thin film transistor TFT and the pixel electrode PXL are arranged in a zigzag shape along the data line DL, the positions of which alternate left and right sides. That is, the thin film transistors TFT and the pixel electrode PXL included in the same column are alternately connected to the different data lines DL adjacent to each other on the horizontal line.

For example, in FIG. 4, the thin film transistor TFT and the pixel electrode PXL of the odd-numbered horizontal lines connected to the odd-numbered gate lines GL1, GL3, GL5, (M is an even number) data lines DL1 to DLm, respectively. Accordingly, the pixel electrode PXL of the odd-numbered horizontal line charges the pixel signal from the data line DL adjacent to the left side through the thin film transistor TFT.

On the other hand, the thin film transistor TFT and the pixel electrode PXL of the odd-numbered horizontal line connected to the odd-numbered gate lines GL2, GL4, GL6, (DL2 to DLm), respectively. Accordingly, the pixel electrode PXL of the odd-numbered horizontal line charges the pixel signal from the adjacent right-side data line through the thin film transistor TFT.

Next, the timing controller 400 generates timing control signals for controlling the gate driver 200 and the data driver 300, and supplies a pixel data signal to the data driver 300. The gate timing control signals generated by the timing controller 400 include a gate start pulse GSP, a gate shift clock signal GSC, a gate output enable signal GOE, and the like. The data timing control signals generated by the timing controller 400 include a source start pulse SSP, a source shift clock signal SSC, a source output enable signal SOE, a polarity control signal POL, .

Next, the gate driver 200 sequentially supplies the scan signals to the gate lines GL1 to GLn using the gate timing control signals. Thus, the thin film transistors (TFT) are driven in units of horizontal lines in response to the scan signals.

Finally, the data driver 300 converts the input pixel data into analog pixel signals, and supplies the pixel signals of one horizontal line to the data lines DL1 to DLm . In this case, the data driver 300 converts pixel data into pixel signals using gamma voltages supplied from a gamma voltage generator (not shown).

The data driver 300 supplies a pixel signal in a column-by-column version manner so that the pixel signals supplied to the data lines DL1 to DLm have a polarity opposite to that of the adjacent data lines DL, To be inverted. In other words, the data driver 300 supplies the pixel signals of opposite polarities to the odd data lines DL1, DL3, ... and the even data lines DL2, DL4, ..., The polarities of the pixel signals supplied to the pixels DL1 to DLm + 1 are inverted frame by frame.

In this case, since the pixel electrode (PXL) 140 is arranged in a staggered manner with respect to the data lines DL1 to DLm to which pixel signals are supplied in a column-version manner, the liquid crystal cells including the pixel electrode And is driven in a dot-inversion manner.

Accordingly, in the liquid crystal display according to the present invention, the image quality is improved by the liquid crystal cells PXL driven by the dot inversion method, and the data driver 300 supplies the pixel signals in the column inversion mode, The power consumption can be remarkably reduced as compared with the case of supplying the pixel signal in the version system.

In the liquid crystal panel 100 shown in FIG. 4, the active tail of the data line semiconductor layer formed at the lower end of each data line is removed, and the same material as the pixel electrode is formed at the upper end of the data line, By forming the line protection film, even if there occurs a gap between the data lines and the pixel electrodes on the left and right sides of the data line, the parasitic capacitor does not deviate.

This will be described in detail below with reference to Figs. 5 and 6. Fig.

6 is a cross-sectional view taken along the line A-A 'shown in FIG.

The parasitic capacitor Cdp is generated between the data line (DL) 120 and the pixel electrode (PXL) 140 as shown in FIG. 5 also in the liquid crystal panel of the liquid crystal display according to the present invention.

 The parasitic capacitor Cdp includes a first parasitic capacitor Cdp1 positioned between the data line DL and the left pixel electrode P1 and a first parasitic capacitor Cdp1 between the data line DL and the right pixel electrode P2. And a second parasitic capacitor (Cdp2) located in the second parasitic capacitor.

On the other hand, in the liquid crystal panel of the liquid crystal display device according to the present invention, the same parasitic capacitor is formed even if the position of the data line is shifted in either one of the right and left pixel electrodes.

6, a common electrode BLSP (blue light-emitting diode) (BLSP) is formed on the lower substrate 102. The common electrode BLSP is formed on the data line portion of the liquid crystal panel of the liquid crystal display according to the present invention. 150, a gate insulating layer 104 is deposited on top of the gate insulating layer, and a data line semiconductor layer 131 is formed on the gate insulating layer.

A data line 120 is formed on the top of the data line semiconductor layer 131. A data line protection layer 149 is formed on the top of the data line 120 and is formed of the same material as the pixel electrode 140, Respectively. Here, the data line protection film 149 is formed so as to completely cover the data line 120 and the data line semiconductor layer 131.

In addition, the data line semiconductor layer 131 is formed in a state where an active tail protruding from the end of the data line is removed.

Even if the position of the data line 120 formed by the mask different from the mask forming the pixel electrode 140 is shifted toward the pixel electrodes on both sides thereof, the pixel electrode 140 and the data line 120 Since the parasitic capacitor Cdp formed between the data line protective film 131 and the pixel electrode 140 formed through the same process as the pixel electrode 140 is a parasitic capacitor Cdp between the data line and the pixel electrode 140, No capacitance variation occurs in the parasitic capacitors formed on both the left and right sides thereof.

That is, as described above, even if the positions of the data lines are changed, the data line protection film 149 formed together with the pixel electrodes through the same mask is formed to have the same interval as the pixel electrodes formed on both the left and right sides of the data line In this case, since the parasitic capacitor between the data line 120 and the pixel electrode 140 is a parasitic capacitor between the data line protective film 139 covering the data line and the pixel electrode 140, No capacitance variation occurs in the parasitic capacitors between the pixel electrodes formed on the left and right sides thereof.

Particularly, in the present invention, the data line semiconductor layer 131 formed at the lower end of the data line 120 is formed in a state where the active tail protruding from the end of the data line is removed, The interval between the end of the data line protective film 149 and the pixel electrodes 140 on both the left and right sides of the data line protective film 149 is the same .

In addition, since the active tail of the data line semiconductor layer 131 is etched as described above, the present invention is characterized in that the aperture ratio, which has been reduced by the active tail, can be increased.

That is, the present invention uses a Z-inversion driving method. In a liquid crystal display device using a TN structure (twisted nematic), a data line 120 is formed on an upper part of a data line semiconductor layer 131, The active tail of the data line portion is removed using a tone mask (HTM: Half tone mask), and a data line protection film 149 using transparent electrodes is formed at the top of the data line.

Hereinafter, a method for manufacturing a liquid crystal display device according to the present invention as described above will be described in detail with reference to FIGS. 7A to 7F.

FIGS. 7A to 7F are schematic cross-sectional views illustrating a method of manufacturing a liquid crystal display device according to the present invention, which illustrates a manufacturing process of the liquid crystal display device shown in FIGS. Particularly, Figs. 7A to 7F show a cross section taken along the line A-A 'shown in Fig. That is, FIGS. 7A to 7F show cross-sectional structures of two pixels formed on the left and right sides of one data line DL shown in FIG.

First, as can be seen from Fig. 7A, the gate electrode 111 is formed on the substrate 102. Then, as shown in Fig.

The gate electrode 111 is formed by depositing a predetermined metal material on the substrate 102, depositing a photoresist on a predetermined metal material, and then sequentially performing exposure, development and etching processes using a mask Called mask process.

Although not shown, a gate line 110 connected to the gate electrode 111 is formed at the same time in the step of forming the gate electrode 111. Here, the gate electrode 111 may be formed by depositing one metal material, or may be formed by depositing two metal materials.

In addition, the common electrode 150 is deposited on the substrate 102, and in particular, the common electrode 150 is formed in the data line portion where the data line is formed.

7B, a gate insulating layer 104 is deposited on the entire surface of the substrate 102 including the gate electrode 111. Then, as shown in FIG. A semiconductor layer material for forming the semiconductor layer 130 and the data line semiconductor layer 131 is deposited on the top of the gate insulating layer 104 and then etched by a mask to form the semiconductor layer 130 and the data line semiconductor layer 131. [ (131a) is formed. Here, the semiconductor layer 130 is formed in the thin film transistor, and the data line semiconductor layer 131 is formed in the data line portion, and the two layers are formed of the same material.

After the electrode material for forming the source electrode 121 and the drain electrode 141 and the data line 120 for forming the thin film transistor is deposited on the top of the semiconductor layer 130 and the data line semiconductor layer 131 The source electrode 121, the drain electrode 141, and the data line 120 are formed by etching by the mask.

Here, the gate insulating layer 104 may be formed using a Plasma Enhanced Chemical Vapor Deposition (PECVD) method or the like.

Meanwhile, the data line semiconductor layer 131a formed in the above process is a data line semiconductor layer in which the active tail protruding from the end of the data line 120 is not removed.

Next, as shown in FIG. 7C, a protective layer (PAS) 106 is deposited on the entire surface of the substrate including the source, drain and data lines, and then the photoresist 108 is applied. Thereafter, a protective layer 106 of the drain electrode 141 is exposed through a drain hole as shown in FIG. 7C by applying a halftone mask (HTM) to the data line portion and exposing and developing the exposed portion , And part of the photoresist of the data line portion is etched.

7D, the drain electrode 141 is exposed by etching the drain hole using dry etching (D / E), and the photoresist remaining in the data line portion by the halftone mask is removed Thereby exposing the protective layer 106 formed in the data line portion.

7E, by performing dry etching (D / E) on the remaining photoresist, a portion of the data line semiconductor layer 131a formed at the lower end of the data line, which protrudes from the end of the data line Remove the Active Tail part.

At this time, the drain electrode 141 is already exposed through the drain hole, and the data line 120 is formed at the upper end of the data line semiconductor layer 131. However, the drain line is formed by copper Only the active tail portion protruding from the end of the data line 120 can be etched and removed because the data line 141 and the data line 120 are not etched.

Finally, as shown in FIG. 7F, after the remaining photoresist is removed, the pixel electrode material is applied over the entire surface of the substrate. Thereafter, the pixel electrode 140 and the data line protection film 149 are formed using a mask (not shown).

Here, the pixel electrode material is a transparent electrode material (ITO), and light can be transmitted by the pixel electrode formed by the pixel electrode material.

In addition, since the data line protection film 149 is formed by the transparent pixel electrode material instead of the opaque active tail in the data line portion, an opening as much as the active tail can be additionally secured.

In addition, the data line protection film 149 covering the data lines can perform a function of protecting the data lines 120.

As described above, since the pixel electrode 140 and the data line protection film 149 are formed through the same process using the same material and the same mask, the edge of the pixel electrode 140 and the data line protection film 149 are always kept at the same interval. Therefore, the gap between the pixel electrodes 140 formed on both the left and right sides of the data line 120 and the end of the data line protective film 149 can be kept constant at all times.

Particularly, since the end of the data line protection film 149 is formed in the active tail portion including the data line 120 and the data line semiconductor layer 131 as shown in FIG. 7F, the data line protection film 149 Can be always formed at the same position.

That is, in the present invention, the parasitic capacitor Cdp formed between the data line 120 and the pixel electrode 140 is a capacitor formed between the end of the data line protective film 149 and the pixel electrode 140 And the positions of both ends of the data line protection film 149 are formed at the same intervals as the pixel electrodes formed on both the left and right sides of the data line.

Therefore, even if the position of the data line 120 is changed to some extent within the error range, the gap between the end of the data line protective film 149 and the pixel electrodes 140 formed on both the left and right sides thereof can be always kept constant The size of the parasitic capacitors formed on both sides of the data line 120 at the boundary thereof can always be kept the same.

That is, in the liquid crystal display device using the Z-inversion driving method as described above, the active tail of the data line semiconductor layer 131 formed at the lower end of the data line 120 The data line protective film 149 is formed on the data line at the upper end of the data line through the same material and the same process as the pixel electrode so that the interval between the data line protective film 149 and the pixel electrodes 140 on both the left and right sides thereof is made constant So that it is possible to prevent defects due to capacitance variations of the parasitic capacitors, which can be generated at two intervals different from each other.

In other words, unlike the dot inversion driving method, the liquid crystal display device using the Z-inversion driving method is different from the dot inversion driving method in that the parasitic capacitor Cdp between the data line and the left and right pixel electrodes due to an overlay error between the data line and the pixel electrode, (Parasitic luminance difference difference) may occur due to the difference between the parasitic capacitors and the parasitic capacitors. Such parasitic capacitors may be formed in the data lines, more specifically, the active tails of the data line semiconductor layers formed at the lower ends of the data lines, The active tail removal structure of the data line semiconductor layer 131 is applied to improve the deviation of the left and right parasitic capacitors according to the overlay error between the data line and the pixel electrode, 120 are formed by using the same material as the pixel electrode, And the protective film 149 protects the left and right parasitic capacitors.

According to this, the deviation of the left and right parasitic capacitors of the data line 120 can be solved, and even / odd defects can be solved.

Further, the present invention is characterized in that the aperture ratio can be improved by removing the active tail (the aperture ratio of the LM185 is expected to improve by about 2.0%).

It will be understood by those skilled in the art that the present invention may be embodied in other specific forms without departing from the spirit or essential characteristics thereof. It is therefore to be understood that the above-described embodiments are illustrative in all aspects and not restrictive. The scope of the present invention is defined by the appended claims rather than the detailed description and all changes or modifications derived from the meaning and scope of the claims and their equivalents are to be construed as being included within the scope of the present invention do.

100: liquid crystal panel 102: substrate
104: gate insulating layer 106: protective layer
108: photoresist 110: gate line
111: gate electrode 120: data line
121: source 130: semiconductor layer
131: Data line semiconductor layer 140: Pixel electrode
141: drain 149: data line protection film
150: common electrode

Claims (12)

And a plurality of pixels formed by intersection of the gate lines and the data lines, wherein a distance between the end of the data line protective film covering each of the data lines and the pixel electrodes formed on the left and right pixels of the data line is constant A liquid crystal panel formed thereon; And
And a driving unit for driving the liquid crystal panel in a Z-inversion mode,
Wherein the data line protection film is formed by a process of manufacturing the pixel electrode using the same material as the pixel electrode. The method according to claim 1,
In the liquid crystal panel,
Wherein the thin film transistors and the pixel electrodes included in the pixels of the same column are formed so as to be alternately connected to different data lines adjacent to each other in the horizontal line. Device. The method according to claim 1,
And an active tail of a data line semiconductor layer formed at a lower end of each of the data lines is removed. delete The method according to claim 1,
In the liquid crystal panel,
Board;
A gate electrode formed on the substrate;
A common electrode formed on the same layer as the gate electrode;
A gate insulating layer formed on the gate electrode and the top of the common electrode;
A semiconductor layer formed on top of the gate electrode with the gate insulating layer interposed therebetween;
A data line semiconductor layer formed on top of the common electrode with the gate insulating layer interposed therebetween, using the same material as the semiconductor layer;
A source electrode and a drain electrode formed on top of the semiconductor layer;
A data line formed on the data line semiconductor layer;
The pixel electrode being connected to the drain electrode with a protective layer interposed therebetween; And
And the data line protection film formed on an upper end of the data line. 6. The method of claim 5,
And an end of the data line semiconductor layer is etched to correspond to a position of an end of the data line. delete The method according to claim 1,
Wherein the data line protection film and the pixel electrode are formed of transparent electrodes. Forming a gate electrode and a common electrode on a substrate;
Forming a semiconductor layer on top of the gate electrode with a gate insulating layer interposed therebetween;
Forming a data line semiconductor layer on top of the common electrode with the gate insulating layer interposed therebetween;
Forming a source electrode and a drain electrode on top of the semiconductor layer;
Forming a data line on top of the data line semiconductor layer;
Etching an end of the data line semiconductor layer to correspond to a position of an end of the data line;
Forming a pixel electrode connected to the drain electrode with a protective layer interposed therebetween; And
And forming a data line protection film covering the data line and the data line semiconductor layer together with the pixel electrode,
Wherein the data line protective film is formed by a process of manufacturing the pixel electrode using the same material as the pixel electrode. 10. The method of claim 9,
Wherein etching the end of the semiconductor layer comprises:
Depositing a photoresist on top of the data line after forming the data line;
Applying a halftone mask (HTM) to a data line portion on which the data line is formed to expose and develop the data line portion;
Exposing the drain electrode using dry etching and removing the photoresist remaining in the data line portion by the halftone mask to expose the protective layer formed in the data line portion; And
And etching the active tail portion protruding from the end of the data line among the data line semiconductor layers formed at the lower end of the data line by performing dry etching on the photoresist. 11. The method of claim 10,
Wherein the data line protection film is deposited so as to cover an upper portion of the data line and a portion where the active tail is removed. 10. The method of claim 9,
Wherein an interval between the end of the data line protective film and the pixel electrodes formed on both sides of the data line is kept constant.

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