KR20040049569A - Liquid crystal display panel - Google Patents

Abstract

PURPOSE: A liquid crystal panel is provided to reduce the capacity of a parasite capacitor between a data line and a pixel electrode. CONSTITUTION: Liquid crystal cells(32) is formed at every region defined by crossing gate lines(GLi, GLi+1) and data lines(DLk-1 to DLk+1). A dummy pattern(30) is overlapped with both sides of the pixel electrode(P1 to P4) for reducing the parasite capacitor(Cdp) between the pixel electrode(P1 to P4) and the data lines(DLk-1 to DLk+1) of the liquid crystal cell(32). The respective liquid crystal cells(32) include a TFT(Thin Film Transistor) and a pixel electrode(P).

Description

Liquid crystal display panel {LIQUID CRYSTAL DISPLAY PANEL}

The present invention relates to a liquid crystal display device, and more particularly, to a liquid crystal display panel capable of minimizing the parasitic capacitor capacity between the pixel electrode and the data line.

In general, a liquid crystal display device displays an image by adjusting the light transmittance of a liquid crystal having dielectric anisotropy using an electric field. To this end, the liquid crystal display includes a liquid crystal display panel in which liquid crystal cells are arranged in a matrix, and a driving circuit for driving the liquid crystal display panel.

The liquid crystal display device drives the liquid crystal display panel by an inversion driving method to prevent deterioration of the liquid crystal and to improve display quality. As the inversion driving method, a frame inversion system, a line (column) inversion system, and a dot inversion system are used.

In particular, the dot inversion driving method of the inversion driving method causes the polarities of the liquid crystal cells to be opposite polarities to all adjacent liquid crystal cells in the horizontal and vertical directions, and are inverted every frame. This dot inversion driving method provides an image with superior image quality compared to other inversion methods by causing the flicker generated between adjacent liquid crystal cells in the vertical and horizontal directions to cancel each other.

However, in the dot inversion driving method, since the polarity of the pixel signal supplied to the data lines in the data driver must be reversed in the horizontal and vertical directions, the variation amount of the pixel signal, that is, the frequency of the pixel signal is larger than that of other inversion methods. Because of the large power consumption has the disadvantage.

In order to solve the large power consumption problem of the dot inversion driving method, as shown in FIG. 1, a liquid crystal display device capable of driving data lines in a column inversion method while driving liquid crystal cells in a dot inversion method has been proposed. There is a bar.

1 includes a liquid crystal display panel 12 having a liquid crystal cell matrix, a gate driver 14 for driving gate lines GL1 to GLn of the liquid crystal display panel 12, and a liquid crystal display. A data driver 16 for driving the data lines DL1 to DLm + 1 of the panel 12 and a timing controller 18 for controlling the gate driver 14 and the data driver 16 are provided.

The liquid crystal display panel 12 includes a liquid crystal cell including a thin film transistor TFT formed at each region defined by the intersection of the gate lines GL1 to GLn and the data lines DL1 to DLm + 1, and a pixel electrode PXL. It is provided. The thin film transistor TFT supplies the pixel signal from the data line DL to the pixel electrode PXL in response to the scan signal from the gate line GL. The pixel electrode PXL adjusts the light transmittance by driving a liquid crystal positioned between the common electrode (not shown) in response to the pixel signal. The liquid crystal cell is alternately connected to adjacent data lines DL along the vertical direction through the thin film transistor TFT.

For example, the liquid crystal cell of the odd horizontal line connected to the odd gate lines GL1, GL3, GL5, ... is connected to the data line DL adjacent to the left to receive the pixel signal. On the other hand, the liquid crystal cell of the even-numbered horizontal line connected to the even-numbered gate lines GL2, GL4, GL6, ... is connected to the data line DL adjacent to the right to receive the pixel signal.

The timing controller 18 generates timing control signals for controlling the gate driver 14 and the data driver 16, and supplies the pixel data signal to the data driver 16. The gate timing control signals generated by the timing controller 18 include a gate start pulse GSP, a gate shift clock signal GSC, a gate output enable signal GOE, and the like. The data timing control signals generated by the timing controller 18 include a source start pulse SSP, a source shift clock signal SSC, a source output enable signal SOE, a polarity control signal POL, and the like.

The gate driver 14 sequentially supplies scan signals to the gate lines GL1 to GLn using the gate timing control signals. Accordingly, the gate driver 14 causes the thin film transistors TFT to be driven in units of horizontal lines in response to the scan signal.

The data driver 16 converts the input pixel data into an analog pixel signal and outputs one horizontal line of pixel signals for each horizontal period during which the scan signal is supplied to the gate line GL. The data lines DL1 to DLm + 1 To feed. In this case, the data driver 16 converts the pixel data into a pixel signal using gamma voltages supplied from a gamma voltage generator (not shown).

The data driver 16 supplies pixel signals in a column inversion manner so that the pixel signals supplied to each of the data lines DL1 to DLm + 1 have polarities opposite to those of the adjacent data lines DL. Invert frame by frame. For example, the data driver 16 supplies pixel signals of opposite polarities to the odd data lines DL1, DL3, ... and even data lines DL2, DL4, ..., and the data. The polarity of the pixel signal supplied to the lines DL1 to DLm + 1 is inverted in units of frames.

In this case, since the pixel electrode PXL is arranged in a zigzag shape based on the data lines DL1 to DLm + 1 to which the pixel signal is supplied in a column inversion manner, the liquid crystal cells including the pixel electrode PXL are dots. It is driven in an inversion manner.

In particular, the data driver 16 alternately outputs an output channel of the pixel signal every horizontal period in order to supply an accurate pixel signal to the pixel electrode PXL arranged in a zigzag pattern along the data lines DL1 to DLm + 1. Will change. In detail, when the pixel signal is supplied to the liquid crystal cells connected to the right side of the data lines DL1 to DLm + 1, the data driver 16 may supply m number of m to the first to mth data lines DL1 to DLm. The effective pixel signal is supplied with a blank signal to the m + 1th data line DLm + 1. On the other hand, when supplying a pixel signal to the liquid crystal cells connected to the left side of the data lines DL1 to DLm + 1, the data driver 16 shifts the m effective pixel signals to the right by one channel to the second to The m + 1 th data lines DL2 to DLm + 1 are supplied, and a blank signal is supplied to the first data line DL1. Here, the blank signal means a don't care signal.

The liquid crystal display device improves image quality by liquid crystal cells driven in a dot inversion method, and the data driver 16 supplies pixel signals in a column inversion method, so that the pixel signals are supplied in a dot inversion method. The power consumption can be reduced.

However, in the liquid crystal display panel 12 illustrated in FIG. 1, a positive polarity (+) or a negative polarity (−) is formed by a parasitic capacitor Cdp formed between the data line DL and the pixel electrode PXL adjacent thereto. Voltage deviation occurs. In particular, as the data line DL driven in the column inversion method maintains the same polarity for one frame, the voltage deviation caused by the parasitic capacitor Cdp also maintains the same polarity for one frame, thereby causing vertical crosstalk. do. The cause of such vertical crosstalk will be described in detail with reference to FIGS. 2 and 3.

FIG. 2 is a view illustrating a portion of the liquid crystal display panel illustrated in FIG. 1, and FIG. 3 is a cross-sectional view illustrating a cut surface of the liquid crystal display panel taken along the line II ′ of FIG. 2.

The parasitic capacitor Cdp illustrated in FIG. 2 includes a first parasitic capacitor Cdp1 positioned between the data line DLk and the left pixel electrode P1 or P3, and the data line DLk and the right pixel electrode. The second parasitic capacitor Cdp2 located between (P2 or P4) is provided. As shown in FIG. 3, the first and second parasitic capacitors Cdp1 and Cdp2 have a passivation layer 26 in which the data line DLk and the pixel electrodes P1 and P2 are made of an inorganic insulating film or an organic insulating film. As it is located. Here, the data line DLk is formed on the gate insulating film 22 on the lower substrate 20, and between the data line DLk and the gate insulating film 22 along the data line DLk along the semiconductor layer ( 24) is further formed.

Due to the coupling effect caused by the first and second parasitic capacitors Cdp1 and Cdp2, the pixel signals supplied to the data line DLk and the pixel electrodes P1 and P2 are distorted, thereby degrading the display quality of the liquid crystal display panel. . In particular, a capacitance variation occurs between the first and second parasitic capacitors Cdp1 and Cdp2 as the left pixel electrode P1 and the right pixel electrode P2 of the data line DLk charge pixel signals having opposite polarities. do. The capacitance deviation between the parasitic capacitors Cdp1 and Cdp2 interferes with the data line DLk by maintaining the same polarity for one frame by the data line DLk having the same polarity for one frame. The pixel signal on DLk is distorted. The distorted pixel signal on the data line DLk is induced to the adjacent pixel electrodes P1 and P2 to generate vertical crosstalk, thereby lowering display quality.

In addition, the data line DLk and the pixel electrodes P1 and P2 are disposed at a predetermined distance to reduce the capacitance of the parasitic capacitor Cdp. As a result, light leakage is generated between the data line DLk and the pixel electrodes P1 and P2 via the liquid crystal not driven from the backlight. In particular, the amount of light leakage between the data line DLk and the pixel electrodes P1 and P2 appears in proportion to the capacitance of the parasitic capacitors Cdp1 and Cdp2. Accordingly, the amount of light leakage through them is also different due to the capacitance variation between the first and second parasitic capacitors Cdp1 and Cdp2. Due to the asymmetrical light leakage caused by the first and second parasitic capacitors Cdp1 and Cdp2, the display quality of the liquid crystal display panel is further degraded.

Accordingly, an object of the present invention is to provide a liquid crystal display panel capable of reducing parasitic capacitor capacitance between data lines and pixel electrodes.

Another object of the present invention is to provide a liquid crystal display panel capable of reducing parasitic capacitor capacitance variations between data lines and left and right pixel electrodes.

Another object of the present invention is to provide a liquid crystal display panel which can minimize the amount of non-danged light leakage between the data line and the left and right pixel electrodes.

1 is a view showing a conventional liquid crystal display device.

FIG. 2 is a plan view of a portion of the liquid crystal display panel illustrated in FIG. 1. FIG.

3 is a cross-sectional view illustrating a cut surface of the liquid crystal display panel along the line II ′ of FIG. 2.

4 is a plan view of a portion of a liquid crystal display panel according to a first exemplary embodiment of the present invention.

FIG. 5 is a cross-sectional view illustrating a cut surface of the liquid crystal display panel taken along the line II-II ′ of FIG. 4.

FIG. 6 is an equivalent circuit diagram for the parasitic capacitor shown in FIG. 5. FIG.

7 is a plan view illustrating a portion of a liquid crystal display panel according to a second exemplary embodiment of the present invention.

8 is a plan view illustrating a portion of a liquid crystal display panel according to a third exemplary embodiment of the present invention.

FIG. 9 is a cross-sectional view of a liquid crystal display panel taken along a line II-II 'shown in FIGS. 7 and 8.

FIG. 10 is a circuit diagram modeling the parasitic capacitor shown in FIG. 9. FIG.

11A and 11B are input and output waveform diagrams of the modeling circuit shown in FIG. 10.

12 is a plan view illustrating a portion of a liquid crystal display panel according to a fourth exemplary embodiment of the present invention.

FIG. 13 is a cross-sectional view illustrating a cut surface of the liquid crystal display panel taken along the line III-III ′ of FIG. 12.

<Short description of the symbols in the drawings>

12 liquid crystal display panel 14 gate driver

16: data driver 18: timing controller

20, 40, 60, 100: lower substrate 22, 42, 62, 102: gate insulating film

24, 44, 64, 104: semiconductor layers 26, 46, 66, 106: protective film

30, 50, 80, 90: dummy pattern 52: constant voltage source

70, 110: upper substrate 72, 112: black matrix

74, 114: color filter 76, 116: common electrode

GL1 to GLn, GLi-1 to GLi + 1: gate line

DL1 to DLm, DLk, DLk + 1: data line

PXL, P1 to P4: Pixel electrode TFT: Thin film transistor

Cdp, C1 to C3: parasitic capacitors 32, 52, 82, 92: liquid crystal cell

In order to achieve the above object, a liquid crystal display panel according to the present invention includes a thin film transistor formed at an intersection of gate lines and data lines, liquid crystal cells including pixel electrodes connected to the thin film transistor, data lines and pixels. A first parasitic capacitor formed by a dummy pattern formed between the electrodes and a pixel electrode formed between the data line and the first insulating layer; A second parasitic capacitor formed by a dummy pattern formed between the pixel electrode and the second insulating layer; And a third parasitic capacitor formed by a dummy pattern formed with the data line and the third insulating layer interposed therebetween.

The dummy pattern is formed of a gate metal together with a gate line.

The dummy pattern is parallel to the data line and is partially overlapped with one side of the pixel electrode and the second insulating layer interposed therebetween.

The dummy pattern may be parallel to the data line and may be completely overlapped with one side of the pixel electrode and the second insulating layer therebetween.

The dummy pattern may indirectly face the common electrode for supplying a reference voltage to the liquid crystal cell and the pixel electrode.

The dummy pattern may be formed independently for each liquid crystal cell.

The dummy pattern is connected to a gate line.

The dummy pattern may be connected to a previous gate line.

The dummy pattern is connected to a current gate line.

Further comprising a common line for supplying a specific voltage to the dummy pattern.

The common line may be configured to supply one of a gate low voltage, a ground voltage, and a reference voltage supplied to a common electrode included in the liquid crystal cell.

The common line is formed to be parallel to the gate line, and partially overlapped with the pixel electrode adjacent to the gate line and the second insulating layer interposed therebetween.

The first insulating layer includes a passivation layer formed between the data line and the pixel electrode, the second insulating layer includes a passivation layer and a gate insulating layer formed between the pixel electrode and the dummy pattern, and the third insulating layer includes a dummy pattern and And a gate insulating film formed between the data lines.

The liquid crystal cells may include a first horizontal line including a data line adjacent to the left side and liquid crystal cells connected through a thin film transistor; And a second horizontal line including liquid crystal cells connected through the data line adjacent to the right and the thin film transistor.

In the first horizontal line, the data line and the right pixel electrode thereof charge pixel signals having the same polarity, and the left pixel electrode thereof have the opposite polarity pixel signals, and in the second horizontal line, the data line and the left pixel electrode have the same pixel signal. The pixel signal of polarity and the pixel electrode on the right thereof are charged with the pixel signal of opposite polarity.

The first horizontal line and the second horizontal line are alternately arranged in units of at least one horizontal line.

Other objects and advantages of the present invention in addition to the above objects will become apparent from the detailed description of the embodiments with reference to the accompanying drawings.

Hereinafter, preferred embodiments of the present invention will be described with reference to FIGS. 4 to 13.

4 is a plan view illustrating a portion of a liquid crystal display panel according to a first exemplary embodiment of the present invention, and FIG. 5 is a cross-sectional view illustrating a cut surface of the liquid crystal display panel taken along line II-II ′ of FIG. 4.

The liquid crystal display panel illustrated in FIG. 4 includes liquid crystal cells 32 and liquid crystal cells 32 formed at respective regions defined by intersections of the gate lines GLi and GLi + 1 and the data lines DLk-1 to DLk + 1. In order to reduce the parasitic capacitor Cdp between the pixel electrodes P1 to P4 and the data lines DLk-1 to DLk + 1, the dummy pattern 30 is formed to be in contact with both sides of the pixel electrodes P1 to P4. do.

Each of the liquid crystal cells 32 includes a thin film transistor TFT and a pixel electrode P. The thin film transistor TFT supplies the pixel signal from the data line DL to the pixel electrode P in response to the scan signal from the gate line GL. The pixel electrode P drives the liquid crystal positioned between the common electrode (not shown) in response to the supplied pixel signal. Accordingly, the liquid crystal cells 32 display an image by adjusting the light transmittance according to the driving of the liquid crystal.

In particular, the liquid crystal cells 32 are alternately connected to adjacent data lines DLk-1 to DLk + 1 in the vertical direction for dot inversion driving. In other words, the liquid crystal display panel includes a first horizontal line HL1 composed of liquid crystal cells 32 connected to data lines DLk-1 and DLk adjacent to the left, and data lines DLk and DLk adjacent to the right. And a second horizontal line HL2 composed of liquid crystal cells 32 connected to +1). The first horizontal line HL1 and the second horizontal line HL2 are alternately arranged in units of one horizontal line when dot inversion driving is performed. For example, as illustrated in FIG. 4, when the pixel signals having polarities are inverted for each of the data lines DLk-1 to DLk + 1, the liquid crystal cells 32 are adjacent to the liquid crystal cells 32 that are adjacent to each other vertically, vertically, and horizontally. Since pixel signals having opposite polarities are supplied to each other, the liquid crystal cells 32 may perform dot inversion driving.

In contrast, in the case of inversion driving of 2 dots or 3 dots or more, the first horizontal line HL1 and the second horizontal line HL2 are alternately arranged in units of 2 or 3 or more horizontal lines.

The dummy pattern 30 is formed to be parallel to the data line DL and the pixel electrode P, for example, without overlapping the data line DL and overlapping with one side of the pixel electrode P. In detail, the dummy pattern 30 is formed to overlap one side of the pixel electrodes P1 and P2 with the passivation layer 46 and the gate insulating layer 42 interposed therebetween, as illustrated in FIG. 5. The dummy pattern 30 is formed side by side without overlap with the data line DLk and the gate insulating layer 42 therebetween. The dummy pattern 30 is formed of a gate metal together with the gate electrode of the gate line GL and the thin film transistor TFT on the lower substrate 40, and is formed independently for each liquid crystal cell 32 to maintain a floating state. do. A semiconductor layer 44 along the data line DLk is further formed between the data line DLk and the gate insulating layer 42.

The dummy pattern 30 can reduce the capacitance of the parasitic capacitor Cdp inversely proportional to the interval by making the distance between the data line DLk and the pixel electrodes P1 and P2 relatively longer.

For example, in the conventional liquid crystal display panel illustrated in FIG. 3, when the distance between the data line DLk and the pixel electrodes P1 and P2 is increased to reduce the capacitance of the parasitic capacitor CDp, The amount of light leakage through the pixel electrodes P1 and P2 increases. For this reason, in the conventional liquid crystal display panel, the distance between the data lines DLk and the pixel electrodes P1 and P2 is limited to about 3.5 μm or less which can block light leakage with the black matrix of the upper substrate.

On the other hand, when the dummy pattern 30 is formed as in the liquid crystal display panel illustrated in FIG. 5, light leakage may be blocked by the dummy pattern 30, so that the data line DLk and the pixel electrodes P1 and P2 may be separated. The interval can be increased. For example, the distance between the light shielding pattern 30 and the data line DLk is set to 3 μm, which is such that light leakage can be blocked by a black matrix (not shown) of the upper substrate, and the width of the light blocking pattern 30 is 5.5 μm, when the overlap width of the light blocking pattern 30 and the pixel electrodes P1 and P2 is set to 2.5 μm, the distance between the data line DLk and the pixel electrodes P1 and P2 may be increased to about 6 μm. do. Since the gap between the data line DLk and the pixel electrodes P1 and P2 is relatively increased by the dummy pattern 30, the parasitic capacitor Cdp may be reduced.

Specifically, each of the parasitic capacitors Cdp formed between the data line DLk and the adjacent pixel electrodes P1 and P2 by the dummy pattern 30 has the passivation layer 46 therebetween as shown in FIG. 5. The first parasitic capacitor Cdp1 formed by the pixel electrodes P1 and P2 and the data line DLk, the pixel electrodes P1 and P3 and the dummy pattern between the passivation layer 46 and the gate insulating layer 42. A second parasitic capacitor Cdp2 formed by 30, a dummy pattern 30 sandwiching the gate insulating film 42, and a third parasitic capacitor Cdp3 formed by the data line DLk. do. Accordingly, the parasitic capacitor CDp is equivalently provided with the first parasitic capacitor Cdp1 connected in parallel with the second and third parasitic capacitors Cdp2 and Cdp3 connected in series as shown in FIG. 6. . Here, since the capacitance of the first parasitic capacitor Cdp1 is relatively decreased as the distance between the data line DL and the pixel electrode P increases, the second and third parasitic capacitors Cdp2 and Cdp3 are further included. The capacity of the parasitic capacitor Cdp becomes smaller than before.

As described above, the liquid crystal display panel according to the first exemplary embodiment includes the dummy pattern 30 to reduce the parasitic capacitor Cdp capacitance between the data line DL and the adjacent pixel electrode P. FIG. Accordingly, distortion of the pixel signal supplied to the data line DL and the pixel electrode P due to the coupling effect of the parasitic capacitor Cdp may be reduced. In addition, as the capacitance of the parasitic capacitor Cdp is reduced, the capacitance variation of the parasitic capacitor Cdp between the data line DL and the left and right pixel electrodes P is also reduced, so that the amount of vertical crosstalk and asymmetric light leakage due to the capacitance variation is reduced. Can be reduced.

Furthermore, the liquid crystal cells 52 and 82 are included in the liquid crystal display panel according to the second exemplary embodiment of the present invention illustrated in FIG. 7 or the liquid crystal display panel according to the third exemplary embodiment of the present invention illustrated in FIG. 8. When the dummy patterns 50 and 80 are electrically connected to the gate line GL, the capacitance of the parasitic capacitor Cdp is further reduced. This is because when the dummy patterns 50 and 80 are connected to a specific voltage source than in the floating state as in the first embodiment, the influence of the dummy patterns 50 and 80 from the pixel signal of the data line DL can be minimized. The dummy patterns 50 and 80 extend downward from the previous gate line GLi-1 as shown in the dummy pattern 50 shown in FIG. 7 to overlap both sides of the pixel electrode P, or FIG. 8. As shown in the dummy pattern 80 shown in FIG. 2, the dummy pattern 80 is extended upward from the current gate line GLi to overlap both sides of the pixel electrode P. Referring to FIG.

Each of the parasitic capacitors Cdp formed between the data lines DLk and the adjacent pixel electrodes P1 and P2 by the dummy patterns 50 and 80 has the passivation layer 66 interposed therebetween as shown in FIG. 9. The first parasitic capacitor Cdp1 formed by the pixel electrodes P1 and P2 and the data line DLk, the pixel electrodes P1 and P3 and the dummy pattern between the passivation layer 66 and the gate insulating layer 62. Third parasitic capacitor Cdp3 formed by the second parasitic capacitor Cdp2 formed by (50, 80), the dummy patterns 50 and 80 having the gate insulating layer 62 interposed therebetween, and the third parasitic capacitor Cdp3 formed by the data line DLk. ) Will be provided. Here, the dummy patterns 50 and 80 may be formed of a gate metal on the lower substrate 60 together with the gate line GL, and may be formed along the data line DLk between the data line DLk and the gate insulating layer 62. The semiconductor layer 64 is further formed.

In this case, since light leakage can be blocked by the dummy patterns 50 and 80, the gap between the data line DLk and the pixel electrodes P1 and P2 can be increased. For example, the distance between the dummy patterns 50 and 80 and the data line DLk is set to 3 μm, which is such that light leakage is blocked by the black matrix 72 of the upper substrate 70. When the width of 80 is set to 5.5 μm and the overlap width of the dummy patterns 50 and 80 and the pixel electrodes P1 and P2 is set to 2.5 μm, the distance between the data line DLk and the pixel electrodes P1 and P2 is 6 μm. It can be increased to about 탆. As the distance between the data line DLk and the pixel electrodes P1 and P2 is relatively increased by the dummy patterns 50 and 80, the parasitic capacitor Cdp may be reduced. In addition, since the dummy patterns 50 and 80 are connected to a specific voltage source, that is, the gate line GL and receive less pixel signal influence from the data line DL, the parasitic capacitor CDp is further reduced. .

The reduction effect of the parasitic capacitor Cdp by the dummy patterns 50 and 80 is a first connection between an input terminal corresponding to the data line DL and an output terminal corresponding to the pixel electrode P, as shown in FIG. 10. The first to third capacitors C1 to C3 are modeled and clearly revealed through simulation results.

Referring to FIG. 10, the first capacitor C1 has a first parasitic capacitor Cdp1 formed between the data line DL and the pixel electrode P, and the second capacitor C2 has a pixel electrode P and a dummy. The second parasitic capacitor Cdp2 formed between the patterns 50 and 80, and the third capacitor C3 are the third parasitic capacitor Cdp3 formed between the data line DL and the dummy patterns 50 and 80. ) Is modeled. Here, it is assumed that the first capacitor C1 has a capacity of 0.5pF, the second capacitor C2 has a capacity of 5pF, and the third capacitor C3 has a capacity of 1.2pF. A constant voltage source 52 for supplying a gate low voltage (eg, -5V) is connected to a node between the second and third parasitic capacitors C2 and C3 corresponding to the dummy patterns 50 and 80. . This is because the dummy patterns 50 and 80 connected to the gate line GLi-1 are supplied with the gate low voltage for most of the period except for one horizontal period during which the gate high voltage is supplied among the frames. In addition, as illustrated in FIG. 11A, an input voltage Vin having a swing width of about 2.5 V and alternating positive and negative polarities is supplied to an input terminal corresponding to the data line DL. Next, as a result of detecting the output voltage Vout at the output terminal corresponding to the pixel electrode P, as shown in FIG. 11B, the second output voltage Vout2 alternates between positive and negative polarities with a swing width of about 100 mV. It can be seen that this is detected. On the other hand, in FIG. 11B, the first output voltage Vout1 is shown in FIG. 11A when only the first capacitor C1 is formed between the conventional parasitic capacitor Cdp, that is, the data line DL and the pixel electrode P. The input voltage as described above is supplied to the input terminal corresponding to the data line DL and then detected at the output terminal corresponding to the pixel electrode P, and it can be seen that it has a swing width of about 300 mV. Accordingly, referring to FIG. 11B, the second output voltage Vout2 by the parasitic capacitor Cdp according to the second embodiment of the present invention is 1 than the first output voltage Vout1 by the conventional parasitic capacitor Cdp. It can be seen that it decreases to about / 3 level.

When the dummy patterns 50 and 80 connected to the gate line GL are provided between the data line DL and the pixel electrode P as shown in FIG. 7 or 9 by the simulation result through the modeling. It can be seen that the capacitance of the parasitic capacitor Cdp between the data line DL and the pixel electrode P is reduced to about one third as compared with the conventional case without the dummy pattern 50.

As described above, the liquid crystal display panel according to the second and third exemplary embodiments includes dummy patterns 50 and 80 connected to the gate line GL, thereby providing parasitics between the data line DL and the adjacent pixel electrode P. FIG. Capacitor (Cdp) capacity can be reduced. Accordingly, distortion of the pixel signal supplied to the data line DL and the pixel electrode P due to the coupling effect of the parasitic capacitor Cdp may be reduced. In addition, as the capacitance of the parasitic capacitor Cdp is reduced, the capacitance variation of the parasitic capacitor Cdp between the data line DL and the left and right pixel electrodes P is also reduced, so that the amount of vertical crosstalk and asymmetric light leakage due to the capacitance variation is reduced. Can be reduced.

However, as shown in FIG. 9, when the dummy patterns 50 and 80 partially overlap the pixel electrodes P1 and P2, the dummy patterns 50 and 80 do not overlap the pixel electrodes P1 and P2. A portion of the black matrix 72 of the upper substrate 70 and the common electrode 76 formed on the color filter 74 directly face each other, thereby providing a strong direct current voltage between the dummy patterns 50 and 80 and the common electrode 76. (Vdc) is taken. Due to the DC voltage Vdc, the liquid crystal present between the dummy patterns 50 and 80 and the common electrode 76 may be deteriorated, and light leakage may be caused by the deteriorated liquid crystal. Furthermore, as the liquid crystal driving time elapses, the liquid crystal deterioration deepens and the amount of light leakage increases, so that a horizontal line phenomenon due to the light leakage may occur.

In order to prevent this, the dummy pattern 90 included in each of the liquid crystal cells 92 and extended from the gate line GL, as in the liquid crystal display panel according to the third embodiment of the present invention, illustrated in FIG. It overlaps completely with both sides of P) so that it does not deviate out of the pixel electrode P. FIG.

Specifically, as shown in FIG. 13, the dummy pattern 90 is formed of a gate metal on the lower substrate 100, and the pixel electrode P1, the gate insulating layer 102 and the passivation layer 106 therebetween. It is formed to completely overlap with both sides of P2). Accordingly, the dummy pattern 90 indirectly faces the common electrode 116 and the pixel electrodes P1 and P2 formed on the black matrix 112 and the color filter 114 of the upper substrate 110 therebetween. . As a result, a direct current is applied between the dummy pattern 90 and the common electrode 116 by the pixel electrodes P1 and P2 alternately supplied with the positive (+) pixel signal and the negative (-) pixel signal in a dot inversion scheme. Since the voltage Vdc is not applied, the deterioration of the liquid crystal due to the DC voltage Vdc can be prevented. A semiconductor layer 104 along the data line DLk is further formed between the data line DLk and the gate insulating layer 102.

Each of the parasitic capacitors Cdp formed between the data line DLk and the adjacent pixel electrodes P1 and P2 by the dummy pattern 90 has a pixel electrode having a passivation layer 106 therebetween as shown in FIG. 13. The first parasitic capacitor Cdp1 formed by the P1 and P2 and the data line DLk, the pixel electrodes P1 and P3 and the dummy pattern 90 interposed between the passivation layer 106 and the gate insulating layer 102. ) And a third parasitic capacitor Cdp3 formed by the dummy pattern 90 having the gate insulating film 102 interposed therebetween, and the third parasitic capacitor Cdp3 formed by the data line DLk.

In this case, since light leakage can be blocked by the dummy pattern 90, the distance between the data line DLk and the pixel electrodes P1 and P2 can be increased. As a result, the distance between the data line DLk and the pixel electrodes P1 and P2 is relatively increased, thereby reducing the capacitance of the parasitic capacitor CDp. In addition, since the dummy pattern 90 is connected to a specific voltage source, that is, the gate line GL, the influence of the pixel signal from the data line DL is less than that in the floating state, as shown in FIG. 11B. The parasitic capacitor Cdp is further reduced.

As described above, the liquid crystal display panel according to the present invention may include a dummy pattern to reduce the parasitic capacitor Cdp capacitance between the data line and the adjacent pixel electrode. In particular, the liquid crystal display panel according to the present invention may include a dummy pattern connected to the gate line to further reduce the parasitic capacitor (Cdp) capacitance between the data line and the pixel electrode.

Accordingly, the liquid crystal display panel according to the present invention can reduce the distortion of the pixel signal supplied to the data line and the pixel electrode due to the coupling effect of the parasitic capacitor (Cdp) as the capacitance of the parasitic capacitor (Cdp) is reduced. do.

Furthermore, in the liquid crystal display panel according to the present invention, the capacitance of the parasitic capacitor Cdp between the data line DL and the left and right pixel electrodes P may be reduced as the capacitance of the parasitic capacitor Cdp is reduced. As a result, the liquid crystal display panel according to the present invention can improve the display quality by reducing the amount of vertical crosstalk and asymmetric light leakage due to variations in the parasitic capacitor Cdp.

In addition, the liquid crystal display panel according to the present invention prevents the liquid crystal deterioration due to the DC voltage between the dummy pattern and the common electrode by preventing the dummy pattern connected to the gate line completely overlapping the pixel electrode and not directly facing the common electrode. It becomes possible. Accordingly, it is possible to prevent the generation of light leakage due to the liquid crystal deterioration of the liquid crystal display panel according to the present invention.

Those skilled in the art will appreciate that various changes and modifications can be made without departing from the technical spirit of the present invention. Therefore, the technical scope of the present invention should not be limited to the contents described in the detailed description of the specification but should be defined by the claims.

Claims (13)

Liquid crystal cells including a thin film transistor formed at an intersection of the gate lines and the data lines, a pixel electrode connected to the thin film transistor, A dummy pattern formed between the data line and the pixel electrode; A first parasitic capacitor formed by a pixel electrode formed with the data line and the first insulating layer interposed therebetween; A second parasitic capacitor formed by the dummy pattern formed between the pixel electrode and the second insulating layer; And a third parasitic capacitor formed by the dummy pattern formed with the data line and the third insulating layer interposed therebetween. The method of claim 1, And the dummy pattern is formed of a gate metal together with the gate line. The method of claim 1, And the dummy pattern is parallel to the data line and partially overlaps one side of the pixel electrode and the second insulating layer. The method of claim 1, And the dummy pattern is parallel to the data line and completely overlaps one side of the pixel electrode with the second insulating layer therebetween. The method of claim 1, And the dummy pattern indirectly faces a common electrode for supplying a reference voltage to the liquid crystal cell and the pixel electrode. The method of claim 1, And the dummy pattern is formed independently for each of the liquid crystal cells. The method of claim 1, And the dummy pattern is connected to the gate line. The method of claim 7, wherein And the dummy pattern is connected to a previous gate line. The method of claim 7, wherein And the dummy pattern is connected to a current gate line. The method of claim 1, The first insulating layer includes a passivation layer formed between the data line and the pixel electrode. The second insulating layer includes the passivation layer and the gate insulating layer formed between the pixel electrode and the dummy pattern. And the third insulating layer includes the gate insulating layer formed between the dummy pattern and the data line. The method of claim 1, The liquid crystal cells A first horizontal line including a data line adjacent to the left side and liquid crystal cells connected through the thin film transistor; And a second horizontal line including data lines adjacent to the right side and liquid crystal cells connected through the thin film transistor. The method of claim 11, In the first horizontal line, the data line and the right pixel electrode thereof charge pixel signals having the same polarity, and the left pixel electrode thereof charge the pixel signals having opposite polarities. And the left pixel electrode of the data line and the right pixel electrode of the second horizontal line charge pixel signals having the same polarity, and the pixel signals of opposite polarities. The method of claim 11, And the first horizontal line and the second horizontal line are alternately arranged in units of at least one horizontal line.