KR100375092B1 - Liquid crystal display and fabricating method thereof - Google Patents

Abstract

The present invention relates to a liquid crystal display device, in order to provide a high-quality liquid crystal display device, the n-th gate line and the n-th gate line, and the m-th data line and the m-th crossing the gate lines, respectively A liquid crystal display device comprising a thin film transistor, wherein a +1 th data line defines an internal region of a (m, n) pixel cell and is electrically connected to the n th gate line and the m th data line. Protruding from the n-th gate line and positioned along the m-th data line, and having holes formed therein, and defining both sides of the hole as a first region and a second region, Only a part of the first extension line formed to overlap the m-th data line; and a portion of the first extension line protruding from the n-th gate line and positioned along the m-th data line; A second extension wiring line having a hole formed therein and defining both regions of the hole as a first region and a second region, wherein only a part of the first region overlaps the rear data line; And a manufacturing method including a pixel electrode positioned in the light transmitting region except for the opaque region of the wires, and a method of manufacturing the same, and minimizing the nonuniformity between the pixel electrode and the data line over the entire pixel cell. Therefore, the size deviation of the parasitic capacitance caused by the overlap of the pixel electrode and the data line can be reduced over the entire pixel cell.

Description

Liquid crystal display and its manufacturing method {LIQUID CRYSTAL DISPLAY AND FABRICATING METHOD THEREOF}

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a liquid crystal display, and more particularly, to an active matrix liquid crystal display (AMLCD) for independently driving a plurality of pixels arranged in a matrix.

The liquid crystal display device includes a first substrate on which a plurality of pixel cells including a switching element and a pixel electrode are arranged, a color filter cell arranged corresponding to each pixel cell of the first substrate, and a common electrode formed on the front surface of the substrate. And a liquid crystal interposed between the second substrate and the first substrate and the second substrate to determine the degree of transmission of light according to the difference in voltage applied to the pixel electrode and the common electrode.

1 is a view for explaining a liquid crystal display device according to the prior art, schematically showing a plan view of a thin film transistor array substrate.

Referring to the drawing, the gate line 10L and the data line 15L cross each other to define an area of the pixel cell. In the pixel cell, a thin film transistor TFT and a pixel electrode 17 electrically connected to the thin film transistor are formed. Thus, the data signal transmitted through the data line 15L is transferred to the pixel electrode 17 through the thin film transistor TFT.

The thin film transistor TFT includes a gate electrode 10G protruding from the gate line 10L, a drain electrode 15D formed corresponding to the source electrode 15S protruding from the data line 15L, and the source electrode 15S, and these The active layer 13 superimposed on the electrode is provided.

At this time, the source electrode 15S, the data line 15L having the same, the drain electrode 15D, the gate electrode 10G, and the gate line 10L having the same and the pixel electrode 17 having the same are conventional devices. And a manufacturing process for forming wiring. That is, after depositing a predetermined material layer, a photoresist film is applied thereon, and a selective exposure is performed using a pattern mask, and developed to form a photoresist pattern. Then, the predetermined material layer is etched using the photoresist pattern as a mask. This is done through a conventional wiring forming process.

However, in the case where the pixel electrode is formed by the manufacturing process as mentioned above, the pixel electrode 17 may be formed by the exposure error due to misalignment of the exposure equipment during the exposure process or the etching error due to the etching process condition during the etching process. Variation in pattern position occurs. Thus, the spacing between the pixel electrode 17 and the data line 15L or the spacing between the pixel electrode 17 and the gate line 10L is not uniform over the entire pixel cell.

When only the distance between the data line and the pixel electrode is considered, as shown in the figure. The interval DL between the pixel electrode 17 and the data lines on the left side thereof, or the interval DR between the pixel electrode 17 and the data lines on the right side thereof is not uniform over all the pixel cells. Thus, the parasitic capacitance present between the pixel electrode and the data line has a large variation depending on the pixel cell. As a result, poor display such as deterioration of image quality is caused.

The present invention provides a liquid crystal display and a method of manufacturing the same, which solves the problems according to the prior art.

The present invention is to provide a liquid crystal display device having high image quality by reducing the variation in parasitic capacitance generated between the pixel electrode and the data line by making the distance between the pixel electrode and the data line uniform throughout the pixel cell.

According to an aspect of the present invention, an n-th gate line and an n-th gate line, and an m-th pixel defining an (m, n) pixel region intersecting the gate lines, respectively, are defined. Protruding from the data line and the m + 1 th data line and the n−1 th gate line and positioned along the m th data line, wherein a hole is formed therein; A first extension line defined as a second area, wherein only a part of the first area overlaps the m-th data line, and the m-th data line protruding from the n-th gate line. A second extension that is formed along the side, and has holes formed therein and defines both sides of the hole as a first region and a second region, wherein only a part of the first region is overlapped with the trailing data line And a thin film transistor electrically connected to the nth gate line and the mth data line, and a pixel electrode connected to the thin film transistor and positioned in a light transmissive area except for an opaque area of the wires. Provide the device.

The present invention also provides a liquid crystal display in which an n-th gate line, an n-th gate line, an m-th data line, and an m-th data line intersect to define an internal area of a pixel cell of (m, n). A method of manufacturing a device, comprising: n-th gate lines and n-th gate lines positioned at predetermined intervals, protruding from and extending from the n-th gate lines, and having holes formed therein; A first extension wiring defining both regions as a first region and a second region, and the first extension wiring are spaced apart from each other by a predetermined distance, and protrude from the n-th gate line to extend Forming a second extension wiring line having both sides of the hole defined as first and second regions, and forming a first insulating layer covering an exposed front surface including the gate lines; Forming an active layer on the first insulating layer to overlap the gate electrode protruding from the n-th gate line, a source electrode and a drain electrode electrically connected to the active layer, and a connection to the source electrode; And intersect the gate lines, but intersect the m-th data line and the gate lines overlapping a portion of the first region of the first extension line, and overlap the portion of the first region of the second extension line. Forming a m + 1th data line to be formed; forming a second insulating film covering an exposed front surface including the data lines; and forming a first contact hole exposing the drain electrode to the second insulating film. And forming the drain electrode on the second insulating layer, wherein the drain electrode is disposed in the light transmission region except for the gate lines, the extension lines, and the data lines. Provides a method of manufacturing the liquid crystal display device comprising a pixel electrode.

1 is a schematic plan view of a liquid crystal display according to the related art

2 is a schematic plan view of a liquid crystal display according to an exemplary embodiment of the present invention.

3 is a cross-sectional view taken along cut lines I-I ', II-II', and III-III 'in the planar structure of the LCD shown in FIG.

4A to 4E are views illustrating a manufacturing process diagram according to the present invention, respectively, along cut lines I-I ', II-II', and III-III 'in the planar structure of the liquid crystal display shown in FIG.

<Description of the symbols for the main parts of the drawings>

Gn: nth gate line. Gn-1: nth-1th gate line.

Dm: m-th data line. Dm + 1: mth + 1th data line.

21: first extension wiring. 22: second extension wiring.

C1: First hole. C2: second hole.

23A: active layer. 23G: gate electrode.

23S: source electrode. 23D: drain electrode.

25: Auxiliary wiring for storage capacitors.

29: pixel electrode.

Hereinafter, the present invention will be described with reference to the following examples and the accompanying drawings.

2 is a schematic plan view of a liquid crystal display according to an exemplary embodiment of the present invention.

In the LCD device, an N × M matrix includes a plurality of pixel cell regions defined by crossing N gate lines formed to extend in a first direction on a substrate and M data lines formed to extend in a second direction crossing the first direction. It is arranged in shape. Each pixel cell region includes a thin film transistor electrically connected to a gate line and a data line, and a pixel electrode connected to a drain electrode of the thin film transistor.

Hereinafter, for the convenience of description, the structure of the liquid crystal display according to the present invention will be described based on one pixel cell, for example, a pixel cell positioned at (n, m) among a plurality of pixel cells arranged in a matrix shape. Explain.

Referring to FIG. 2, which shows a planar structure of a pixel cell located at (n, m), an n−1 th gate line Gn−1 and an n th gate line Gn are arranged at predetermined intervals. Are arranged. The m-th data line Dm and the m-th data line Dm + 1 are spaced at predetermined intervals from the n-th gate line Gn-1 and the n-th gate line Gn. Internal regions of the (n, m) th pixel cells are defined to intersect with each other.

The n-th gate line Gn-1 is positioned along the m-th data line Dm, but has a first hole C1 formed therein, and part of the n-th gate line Gn-1 overlaps the m-th data line Dm. The first extension wiring 21 is extended. An area overlapping with the m th data line Dm is defined as the first area 21-1 among the both areas positioned in the first extension line 21 with the first hole C1 interposed therebetween. The area is defined as the second area 21-2.

In addition, the n-th gate line Gn-1 is positioned along the m-th data line Dm + 1, and a second hole C2 is formed therein, and a portion of the n-th gate line Gn-1 is formed in the n-th gate line Gn-1. The second extension wiring 22 overlapping the first data line Dm + 1 is extended. A region overlapping the m + 1th data line Dm + 1 is defined as the first region 22-1 among both regions positioned between the second hole C2 in the second extension wiring 22. The other area is defined as the second area 22-2.

In addition, the gate electrode 23G and the m-th data line Dm extending from the n-th gate line Gn at portions where the n-th gate line Gn and the m-th data line Dm cross each other. A switching electrode having a source electrode 23S extending from the drain electrode, a drain electrode 23D formed corresponding to the source electrode 23S, and an active layer 23A formed to overlap the electrodes 23S, 23D, 23G. The element 23 is formed.

The pixel electrode 29 is connected to the drain electrode 23D through the first contact hole T1 formed on the drain electrode 23D of the switching element 23. At this time, the pixel electrode 29 is an opaque wiring, that is, a gate line Gn (Gn + 1), a data line Dm (Dm + 1), an extension wiring 21 (22), and a source electrode 23S. In the light transmission region except for the opaque wiring such as the gate electrode 23G and the drain electrode 23D, the contact hole T1 formed on the drain electrode 23D is covered. At this time, the pixel electrode 29 is formed so as to cover the second region 21-2 of the first extension wiring and the second region 22-2 of the second extension wiring, which are opaque wirings. The first hole C1 of the first extension line 21 and the second hole C2 of the second extension line 22 may be extended in both directions.

In the above-described liquid crystal display, the first region 21-1 of the first extension line 21 covers the gap between the m th data line Dm and the pixel electrode 29. That is, the first region 21-1 of the first extension wiring 21 covers the light leaking region between the pixel electrode 29 and the m th data line Dm. Therefore, the first region 21-1 of the first extension wiring 21 serves as a light shielding function. The light shielding function of the first region 22-1 of the second extension wiring 22 is also described in the same manner.

On the other hand, when the protrusions 26 are formed in the m + 1 th data line Dm + 1 to cover the second extension line 22 and the n th gate line Gn positioned adjacent thereto, There is an advantage in that light can be prevented from leaking between the second extension wiring 22 and the nth gate line Gn.

In the drawing, the liquid crystal display has an on-gate storage capacitor in which the pixel electrode overlaps the gate line of the front end to form a storage capacitor.

Auxiliary wiring 25 for a storage capacitor is formed on the n-th gate line Gn-1, and the auxiliary wiring 25 is connected to the pixel electrode 29 through the second contact hole T2. . Thus, in the liquid crystal display according to the present invention, the auxiliary line 25 and the pixel electrode 29 overlap with the n-th gate line Gn-1 to form a storage capacitor.

The second region 21-2 of the first extension wiring 21 overlaps the pixel electrode 29. However, the first extension line 21 protrudes from the n-th gate line Gn-1, which is the front gate line. Accordingly, the overlapping portion of the second region 21-2 of the first extension wiring 21 and the pixel electrode 29 forms a storage capacitor. That is, the second region 21-2 of the first extension wiring is used as the storage capacitor electrode. The storage capacitor electrode function of the second region 22-2 of the second extension wiring 22 is also described in the same manner.

A stack structure of the liquid crystal display device having the above-described planar structure will be described with reference to FIG. 3.

FIG. 3 is a cross-sectional view taken along cut lines I-I ', II-II', and III-III 'in the planar structure of the LCD shown in FIG.

Referring to the cross-sectional structure along the cutting line I-I 'defined to explain the gap between the pixel electrode and the data line, the first extension wiring 21 and the first extension wiring 21 having the first hole C1 on the substrate 200 are formed. Second extension wirings 22 having two holes C2 are formed at predetermined intervals.

Reference numerals 21-1 and 21-2 denote first and second regions located on both sides of the first extension wiring 21 with the first hole C1 interposed therebetween. Reference numerals 22-1 and 22-2 denote first and second regions respectively positioned at both sides with the second hole C2 in the second extension wiring 22 interposed therebetween.

The first insulating layer 210 covers the exposed entire surface including the first extension wiring 21, the second extension wiring 22, and the substrate 200.

The m th data line Dm and the m + 1 th data line Dm + 1 are formed on the first insulating layer 210 at predetermined intervals. In this case, the m-th data line Dm overlaps only a part of the first region 21-1 of the first extension line 21 and is positioned with a first distance d1 from the first hole C1. have. In addition, the m + 1 th data line Dm + 1 overlaps only a part of the first region 22-1 of the second extension line 22 and has a second distance d2 from the second hole C2. Is located.

The second insulating layer 220 covers the exposed entire surface including the m th data line Dm, the m + 1 th data line Dm + 1, and the first insulating layer 210.

The pixel electrode 29 is formed on the second insulating layer 220. The pixel electrode 29 is formed to cover only the first hole C1 of the first extension line 21 and the second hole C2 of the second extension line 22 in both directions. Thus, the pixel electrode 29 has a first distance d1 from the m-th data line Dm and a second distance d2 from the m + 1th data line Dm + 1. do.

Referring to the cross-sectional structure along the cutting line II-II 'defined to explain the gap between the pixel electrode and the gate line, the n-th gate line Gn-1 and the n-th gate on the substrate 200 are described. Line Gn is formed at predetermined intervals.

The first insulating layer 210 covers the exposed entire surface including the n-th gate line Gn-1, the n-th gate line Gn, and the substrate 200.

On the first insulating layer 210, the auxiliary capacitor 25 for the storage capacitor overlaps the n−1 th gate line Gn−1.

The second insulating layer 220 covers the entire exposed surface except for a part of the auxiliary capacitor 25 for the storage capacitor.

The pixel electrode 29 electrically connected to the storage capacitor auxiliary line 25 is formed on the second insulating layer 220 by covering the exposed portion of the storage capacitor auxiliary line 25. Thus, the interlayer wiring 25 and the pixel electrode 29 overlap with the n-th gate line Gn-1 to form a storage capacitor.

The end of the pixel electrode 29 and the end of the n-th gate line Gn are aligned on one boundary line L. FIG.

Referring to the cross-sectional structure along the cut line III-III 'defined to explain the thin film transistor portion, a conventional thin film transistor structure is formed. That is, the gate electrode 23G is formed on the substrate 200, and the first insulating film 210, the source electrode 23S, and the drain electrode 23D are formed thereon. The pixel electrode 29 connected to the drain electrode 23D is formed on the second insulating film 220.

Hereinafter, a cross-sectional view (Fig. 4) of the manufacturing process of the liquid crystal display device as described above will be described in detail.

4A through 4E illustrate cross-sectional views of the manufacturing process along the cutting lines I-I ', II-II', and III-III 'in the planar structure of the liquid crystal display shown in FIG. Hereinafter, a manufacturing process of the liquid crystal display device according to the present invention will be described with reference to FIG. 2.

Referring to FIG. 4A, after depositing the first conductive layer on the substrate 200, the n-th gate line Gn-1 and the n-th gate line G which are positioned at predetermined intervals by photolithography are formed. Gn), the first extension wiring 21 and the second extension wiring 22 are formed.

The first extension line 21 protrudes from the n-th gate line Gn-1 and extends therein, and a first hole C1 is formed therein. Both side regions of the hole C1 in the first extension wiring 21 are defined by the first region 21-1 and the second region 21-2. The second extension line 22 also protrudes from the n-th gate line Gn-1 and extends in the same manner as the first extension line 21, and a second hole C2 is formed therein. It is. Both side regions of the hole C2 in the second extension wiring 22 are defined by the first region 22-1 and the second region 22-2.

Reference numeral 23G denotes a gate electrode formed to protrude from the nth gate line Gn.

Referring to FIG. 4B, a first insulating layer 210 covering the exposed entire surface is formed.

Next, after depositing a semiconductor layer on the first insulating film 210, the photo-etched to form an active layer (23A) overlapping the gate electrode (23G).

Next, after depositing the second conductive layer on the exposed front surface, the photo-etched m-th data line (Dm), the m + 1st data line (Dm + 1) and the source electrode (23S), the drain electrode ( 23D) and the auxiliary wiring 25 for the storage capacitor is formed.

At this time, the m-th data line Dm overlaps only a part of the first region 21-1 of the first extension line 21, but differs from the first hole C1 of the first extension line 21. It is formed to be positioned at a first interval (d1). In addition, the m + 1 th data line Dm + 1 overlaps only a part of the first region 22-1 of the second extension line 22, and the second hole C2 of the second extension line 22 is overlapped. ) Is formed at a second interval d2.

The auxiliary wiring 25 for the storage capacitor is formed to overlap the n-th gate line Gn-1.

Referring to FIG. 4C, a second insulating layer 220 covering the exposed entire surface is formed.

Next, the second insulating layer 220 is photo-etched to expose the first contact hole T1 exposing the drain electrode 23D of the thin film transistor 23 and the second contact hole exposing the storage capacitor auxiliary wiring 25. (T2) is formed.

Next, a transparent conductive material layer 29L covering the exposed front surface is formed.

Referring to FIG. 4D, after the negative photosensitive film is formed on the exposed transparent conductive material layer 29L, a photosensitive film pattern PR defining a region to be the pixel electrode is formed by using a backside exposure technique and a topside exposure technique. do.

During back exposure, an opaque region, that is, gate lines Gn (Gn + 1), data lines Dm (Dm + 1), extension wirings 21 and 22, source electrodes 23S, and gate electrodes 23G. ) And an opaque wiring such as the drain electrode 23D serve as a mask. Thus, the photosensitive film portions PR1, PR2, and PR3 located on the transmissive region other than the opaque wiring are selectively exposed.

PR1 represents a portion of the photosensitive film exposed by the light passing through the central portion of the pixel cell region occupying most of the light transmissive region, and PR2 represents the light passing through the first hole C1 of the first extension wiring 21. The photosensitive film portion exposed by the above is shown, and PR3 represents the photosensitive film part exposed by the light passing through the second hole C2 of the second extension wiring 22.

When the pixel electrode is formed using the photoresist formed only on the backside exposure as an etching mask, the pixel electrode is not connected to the drain electrode 23D and the auxiliary capacitor 25 for the storage capacitor. Thus, the photoresist portion PR4 on the first contact hole T1 exposing the drain electrode 23D and the photoresist portion PR5 on the second contact hole T2 exposing the auxiliary capacitor 25 for the storage capacitor are also exposed. The top surface exposure is performed using a separate photomask M so that it can be exposed.

On the other hand, during the back exposure, the photoresist portion PR2 positioned above the first hole C1 of the first extension wiring 21 and the second hole C2 of the second extension wiring 22 are exposed. The photosensitive film portion PR3 is separated from the central exposure portion PR1 of the pixel cell region. Thus, the photosensitive film portion PR6 on the second region 21-2 of the first extension wiring 21 and the second region 22- of the second extension wiring 22 can be connected to each other so as to connect the separated exposure portions. The photosensitive film portion PR7 on 2) is also selectively exposed. In this case, there is an advantage that the area of the pixel electrode can be extended to holes of extension wirings in both directions.

Referring to FIG. 4E, the transparent conductive material layer 29L at the bottom thereof is etched using the photoresist pattern PR as a mask to form the pixel electrode 29.

The first hole C1 of the m th data line Dm and the first extension line 21 is positioned at a first distance d1 and the m + 1 th data line Dm + 1 and the second extension The second hole C2 of the wiring 22 is positioned at the second interval d2. Accordingly, self-alignment is performed by back exposure using the m th data line Dm, the first extension line 21, the m + 1 th data line Dm + 1, and the second extension line 22 as a mask. The pixel electrode 29 is positioned at a first distance d1 from the m-th data line Dm and at a second distance d2 from the m + 1th data line Dm + 1. do.

In addition, the pixel electrode 29 is electrically connected to the auxiliary capacitor 25 for the storage capacitor positioned on the n−1 th gate line Gn−1. The cross-sectional structure shows a storage capacitor in which the n−1 th gate line Gn−1 and the interlayer wiring 25 are formed through the first insulating layer 210.

In this case, the end of the pixel electrode 29 and the end of the n-th gate line Gn are positioned on one boundary line L. FIG. This is because, as described above, the pixel electrode 29 is formed by the self-alignment technique by the back exposure using the gate line as a mask.

Since the pixel electrode 29 is formed by back exposure using the first and second extension wirings 21 and 22 as masks, the pixel electrodes 29 are automatically aligned with the extension wirings. The first hole C1 of the m th data line Dm and the first extension line 21 is positioned at a first distance d1 and the m + 1 th data line Dm + 1 and the second extension Considering the second hole C2 of the wiring 22 is positioned at a second distance d2, the m th data line Dm, the first extension line 21, and the m + 1 th data line The pixel electrode 29 self-aligned by the back exposure using (Dm + 1) and the second extension wiring 22 as a mask has a first distance d1 from the m-th data line Dm. The m + 1 th data line Dm + 1 is positioned at a second distance d2. The description of the gap between the pixel electrode and the data line applies to all pixel cells of the liquid crystal display device. Thus, the gap between the pixel electrode and the data line can be formed uniformly over the entire pixel cell. The present invention is characterized in that the nonuniformity between the pixel electrode and the data line can be reduced over the entire pixel cell of the liquid crystal display device as compared with the conventional art in which the area of the pixel electrode should be defined only by the top exposure technique.

In addition, since the pixel electrode is formed using a back exposure technique using the gate line as a mask, the pixel electrode is automatically aligned to be positioned on one boundary line with the gate line, in particular, the magnetic end gate line. Therefore, the distance between the pixel electrode and the gate line is automatically uniformed over the entire pixel cells of the liquid crystal display device.

The present invention can minimize the spacing unevenness between the pixel electrode and the data line over the entire pixel cell. Thus, the size deviation of the parasitic capacitance caused by the overlap of the pixel electrode and the data line can be reduced over the entire pixel cell. In addition, the present invention makes it possible to equalize the distance between the pixel electrode and the magnetic terminal gate line over the entire pixel cell. Therefore, generation of parasitic capacitance caused by superposition of the pixel electrode and the magnetic gate gate line can be suppressed.

The present invention can be implemented in various embodiments through the appended claims and the above-mentioned parts as well as the presented embodiments, and can be applied in various ways by its partners.

Claims (10)

An n-th gate line and an n-th gate line, and an m-th data line and an m + 1-th data line that intersect the gate lines, respectively, define an (m, n) pixel region. And a thin film transistor electrically connected to the nth gate line and the mth data line. Protruding from the n-th gate line and positioned along the m-th data line, and having holes therein, both sides of the hole being defined as a first region and a second region, A first extension line formed to partially overlap the m-th data line; Protruding from the n−1 th gate line and positioned along the m + 1 th data line with holes formed therein, and both sides of the hole being defined as a first region and a second region; A second extension line formed to overlap a portion of the region with the m + 1th data line; And a pixel electrode connected to the thin film transistor, the pixel electrode being formed in a light transmissive region except for an opaque region of the wires. The method according to claim 1, The pixel electrode covers the second area of the first extension line and the second area of the second extension line in both directions so as to extend to the first hole of the first extension line and the second hole of the second extension line. The liquid crystal display device is formed to be expanded. The method according to claim 1, And a protrusion formed in the mth data line to cover the first extension line and the nth gate line. The method according to claim 1, And the pixel electrode extends to overlap the n-th gate line to form a storage capacitor with the n-th gate line. The method according to claim 4, And an auxiliary line for a storage capacitor connected to the pixel electrode between the pixel electrode and the n-th gate line. A method of manufacturing a liquid crystal display device, wherein an n-th gate line, an n-th gate line, an m-th data line, and an m-th data line intersect to define an internal area of a pixel cell of (m, n). To The n-th gate line, the n-th gate line, and the n-th gate line, which are positioned at predetermined intervals, protrude from the n-th gate line, and have holes formed therein, and both regions of the hole are formed in the first region. The first extension wiring and the first extension wiring defined as the second region and the first extension wiring are spaced apart from each other, and protrude from the n-th gate line, and have holes formed therein. Forming a second extension wiring defining both regions as a first region and a second region; Forming a first insulating film covering the exposed entire surface including the gate lines, An active layer is formed on the first insulating layer to overlap the gate electrode protruding from the nth gate line, and then A source electrode and a drain electrode electrically connected to the active layer, an mth data line connected to the source electrode and intersecting the gate lines but overlapping a portion of the first region of the first extension line; Forming an m + 1 th data line intersecting the lines but overlapping a portion of the first region of the second extension line; Forming a second insulating film covering the exposed front surface including the data lines, Forming a first contact hole exposing the drain electrode in the second insulating film; And forming a pixel electrode on the second insulating layer, wherein the pixel electrode is disposed in the light transmissive region except for the gate lines, the extension lines, and the data lines. The method of claim 6, wherein the pixel electrode is formed, Depositing a transparent conductive layer covering the exposed front surface including the second insulating film; Forming a negative photosensitive film on the transparent conductive layer; Performing a back exposure so that only a portion of the photoresist layer positioned above the light transmission region except for the gate lines, extension wirings, and data lines can be selectively exposed; Subjecting the photoresist portion above the first contact hole of the drain electrode to be selectively exposed to light; Forming a photoresist pattern in which an exposed portion of the photoresist is selected; And etching the transparent conductive layer using the photoresist pattern as a mask. The method according to claim 7, The top surface exposure is performed so that the second region of the first extension line and the portion of the photoresist layer on the second region of the second extension line are selectively exposed so that the area of the pixel electrode is equal to the first length of the first extension line. A method of manufacturing a liquid crystal display device, which extends into one hole and a second hole of the second extension wiring. The method according to claim 7, And subjecting the upper surface exposure to selectively expose a portion of the photoresist layer on the n-th gate line so that the pixel electrode overlaps the n-th gate line. The method according to claim 9, An auxiliary line overlapping the n-th gate line is formed on the first insulating layer, a second contact hole is formed in the second insulating layer to expose a part of the auxiliary line, and the pixel electrode is formed on the auxiliary electrode. A manufacturing method of a liquid crystal display device formed to be connected to the wiring.