KR100942510B1 - Thin film transistor substrate and method of fabricating the same - Google Patents

Abstract

A thin film transistor substrate for improving display quality and a method of manufacturing the same are disclosed. The compensation wiring is branched from the data line, and a protective film is formed over the data line and the compensation wiring. The light blocking pattern is formed in the edge region of the pixel region to form a compensation capacitor with the compensation wiring to compensate for the coupling capacitor with the data line adjacent to the pixel region, and the pixel electrode is formed on the pixel region. By compensating for the variation of the coupling capacitor to ensure a uniform screen, the display quality can ultimately be improved.

Description

Thin film transistor substrate and its manufacturing method {THIN FILM TRANSISTOR SUBSTRATE AND METHOD OF FABRICATING THE SAME}

1 is a plan view illustrating a thin film transistor substrate according to an exemplary embodiment of the present invention.

2 is a cross-sectional view taken along the cutting lines A-A 'and B-B' of FIG. 1.

3 is an enlarged view of a circle 'C' of FIG. 1.

4A to 4D are plan views illustrating a method of manufacturing a thin film transistor substrate according to an exemplary embodiment of the present invention.

* Description of the symbols for the main parts of the drawings *

111: gate line 112: gate electrode

113: gate pad 115: light blocking pattern

121: data line 122: source electrode

123: drain electrode 124: data pad

130: protective film 150: pixel electrode

171: compensation electrode

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a thin film transistor substrate and a method of manufacturing the same, and more particularly, to a thin film transistor substrate and a method of manufacturing the same for improving display quality.

A liquid crystal display device employing a thin film transistor substrate is one of the most widely used flat panel display devices. It consists of two glass substrates on which electrodes are formed and a liquid crystal layer interposed therebetween, and applies voltage to the two electrodes. To rearrange liquid crystal molecules of the liquid crystal layer to control the amount of light transmitted.

One substrate of such a liquid crystal display device generally has a thin film transistor for switching a voltage applied to an electrode. In addition to the thin film transistor, a wiring including a gate line and a data line and a gate line are applied to the thin film transistor substrate. And gate pads and data pads that transfer to the data lines, respectively. A pixel electrode electrically connected to the thin film transistor is formed in the pixel region defined by the intersection of the gate line and the data line.

When driving such a liquid crystal display, (+) voltage and (-) voltage are periodically inverted and input to the data line, and the pixel electrode voltage changes with the change of the data line voltage by the coupling capacitor between the data line and the pixel electrode. do.

On the other hand, the thin film transistor substrate is wired using several photolithography processes, and the thin film transistor substrate is non-uniform in relative positions between the wires, thin film transistors, and pixel electrode patterns using several photolithography processes. In other words, when the substrate surface is separated into several parts using a stepper and exposed, the distance between the patterns becomes uneven due to different alignment errors between the separated parts. Even when exposing at a time, the distance between each layer pattern becomes uneven due to the interlayer alignment error.

However, when the distances between the wirings are non-uniform, the coupling capacitors may be different from each other, leading to a problem of deterioration in image quality due to a stitch defect or screen irregularity.

Accordingly, an aspect of the present invention is to solve the above-described problems, and an object of the present invention is to provide a thin film transistor substrate having improved display quality by compensating for variation in a coupling capacitor.

Another object of the present invention is to provide a method of manufacturing the thin film transistor substrate.

A thin film transistor substrate according to the present invention for achieving the above object is defined by a gate electrode branched from a gate line, a source electrode branched from a data line, and a drain electrode spaced apart from the source electrode by a predetermined distance. The thin film transistor substrate may include a first compensation electrode formed in the pixel area defined by the gate line and the data line branched from the data line, and formed in the pixel area branched from the data line neighboring the data line. A second compensation electrode, a passivation layer formed on the data line, the neighboring data line, and the first and second compensation electrodes, and an edge region of the pixel area to form a first compensation capacitor with the first compensation electrode. And a light blocking pattern configured to form a second compensation capacitor with the second compensation electrode to compensate for the deviation of coupling capacitors due to the data line and the neighboring data line, and a pixel electrode formed on the pixel area. do.

In addition, the method for manufacturing a thin film transistor substrate according to the present invention for achieving the above-mentioned other object, (a) forming a gate line formed on the substrate, a gate electrode branched from the gate line, (b) the Forming a gate insulating film on the resultant product of step (a), (c) forming a light blocking pattern branched from the gate line, (d) a data line formed on the resultant product of step (c); A data line neighboring the data line, a source electrode branched from the data line, a drain electrode spaced apart from the source electrode at a predetermined interval, a first compensation electrode branched from the data line, and the neighboring data line Forming a second compensation electrode branched from the step (e) forming a protective film on the resultant of step (d), and (f) the Of the area of the output by the system (e) it includes forming so as to overlap the pixel electrode formed in a region defined by the gate lines and data lines of the first and second compensating electrode in part.

According to such a thin film transistor substrate and a manufacturing method thereof, the display quality can be improved by ensuring a uniform screen by compensating for the variation of the coupling capacitor.

Hereinafter, a thin film transistor substrate according to an embodiment of the present invention will be described in detail with reference to the accompanying drawings.

1 is a plan view illustrating a thin film transistor substrate according to an exemplary embodiment of the present invention, and FIG. 2 is a cross-sectional view taken along the cutting lines A-A 'and B-B' of FIG. 1.

1 and 2, a metal or conductive material such as chromium (Cr), molybdenum (Mo), tantalum (Ta), or titanium (Ti) on a substrate 100 made of an insulating material such as glass, quartz, or sapphire Gate lines 111, 112, and 113 formed of a sieve are formed. The gate lines 111, 112, and 113 are formed in the formed gate line 111, the gate electrode 112 and the pad region of the thin film transistor branched from the gate line 111, and a gate pad connected to an end of the gate line 111. (113). In the formation of the gate lines 111, 112, and 113, a liquid crystal capacitor branched from the light blocking pattern 115 and the gate lines 111, 112, and 113 to prevent light leakage from occurring at the edge of one pixel unit. Auxiliary electrode 117 is provided to supplement the.

On the other hand, Figure 1 illustrates a shear gate method for branching the auxiliary electrode 117 to supplement the liquid crystal capacitor in the gate line (111, 112, 113) of the front end, a person skilled in the art of the present invention separate wiring It can be easily modified and changed in the independent wiring method having a secondary electrode in the, or a ring method.

The gate lines 111, 112, and 113 may be formed as a single layer, but may be formed as a double layer or a triple layer. In the case of forming more than two layers, it is preferable that one layer is made of a material having a low resistance and the other layer is made of a material having good contact properties with other materials. A double layer of Al alloy) / Mo can be mentioned.

On the gate lines 111, 112, 113, and the substrate 100, the data lines 121, 122, 123, which are formed of a single metal film such as chromium (Cr) via a gate insulating film 120 made of an inorganic material such as silicon nitride, 124 is formed. The data lines 121, 122, 123, and 124 are formed in the data line 121, the source and drain electrodes 122 and 123 branched from the data line 121, and a pad region, and are formed at the ends of the data line 121. Includes a connected data pad 124.

The compensation electrode 171 branches from the data line 121 to adjust the deviation of the coupling capacitor due to the distance difference between the data line 121 and the light blocking pattern 115.

The data lines 121, 122, 123, and 124 may be formed in a single layer like the gate lines 111, 112, and 113, but may also be formed in a double layer or a triple layer. In the case where more than two layers are formed, it is preferable that one layer is formed of a material having low resistance and the other layer is formed of a material having good contact properties with other materials.

The first pad contact hole 126 exposing the gate pad 113 and the second pad contact hole 133 exposing the data pad 124 on the data lines 121, 122, 123, and 124 and the gate insulating layer 120. A protective film 130 is formed. Preferably, the passivation layer 130 is formed of an inorganic insulator such as silicon nitride. In detail, the first pad contact hole 126 passes through the passivation layer 130 and the gate insulating layer 120 to expose the metal layer of the gate pad 113.

On the passivation layer 130, the pixel electrode 150, the gate pad electrode 132, and the data are made of a transparent material such as indium tin oxide (ITO) or indium zinc oxide (IZO) or a conductive material having high reflectivity such as aluminum or silver. The pad electrode 143 is formed.

The pixel electrode 150 is connected to the drain electrode 123 through the drain contact hole 125 to receive an image signal. Here, the distance between the data line 121 and the light blocking pattern 115 and the distance between the pixel electrode 150 and the light blocking pattern 115 formed through the photolithography process of the different steps are spaced between the patterns due to misalignment. In this case, the compensation electrodes DR and DL branched from the data line 121 are formed to prevent deterioration of image quality caused by the variation of the coupling capacitor.

In the present invention, the compensation electrode 171 is provided to prevent the deterioration of image quality caused by the deviation of the coupling capacitor between the light blocking pattern 115 and the data line 121.

For example, due to an alignment error, the interval 'L1' between the data line Dp of the p-th line and the light blocking pattern 115 is changed to the data line Dp + 1 and the light blocking pattern of the p + 1 line. In the case of smaller than 'L2', the size of the coupling capacitor C1 due to the data line Dp on the Dp side and the light blocking pattern 115 is greater than the coupling capacitor C2 on the Dp + 1 side. Is greater than the size of.

Even in such a case, since the light blocking pattern 115 is formed at an edge of a unit pixel predetermined in design, there is no change in size, and the first compensation electrode DL branched at Dp and the light blocking pattern 115 overlap each other. The area becomes small, and the first compensation capacitor Ca made by the first compensation electrode DL and the light blocking pattern 115 becomes small, and the second compensation electrode DR and the light blocking pattern branched at Dp + 1 ( The area where the 115 overlaps with each other increases, so that the second compensation capacitor Cb formed by the second compensation electrode DR and the light blocking pattern 115 becomes large.

That is, when C1 is increased, the value of the first compensation capacitor Ca is automatically decreased by the increased coupling capacitor value, and when C1 is decreased, the first compensation capacitor is automatically reduced by the reduced coupling capacitor value (C1). The first and second compensation electrodes DR and DL are designed to increase the value of Ca).

On the contrary, 'L1', which is the distance between the data line Dp of the p-th line and the light blocking pattern 115, is the interval between the data line Dp + 1 and the light-blocking pattern 115, which is the p + 1th line. If it is larger than 'L2', the size of C1 is smaller than the size of C2.

Even in such a case, since the light blocking pattern 115 is formed at an edge of a unit pixel predetermined in design, there is no change in size, and the first compensation electrode DL branched at Dp and the light blocking pattern 115 overlap each other. The area becomes larger, and the first compensation capacitor Ca made by the first compensation electrode DL and the light blocking pattern 115 becomes larger, and the second compensation electrode DR and the light blocking pattern 115 branched at Dp + 1. The overlapping area becomes smaller, and the second compensation capacitor Cb formed by the second compensation electrode DR and the light blocking pattern 115 is smaller.

That is, when C1 decreases, the value of the first compensation capacitor Ca is automatically increased by the reduced coupling capacitor value, and when C1 is increased, the first compensation capacitor is automatically increased by the increased coupling capacitor value (C1). The first and second compensation electrodes DR and DL are designed to decrease the value of Ca).

In other words, the size or shape of the first compensation electrode DL and the second compensation electrode DR are designed such that the sum of the C1 and the second compensation capacitor Cb is equal to the sum of the C2 and the first compensation capacitor Ca. Equipped.

3 is an enlarged view of a circle 'C' of FIG. 1.

1 and 3, the compensation electrode 171 extends from the first metal 171a and the first metal 171a parallel to the adjacent gate line 111, and partially overlaps the light blocking pattern 115. It is made of a second metal 171b.

In particular, the second metal 171b has a shape that becomes narrower as it moves away from the first metal in a plan view. This is because when the distance between the data line 121 and the light blocking pattern 115 increases, the coupling capacitor made by the data line 121 and the light blocking pattern 115 becomes smaller, and conversely, the data line 121 and the light blocking pattern When the distance between the 115 is close, the data line 121 and the light blocking pattern 115 are made larger.

That is, since the coupling capacitor is inversely proportional to the gap between the light blocking pattern 115 and the data line 121, the shape of the second metal 171b including a portion where the light blocking pattern 115 and the compensation electrode overlap with each other. In this way, the portion where the light blocking pattern 115 and the compensation electrode 171 overlap is linearly increased.

4A to 4D are plan views illustrating a method of manufacturing a thin film transistor substrate according to an exemplary embodiment of the present invention.

First, as illustrated in FIG. 4A, a gate line conductor or metal is deposited on an insulating substrate (not shown) by sputtering, and patterned by a photolithography process using a mask to form a gate line 111. , A gate line including the gate electrode 112 and the gate pad 113, a light blocking pattern 115 to prevent light leakage occurring at the edge of the pixel region along the edge of the pixel region, and an auxiliary for replenishing the liquid crystal capacitor. The electrode 117 is formed.

Next, as shown in FIG. 4B, a gate insulating film (not shown), an amorphous silicon layer, and an amorphous silicon layer doped with n-type impurities are sequentially deposited by using chemical vapor deposition (CVD), and the like. The two layers are patterned by a photolithography process using a mask to form a semiconductor layer (not shown) and an ohmic contact layer 114.

Next, as illustrated in FIG. 4C, a conductor or a metal for the data line is deposited by a method such as sputtering, and patterned by a photolithography process using a mask to form the data line Dp and Dp + 1 and the drain electrode 123. In addition, a data line including the data pad 124, the first compensation electrode DL, and the second compensation electrode DR is formed. Next, the ohmic contact 122 that does not cover the source electrode 122 and the drain electrode 123 is separated and separated into two parts.

Next, as shown in FIG. 4D, a silicon nitride is deposited or coated to form a protective film (not shown), and then patterned by a photolithography process using a mask to form a drain electrode 123, a gate pad 113, and a data pad. Contact holes 126 and 133 exposing 124 are formed, respectively.

Next, as shown in FIG. 1 and FIG. 2, a transparent conductive material such as ITO or IZO, or a metal having excellent reflectance such as aluminum or silver is deposited on the protective layer 130 by sputtering or the like, and then photo-etched using a mask. Patterning is performed to form the pixel electrode 150, the data pad electrode 143, and the gate pad electrode 132.

As described above, the present invention includes a compensation electrode branched from the data line to compensate for the variation of the coupling capacitor caused by the difference between the light blocking pattern and the distance of the data line, thereby equalizing the size of the capacitor generated between both data lines. Let's do it.

Therefore, the display quality of the liquid crystal display device employing the thin film transistor substrate is improved by ensuring the uniformity of the screen.

It will be apparent to those skilled in the art that various modifications and variations can be made in the present invention without departing from the spirit or scope of the present invention as defined by the following claims It can be understood that

Claims (7)

A thin film transistor substrate having a thin film transistor defined by a gate electrode branched from a gate line, a source electrode branched from a data line, and a drain electrode spaced apart from the source electrode by a predetermined distance, A first compensation electrode branched from the data line and formed in one pixel area defined by the gate line and the data line; A second compensation electrode branched from the data line neighboring the data line and formed in the pixel area; A passivation layer formed on the data line, the neighboring data line, and the first and second compensation electrodes; And a first compensation capacitor formed with the first compensation electrode, and a second compensation capacitor formed with the second compensation electrode formed by the data line and the neighboring data line. A light blocking pattern for compensating for deviations in the coupling capacitors; And And a pixel electrode formed on the pixel region. The thin film of claim 1, wherein the first compensation electrode is formed of a first metal parallel to an adjacent gate line, and a second metal extending vertically from the first metal and partially overlapping the light blocking pattern. Transistor substrate. The thin film transistor substrate of claim 2, wherein the width of the second metal becomes narrower as it moves away from the first metal. delete The method of claim 1, wherein a sum of the first coupling capacitor based on the data line and the light blocking pattern and the first compensation capacitor due to the light blocking pattern of a portion overlapped with the first compensation electrode and the first compensation electrode. silver The sum of the neighboring data line, the second coupling capacitor due to the light blocking pattern, and the second compensation capacitor due to the light blocking pattern of the portion overlapped with the second compensation electrode and the second compensation electrode are the same. A thin film transistor substrate. (a) forming a gate line formed on the substrate and a gate electrode branched from the gate line; (b) forming a gate insulating film on the resultant of step (a); (c) forming a light blocking pattern branched from the gate line; (d) a data line formed on the resultant of step (c), a data line neighboring the data line, a source electrode branched from the data line, a drain electrode spaced apart from the source electrode at a predetermined interval, Forming a first compensation electrode branched from the data line and a second compensation electrode branched from the neighboring data line; (e) forming a protective film on the resultant of step (d); And and (f) forming a pixel electrode formed in the region defined by the gate line and the data line in the region of the resultant by partially overlapping the first and second compensation electrodes. Method for manufacturing a transistor substrate. 7. The data line and the neighboring data line of claim 6, wherein the light blocking pattern is formed in an edge region of the pixel region to form the first and second compensation electrodes and the first and second compensation capacitors. The method of manufacturing a thin film transistor substrate, characterized in that for compensating for the deviation of the coupling capacitors by the.

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