KR20040107031A - Thin film transistor substrate and method of fabricating the same - Google Patents

Abstract

PURPOSE: A thin film transistor substrate and a method for manufacturing the same are provided to compensate the deviation of the coupling capacitor generated due to the distance difference between the pixel electrode and the data line. CONSTITUTION: A thin film transistor substrate includes a compensation line(171), a protection layer and a pixel electrode(150). The compensation line is branched from the data line(121). The protection layer is formed on the data line and the compensation line. The pixel electrode is formed on one of the pixel regions defined by the gate line and the data line. And, the pixel electrode compensates the coupling capacitor placed adjacent the data line by forming the compensation line and the compensation electrode.

Description

Thin film transistor substrate and its manufacturing method {THIN FILM TRANSISTOR SUBSTRATE AND METHOD OF FABRICATING THE SAME}

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a thin film transistor substrate and a method of manufacturing the same, and more particularly, to a thin film transistor substrate and a method of manufacturing the same for improving display quality.

In general, a liquid crystal display device includes two substrates on which electrodes are formed and a liquid crystal layer formed therebetween, and by applying a voltage to each electrode formed on the two substrates, the liquid crystal molecules of the liquid crystal layer are rearranged to transmit light. It is a display device to adjust the amount.

One of two substrates of such a liquid crystal display device generally has a thin film transistor for switching a voltage applied to an electrode, and a substrate having such a thin film transistor is called a thin film transistor substrate (or an array substrate).

The thin film transistor substrate includes a wiring line including a gate line connected to a gate electrode of the thin film transistor and a data line connected to a data electrode, in addition to the thin film transistor, a gate pad configured to receive a signal from the outside and to transfer the signal to the gate line and the data line, respectively; The data pad is formed. A pixel electrode electrically connected to the thin film transistor is formed in the pixel region defined by the gate line and the data line crossing each other.

When driving the liquid crystal display device, the positive voltage and the negative voltage are periodically inverted and input to the data line. The voltage of the pixel electrode is changed by a coupling capacitor between the data line and the pixel electrode. It varies with the variation of the voltage delivered to the data line.

In the meantime, the thin film transistor substrate is wired using several photolithography processes, and the thin film transistor substrate is non-uniform in relative positions between the wires, thin film transistors, and pixel electrode patterns using several photolithography processes. That is, when the substrate surface is separated into several parts using a stepper and exposed, the distance between the patterns becomes nonuniform due to different alignment errors between the separated parts, and the entire substrate surface using a large mask. Even when exposing at a time, the distance between each layer pattern becomes uneven due to the interlayer alignment error. However, when the distance between the pixel electrode and the data line is non-uniform, the coupling capacitor between them becomes different, resulting in a problem of deterioration in image quality due to a poor stitch or a screen unevenness.

Accordingly, an aspect of the present invention is to solve the above-described conventional problem, and an object of the present invention is to provide a thin film transistor substrate for compensating for variation in coupling capacitors to improve display quality.

Another object of the present invention is to provide a method of manufacturing the thin film transistor substrate.

1 is a plan view illustrating a thin film transistor substrate according to an exemplary embodiment of the present invention.

2 is a cross-sectional view taken along the line A-A 'of FIG. 1.

3 is a graph illustrating a correlation between a distance between a data line and a pixel electrode and a coupling capacitor formed by the data line and the pixel electrode.

FIG. 4 is an enlarged view of a portion 'B' of FIG. 1.

5A through 5D are plan views illustrating a method of manufacturing a thin film transistor substrate according to an exemplary embodiment of the present invention.

6 is a plan view illustrating a thin film transistor substrate according to another exemplary embodiment of the present invention.

* Description of the symbols for the main parts of the drawings *

111: gate line 112: gate electrode

113: gate pad 121: data line

122 source electrode 123 drain electrode

124: data pad 130: protective film

150 pixel electrode 171 compensation electrode

A thin film transistor substrate according to the present invention for achieving the above object is formed in a pixel region defined by a gate wiring, a data wiring, a gate electrode line branched from the gate wiring, and data branched from the data wiring. A thin film transistor substrate having an electrode line and a thin film transistor defined by a drain electrode line spaced from the data electrode line by a predetermined distance, comprising: a compensation wiring branched from the data line; A protective film formed on the data line and the compensation line; And a pixel electrode formed on one pixel area defined by the gate line and the data line to form a compensation capacitor with the compensation line to compensate for the coupling capacitor with the data line adjacent to the pixel area. .

In addition, a method of manufacturing a thin film transistor substrate according to the present invention for achieving the above-described other object, (a) forming a gate wiring extending in a first direction on the substrate and a gate electrode line branched from the gate wiring; step; (b) forming a gate insulating film on the resultant of step (a); (c) a data line extending in a second direction on the resultant of step (b), a data electrode line branched from the data line, a drain electrode line spaced apart from the data electrode line by a predetermined distance, and the data Forming a compensation pattern branched from the wiring; (d) forming a protective film on the resultant of step (c); And (e) forming a pixel electrode formed in a region defined by the gate wiring and the data wiring in the region of the resultant product of step (d).

According to such a thin film transistor substrate and a method of manufacturing the same, variations in the coupling capacitor can be compensated for, and ultimately, display quality can be improved.

Hereinafter, a thin film transistor substrate according to an embodiment of the present invention will be described in detail with reference to the accompanying drawings.

1 is a plan view illustrating a thin film transistor substrate according to an exemplary embodiment of the present invention, and FIG. 2 is a cross-sectional view taken along the line A-A 'of FIG. 1.

1 and 2, a metal or conductive material such as chromium (Cr), molybdenum (Mo), tantalum (Ta), or titanium (Ti) on a substrate 100 made of an insulating material such as glass, quartz, or sapphire The gate wirings 111, 112, and 113 formed of sieves are formed. The gate lines 111, 112, and 113 are formed in the gate line 111 extending in the first direction, the gate electrode 112 of the thin film transistor branched from the gate line 111, and the pad region, and the gate line 111 of the gate line 111. It includes a gate pad 113 connected to the end.

The gate wirings 111, 112, and 113 may be formed in a single layer, but may be formed in a double layer or a triple layer. In the case of forming more than two layers, it is preferable that one layer is made of a material having a low resistance and the other layer is made of a material having good contact properties with other materials. For example, a double layer of Cr / Al (or Al alloy) or Al (or A double layer of Al alloy) / Mo can be mentioned.

On the gate wirings 111, 112, 113 and the substrate 100, the data wirings 121, 122, 123, which are made of a single metal film such as chromium (Cr), via a gate insulating film 120 made of an inorganic material such as silicon nitride, and the like. 124 is formed. The data wires 121, 122, 123, and 124 are formed in the data line 121, the source and drain electrodes 122 and 123 branched from the data line 121, and a pad region, and are formed at the ends of the data line 121. Includes a connected data pad 124.

The compensation electrode 171 branches from the data line 121 to adjust the deviation of the coupling capacitor due to the difference in distance between the data line 121 and the pixel electrode 150.

The data wirings 121, 122, 123, and 124 can also be formed in a single layer like the gate wirings 111, 112, and 113, but can also be formed in a double layer or a triple layer. In the case where more than two layers are formed, it is preferable that one layer is formed of a material having low resistance and the other layer is formed of a material having good contact properties with other materials.

First pad contact holes 126 exposing the gate pads 113 and second pad contact holes 133 exposing the data pads 124 on the data lines 121, 122, 123, and 124 and the gate insulating layer 120. A protective film 130 is formed. Preferably, the passivation layer 130 is formed of an inorganic insulator such as silicon nitride. In detail, the first pad contact hole 126 passes through the passivation layer 130 and the gate insulating layer 120 to expose the metal layer of the gate pad 113.

The passivation layer 130 includes a pixel electrode 150, a gate pad electrode 132, and a data pad made of a transparent material such as indium tin oxide (ITO) or indium zinc oxide (IZO) or a conductive material having high reflectivity such as aluminum or silver. An electrode 143 is formed.

The pixel electrode 150 is connected to the drain electrode 123 through the drain contact hole 125 to receive an image signal. Here, the distance between the data line 121 and the pixel electrode 150 formed through another photolithography process is different from each other due to misalignment, so that the compensation electrode DR branched from the data line 121 is different. DL) prevents deterioration in image quality caused by variation in the coupling capacitor.

For example, due to an alignment error, the interval 'L1' between the data line Dp of the p-th line and the pixel electrode 150 is equal to the data line p + 1 and the pixel electrode 150 of the p + 1th line. In the case where the interval between the two is smaller than 'L2', the size of the first capacitor C1, which is a coupling capacitor on the Dp side, is larger than that of the second coupling capacitor C2 on the Dp + 1 side.

Even in such a case, since the size of the pixel electrode 150 which determines the aperture ratio determined in advance by design does not change, an area where the first compensation electrode DL and the pixel electrode 150 branched at Dp overlap with each other becomes small, The first compensation capacitor Ca made by the first compensation electrode DL and the pixel electrode 150 becomes smaller, and the area where the second compensation electrode DR branched from Dp + 1 overlaps with the pixel electrode 150 becomes larger. The second compensation capacitor Cb formed by the second compensation electrode DR and the pixel electrode 150 is increased.

That is, when the C1 is increased, the value of the second compensation capacitor Cb is automatically decreased by the increased coupling capacitor value, and when the C1 is decreased, the first compensation capacitor is automatically increased by the reduced coupling capacitor value (C1). The first and second compensation electrodes DR and DL are designed to increase the value of Ca).

On the contrary, 'L1', which is an interval between the data line Dp of the p-th line and the pixel electrode 150, is' L2, which is an interval between the data line Dp + 1 and the pixel electrode 150, on the p + 1th line. If greater than ', the size of C1 is smaller than the size of C2.

Even in this case, since the size of the pixel electrode 150 that determines the aperture ratio determined in advance by design does not change, an area where the first compensation electrode DL and the pixel electrode 150 branched at Dp overlap with each other is increased. The first compensation capacitor Ca made by the electrode DL and the pixel electrode 150 becomes large, and the area where the second compensation electrode DR branched from Dp + 1 overlaps with the pixel electrode 150 becomes small, resulting in a second reduction. The second compensation capacitor Cb formed by the compensation electrode DR and the pixel electrode 150 becomes small.

That is, when C1 decreases, the value of the second compensation capacitor Cb is automatically increased by the reduced coupling capacitor value, and when C1 is increased, the value of the first compensation capacitor is automatically increased by the increased coupling capacitor value (C1). The first and second compensation electrodes DR and DL are designed to decrease the value of Ca).

In other words, the size or shape of the first compensation electrode DR and the second compensation electrode DR are designed such that the sum of the C1 and the second compensation capacitor Cb is equal to the sum of the C2 and the first compensation capacitor Ca. Equipped.

3 is a graph illustrating a correlation between a distance between a data line and a pixel electrode and a coupling capacitor formed by the data line and the pixel electrode, and FIG. 4 is an enlarged view of a circle 'B' of FIG. 1.

Referring to FIG. 3, when the data line and the pixel electrode move away from each other, the coupling capacitor made by the data line and the pixel electrode becomes smaller, and conversely, when the data line and the pixel electrode become closer, the coupling capacitor made by the data line and the pixel electrode becomes larger. Able to know. Here, the x-axis represents the distance between the data line and the pixel electrode, and the y-axis represents the value of the coupling capacitor produced by the data line and the pixel electrode.

Referring to FIG. 4, the compensation electrode 171 includes a first metal 171a parallel to the adjacent gate line 111, a second metal 171b extending vertically from the first metal 171a, and a second metal ( The third metal 171c extends vertically at 171b and overlaps the pixel electrode 150.

In particular, when viewed in plan, the third metal 171c has a shape that becomes narrower as it moves away from the second metal 171b. This is because when the pixel electrode 150 is far from the data line 131 due to an alignment error, the size of the coupling capacitor is reduced.

Accordingly, the third capacitor includes a portion in which the pixel electrode 150 and the compensation electrode 171 overlap each other according to the graph illustrated in FIG. 3 in which the coupling capacitor is inversely proportional to the distance between the pixel electrode 150 and the data line 131. The shape of the metal 171c is thus designed to linearly increase the overlapping portion of the pixel electrode 150 and the compensation electrode 150.

5A through 5D are plan views illustrating a method of manufacturing a thin film transistor substrate according to an exemplary embodiment of the present invention.

First, as illustrated in FIG. 5A, a gate wiring conductor or metal is deposited on an insulating substrate (not shown) by sputtering, and patterned by a photolithography process using a mask to form a gate line 111, A gate wiring including the gate electrode 112 and the gate electrode 113 is formed.

Next, as shown in FIG. 5B, a gate insulating film (not shown), an amorphous silicon layer, and an amorphous silicon layer doped with n-type impurities are sequentially deposited by using chemical vapor deposition (CVD), and the like. The two layers are patterned by a photolithography process using a mask to form a semiconductor layer (not shown) and an ohmic contact layer 114.

Next, as illustrated in FIG. 5C, a data wiring conductor or metal is deposited by a method such as sputtering, and patterned by a photolithography process using a mask to form the data lines Dp and Dp + 1, the drain electrode 123, and the like. A data line including the data pad 124, the first compensation electrode pattern DR, and the second compensation electrode pattern DL is formed. Next, the ohmic contact 122 that does not cover the source electrode 122 and the drain electrode 123 is separated and separated into two parts.

Next, as shown in FIG. 5D, silicon nitride is deposited or coated to form a protective film (not shown), and then patterned by a photolithography process using a mask to form a drain electrode 123, a gate pad 113, and a data pad. Contact holes 126 and 133 exposing 124 are formed, respectively.

Next, as shown in FIG. 1 and FIG. 2, a transparent conductive material such as ITO or IZO, or a metal having excellent reflectance such as aluminum or silver is deposited on the protective layer 130 by sputtering or the like, and then photo-etched using a mask. Patterning is performed to form the pixel electrode 150, the data pad electrode 143, and the gate pad electrode 132.

6 is a plan view illustrating a thin film transistor substrate according to another exemplary embodiment of the present invention. In FIG. 6, the same reference numerals are assigned to the same components as those illustrated in FIG. 1, and description thereof will be omitted.

Referring to FIG. 6, a gate wiring 111 made of a metal or conductor such as chromium (Cr), molybdenum (Mo), tantalum (Ta), or titanium (Ti) on a substrate made of an insulating material such as glass, quartz, or sapphire 112, 113 are formed. The gate lines 111, 112, and 113 are formed in the gate line 111 extending in the first direction, the gate electrode 112 of the thin film transistor branched from the gate line 111, and the pad region, and the gate line 111 of the gate line 111. It includes a gate pad 113 connected to the end.

The data wires 121, 122, 123, and 124 are formed in the data line 121, the source and drain electrodes 122 and 123 branched from the data line 121, and a pad region, and are formed at the ends of the data line 121. Includes a connected data pad 124.

The compensation electrodes DRa and DLa branch from the data line to adjust the deviation of the coupling capacitor due to the difference in distance between the data line 121 and the pixel electrode 150.

As shown in FIG. 1, the first compensation electrode DRa and the second compensation electrode DRb according to the exemplary embodiment shown in FIG. 6 are also referred to as the p-th data line. It is branched at Dp, and the second compensation electrode DRb is branched at the p + 1th data line Dp + 1.

In FIG. 4, the first and second compensation electrodes DLa and DRa are directly branched from the p-th and p + 1th data lines Dp and Dp + 1, respectively. The first compensation electrode DLa according to the illustrated embodiment is not only branched from the pth and p + 1th data lines but also from the compensation electrode of another pixel.

This type is based on the same technical concept as the direct branching of the data line, and only the specific shape is different, and the first compensation electrode DLa includes the p + 1th data line Dp + 1 and the pixel electrode ( The coupling capacitor made by 150 is compensated for, and the second compensation electrode DRa compensates for the coupling capacitor made by the p-th data line Dp and the pixel electrode 150.

Since there is no change in the size of the pixel electrode 150 that determines the aperture ratio determined by design, an area where the first compensation electrode DLa branched from the Dp and the pixel electrode 150 overlap with each other decreases, and thus the first compensation electrode DLa The value of the first compensation capacitor made by the pixel electrode 150 is reduced, and the area where the second compensation electrode DRa branched from Dp + 1 overlaps with the pixel electrode 150 is increased, thereby increasing the area of the second compensation electrode DRa and the pixel. The second compensation capacitor value produced by the electrode 150 is increased.

That is, when the coupling capacitor value generated by the p-th data line Dp and the pixel electrode 150 increases, the second compensation electrode DRa and the pixel electrode 150 are automatically overlapped by the increased coupling capacitor value. When the value of the capacitor to be made decreases and the value of the coupling capacitor made by the p-th data line Dp and the pixel electrode 150 decreases, the value of the first compensation electrode DLa and the pixel is automatically increased by the reduced coupling capacitor value. When the first and second compensation electrodes DRa and DLa are designed to increase the value of the capacitor made by the electrode 150, the coupling capacitor is automatically adjusted.

In other words, the sum of the coupling capacitor value made by the p-th data line Dp and the pixel electrode 150 and the capacitor value made by the pixel electrode 150 in the overlapped portion with the second compensation electrode DRa are p + 1 th. The first and second compensation electrodes may be equal to the sum of the coupling capacitor value made by the data line Dp and the pixel electrode 150 and the capacitor value made by the pixel electrode 150 overlapping the first compensation electrode DLa. The size and shape of DLa and DRa) are designed and provided.

As described above, the present invention includes a compensation electrode branched from the data line to compensate for the variation of the coupling capacitor caused by the difference between the distance between the pixel electrode and the data line, thereby equalizing the size of the capacitor generated between the two data lines. do.

Therefore, the display quality of the liquid crystal display device employing the thin film transistor substrate is improved by ensuring the uniformity of the screen.

Although described above with reference to a preferred embodiment of the present invention, those skilled in the art will be variously modified and changed within the scope of the invention without departing from the spirit and scope of the invention described in the claims below I can understand that you can.

Claims (7)

A gate electrode line formed in a gate wiring, a pixel region defined by a data wiring, branched from the gate wiring, a data electrode line branched from the data wiring, and a drain electrode line spaced apart from the data electrode line by a predetermined interval. A thin film transistor substrate having a thin film transistor defined by Compensation wiring branched from the data wiring; A protective film formed on the data line and the compensation line; A pixel electrode formed on one pixel region defined by the gate wiring and the data wiring to form a compensation capacitor with the compensation wiring to compensate for a coupling capacitor with the data wiring adjacent to the pixel region; Thin film transistor substrate. The method of claim 1, wherein the compensation wiring, A thin film transistor comprising a first metal parallel to an adjacent gate line, a second metal extending vertically from the first metal, and a third metal extending vertically from the second metal and partially overlapping the pixel electrode. Board. 3. The thin film transistor substrate of claim 2, wherein the third metal becomes narrower as it moves away from the second metal. 2. The magnetic field of claim 1, wherein the compensation wiring is branched from the first data wiring corresponding to the magnetic pixel region to the magnetic pixel region and from the second data wiring corresponding to the adjacent pixel region to the magnetic pixel region. A thin film transistor substrate comprising a second electrode. The sum of the first coupling capacitors of the first data wires and the pixel electrodes, and the capacitors of the pixel electrodes of portions overlapping the second electrodes and the second electrodes. The sum of the second data capacitor and the second coupling capacitor by the pixel electrode and the capacitor by the pixel electrode in a portion overlapping the first electrode and the first electrode are the same. (a) forming a gate wiring extending in a first direction on the substrate and a gate electrode line branched from the gate wiring; (b) forming a gate insulating film on the resultant of step (a); (c) a data line extending in a second direction on the resultant of step (b), a data electrode line branched from the data line, a drain electrode line spaced apart from the data electrode line by a predetermined distance, and the data Forming a compensation pattern branched from the wiring; (d) forming a protective film on the resultant of step (c); And (e) forming a pixel electrode formed in a region defined by the gate wiring and the data wiring in the region of the resultant by step (d). The method of claim 6, wherein the pixel electrode forms a compensation capacitor with the compensation wiring to compensate for a coupling capacitor with a data wiring adjacent to the pixel area.