KR20030006806A - Thin film transistor plate - Google Patents

Abstract

PURPOSE: A thin film transistor substrate is provided to control pixel electrode change amounts, thereby realizing the uniformity in the luminance of a screen. CONSTITUTION: A thin film transistor substrate includes a plurality of gate lines(110), a plurality of data lines(120) intersecting the gate lines respectively, a plurality of thin film transistors(TFT) electrically connected to the gate and data lines, a plurality of pixel electrodes(130) respectively connected to the thin film transistors, dummy data lines(200) formed at a side of the pixel electrodes which neighbor one(DN) of the data lines only at the other side, and a connection pattern(210) for electrically connecting the dummy data line to a data line(DN-1) among all data lines except the data line neighboring the pixel electrodes neighboring the dummy data lines.

Description

Thin Film Transistor Boards {THIN FILM TRANSISTOR PLATE}

The present invention relates to a thin film transistor substrate, and more particularly, to a thin film transistor substrate for a liquid crystal display device.

The liquid crystal display is one of the most widely used flat panel display devices, and includes two substrates on which a plurality of electrodes for generating an electric field are formed, that is, a thin film transistor substrate and a liquid crystal layer between the opposite and opposite substrates, Two polarizers are attached to the outer surface of each substrate to polarize light. The display device controls the amount of light transmitted by rearranging liquid crystal molecules of the liquid crystal layer by applying a voltage to the electrodes.

1 shows a schematic layout of a thin film transistor substrate according to the prior art.

The thin film transistor substrate defines M x N pixel regions in which M gate lines 110 and N data lines 120 cross each other and are arranged in a matrix. Gate pads 112 and data pads 122 are formed at ends of the gate line 110 and the data line 120.

Here, the M gate lines 110 may include the first gate line G1, the second gate line G2,. The M-th gate line GM is arranged at a predetermined interval from the upper side to the lower side. In addition, the N data lines 120 include the first data line D1, the second data line D2,... The N-th data line DN-1 and the N-th data line DN are arranged at a predetermined interval from the left to the right.

Each pixel area includes a thin film transistor TFT electrically connected to the gate line 110 and a data line 120, and a pixel electrode 130 electrically connected to the thin film transistor TFT.

Here, the first data line D1, the second data line D2,... And the pixel electrode 130 connected to the N-th data line DN-1 and the N-th data line DN, respectively, of the first type pixel electrode P1, the second type pixel electrode P2,. N-type pixel electrode PN-1 and N-type pixel electrode PN.

In such a thin film transistor substrate, coupling capacitance generated between the pixel electrode 130 and the neighboring data line 120 serves as a parasitic capacitance that affects the pixel electrode voltage applied to the pixel electrode.

For example, the first type pixel electrode P1 connected to the first data line D1 may have coupling capacitances C1 and C2 generated between the first and second data lines D1 and D2 positioned on the left and right sides thereof. ) Fluctuates by ΔVp1. The change of the pixel electrode is the same in other pixel electrodes P2, ..., PN-1 except for the N-type pixel electrode PN connected to the n-th data line DN.

At this time, since the N-type pixel electrode PN is adjacent only to the N-th data line DN positioned on its left side, it affects the coupling capacitance CN generated between the N-type pixel electrode PN and the N-th data line DN. The variation by ΔVp2 occurs.

Due to the difference in the amount of variation of the pixel electrodes, different amounts of charges are applied to the pixel electrodes P1, P2, ..., PN-1 other than the N-type pixel electrode PN and the N-type pixel electrode PN. Is charged. That is, since the N-type pixel electrode PN is changed by the coupling capacitance between one data line, the other pixel electrode P1, which is affected by the coupling capacitance between the two data lines, is affected. The amount of charge to be charged is larger than that of P2, ..., PN-1).

For this reason, the image shown by the N-type pixel electrode PN becomes brighter by 2-3 gray or more than the image shown by the other pixel electrodes P1, P2, ..., PN-1, causing line defects throughout the screen. It causes poor image quality.

An object of the present invention is to provide a thin film transistor substrate that prevents poor image quality.

1 is a schematic structural diagram of a thin film transistor substrate according to the prior art,

2 is a schematic structural diagram of a thin film transistor substrate according to a first embodiment of the present invention,

3 is a layout view of a thin film transistor substrate according to a second exemplary embodiment of the present invention,

4 and 5 are cross-sectional views of the thin film transistor substrate taken along the cutting lines IV-IV 'and V-V' shown in FIG.

6A is a layout view of a substrate in a first manufacturing step for manufacturing a thin film transistor substrate according to an embodiment of the present invention;

6B and 6C are cross-sectional views illustrating cutting lines VIb-VIb 'and VIc-VIc' of the substrate shown in FIG. 6A;

FIG. 7A is a layout view of a substrate in a subsequent manufacturing step of FIG. 6A,

7B and 7C are cross-sectional views of the substrate shown in FIG. 7A along cut lines Xb-Xb 'and Xc-Xc';

FIG. 8A is a layout view of a substrate in a subsequent manufacturing step of FIG. 7A, and FIG.

8B and 8C are cross-sectional views of the substrate shown in FIG. 8A along cutting lines Xb-Xb 'and Xc-Xc';

FIG. 9A is a layout view of a substrate in a subsequent manufacturing step of FIG. 8A,

9B and 9C are cross-sectional views of the substrate shown in FIG. 9A along cut lines Xb-Xb 'and Xc-Xc'.

In order to solve this technical problem, in the present invention, a dummy data line is formed on the other side of the pixel electrode having a data line on only one side.

Specifically, in the thin film transistor substrate according to the present invention, a plurality of gate lines and a plurality of data lines cross each other, a plurality of thin film transistors are electrically connected to the gate lines and the data lines, and each of the thin film transistors includes a plurality of pixel electrodes. Is formed. The dummy data line is formed on the other side of the pixel electrode adjacent to the data line only on one side of the plurality of pixel electrodes, and the other data lines of the plurality of data lines except for the data line neighboring the neighboring pixel electrode. A connection pattern for electrically connecting one of the data lines and the dummy data line is formed.

The data pad may further include a data pad formed at one end of the data line and a gate pad formed at one end of the gate line, and the connection pattern may be formed around the data pad. In addition, the connection pattern may be formed of a material forming a pixel electrode, and the dummy data line may be formed of a material forming a data line.

Hereinafter, with reference to the accompanying drawings will be described in detail the present invention.

2 is a schematic plan view of a thin film transistor substrate according to a first exemplary embodiment of the present invention.

M gate lines 110 and N data lines 120 define M × N pixel regions in which matrix lines are arranged to cross each other. Gate pads 112 and data pads 122 are formed at ends of the gate line 110 and the data line 120.

Here, the M gate lines 110 may include the first gate line G1, the second gate line G2,. The M-th gate line GM is arranged from the upper side to the lower side of the substrate. In addition, the N data lines 120 include the first data line D1, the second data line D2,... , The N-th data line DN-1 and the N-th data line DN are arranged from the left side to the right side of the substrate.

In the thin film transistor substrate according to the present invention, the dummy data line 200 is formed on the right side of the N-th data line DN at a predetermined distance from the N-th data line DN.

Each pixel area includes a thin film transistor TFT electrically connected to the gate line 110 and a data line 120, and a pixel electrode 130 electrically connected to the thin film transistor TFT.

Here, the first data line D1, the second data line D2,... And the pixel electrode 130 connected to the N-th data line DN-1 and the N-th data line DN, respectively, of the first type pixel electrode P1, the second type pixel electrode P2,. N-type pixel electrode PN-1 and N-type pixel electrode PN.

In the thin film transistor substrate according to the present invention, a connection pattern 210 for connecting the dummy data line 200 and the N-th data line DN-1 is formed. The connection pattern 210 is positioned around the data pad 122 away from the pixel area. By the connection pattern 210, the same signal as that of the data signal coming into the N-th data line DN-1 is applied to the dummy data line 200.

In such a thin film transistor substrate, coupling capacitance generated between the pixel electrode 130 and the neighboring data line 120 serves as a parasitic capacitance that affects the pixel electrode voltage applied to the pixel electrode.

For example, the first type pixel electrode P1 connected to the first data line D1 may have coupling capacitances C1 and C2 generated between the first and second data lines D1 and D2 positioned on the left and right sides thereof. ) Fluctuates by ΔVp1. Such fluctuations of the pixel electrodes occur equally in all the pixel electrodes P2, ..., PN-1, PN of the substrate.

In the case of the N-type pixel electrode PN, the coupling capacitance CN and Cq generated between the N-th data line DN positioned on the left side and the dummy data line 200 positioned on the right side is affected. Is then changed by ΔVp2.

Here, ΔVp1 and ΔVp2 are both affected by the coupling capacitance between the pixel electrode and two adjacent data lines, and thus have the same value. For this reason, all pixel electrodes are charged with the same amount of electric charge to represent an image of the same brightness. Therefore, the overall brightness of the screen can be made uniform to improve image quality characteristics.

Here, the connection pattern 220 may connect the dummy data line 200 to other data lines D1, D2, ... except for the Nth data line DN in addition to the N-1th data line DN-1. The same effect can be obtained.

In the first embodiment of the present invention described above, the pixel electrode is connected to the data line positioned on the left side, whereby the right side of the N-type pixel electrode PN arranged on the last line of the substrate, that is, the Nth data line ( The structure for forming the dummy data line 200 on the right side of DN) is shown. However, the present invention can be applied in various ways in addition to such a structure. For example, by connecting the pixel electrode to the data line positioned on the right side, the dummy data on the left side of the first type pixel electrode P1 arranged on the first line of the substrate, that is, on the left side of the first data line D1. A structure for forming a line can be proposed.

3 is a layout view of a thin film transistor substrate according to a second exemplary embodiment of the present invention, and FIGS. 4 and 5 are cross-sectional views of the thin film transistor substrate taken along the cutting lines IV-IV ′ and V-V ′ of FIG. 3.

A plurality of gate wirings made of metal such as aluminum or aluminum alloy, molybdenum or molybdenum alloy, chromium or chromium alloy, tantalum or tantalum alloy, titanium or titanium alloy is formed on the insulating substrate 10.

Each gate wiring is connected to the gate line 22 and the gate line 22 extending in the horizontal direction, so that the gate pad 24 and the gate line receive the gate signal from the outside and transmit the gate signal to the gate line 22. And a gate electrode 26 of the thin film transistor connected to the reference numeral 22.

Here, the gate wiring may be formed to have a structure of more than two layers, in this case, one layer is formed of a conductive material of aluminum-based low resistance, the other layer is formed of a material having good contact properties with other materials It is advantageous. Examples thereof include Cr / Al (or Al alloy) or Al / Mo.

On the insulating substrate 10, a gate insulating film 30 made of silicon nitride or the like covers the gate wirings 22, 24, 26, 27, and 29.

A semiconductor pattern 42 made of a semiconductor such as amorphous silicon is formed on the gate insulating layer 30, and an amorphous silicon or the like doped with a high concentration of impurities is formed on the semiconductor pattern 42. Resistive contact patterns 55 and 56 are formed, respectively.

On the resistive contact patterns 55 and 56 and the gate insulating film 30, a plurality of data wires are made of metal such as aluminum or aluminum alloy, molybdenum or molybdenum alloy, chromium or chromium alloy, tantalum or tantalum alloy, or titanium or titanium alloy. Is formed.

Each data line is formed in a vertical direction and is connected to one end of the data line 62 and the data line 62 that crosses the gate line 22 to define a pixel area, and receives a data signal from an external source. 64, a source electrode 65 protruding from the data line 62 and contacting the ohmic contact pattern 55, separated from the source electrode 65, and opposite to the source electrode 65 with respect to the gate electrode 26. Data line portions 62, 64, 65, and 66 including the drain electrode 66 in contact with the ohmic contact pattern 56 and dummy data arranged parallel to the data line 62 and intersect the gate line 22. Line 68;

Here, for convenience of description, the first data line D1, the second data line D2,... It is defined as

The dummy data line 68 is formed on the other side of the pixel area in which the data line is located only on one side. As shown in Fig. 3, since the first data line D1 is located on the right side, it is preferable that the derby data line 68 is formed on the right side in the pixel area where the wiring is not located on the left side. In this case, data lines or dummy data lines are located on the left and right sides of every pixel area.

The passivation layer 70 made of silicon nitride is formed on the data lines 62, 64, 65, 66, and 68 and the thin film transistor.

The passivation layer 70 includes a first contact hole 72 exposing the drain electrode 66, a second contact hole 74 exposing the data pad 64, and a third contact hole exposing an edge portion of the dummy data line 68. A fourth contact hole 76 is formed to expose the second data line D2 and to be parallel to the third contact hole 75. In addition, a fifth contact hole 78 exposing the gate pad 24 is formed in the passivation layer 70 and the gate insulating layer 30.

The pixel electrode 82 electrically connected to the drain electrode 66 through the first contact hole 72 and the auxiliary data pad connected to the data pad 64 through the second contact hole 74 on the passivation layer 70. An auxiliary gate pad 86 is formed, which is connected to the gate pad 24 through the 84 and fifth contact holes 78, and the dummy through the third contact hole 75 and the fourth contact hole 76. The connection pattern 88 connecting the data line 68 and the second data line D2 is formed. In this case, the pixel electrode 82, the auxiliary data pad 84, the auxiliary gate pad 86, and the connection pattern 88 may be formed of ITO or IZO.

The connection pattern 88 may be connected to another data line except for the first data line D1 in addition to the second data line D2.

Next, a method of manufacturing the liquid crystal display according to the exemplary embodiment of the present invention will be described in detail with reference to FIGS. 6A to 9C and FIGS. 3, 4 and 5.

First, as shown in FIGS. 6A, 6B, and 6C, a metal layer made of aluminum or an aluminum alloy, chromium or chromium alloy, molybdenum or molybdenum alloy, titanium or titanium alloy, or tantalum or tantalum alloy is placed on the substrate 10. After the deposition, the metal layer is patterned by a photolithography process to form a gate wiring including the gate line 22, the gate pad 24, and the gate electrode 26.

Next, as shown in FIGS. 7A, 7B, and 7C, three layers of the gate insulating film 30, the semiconductor layer, and the semiconductor layer doped with impurities are sequentially stacked, and then the semiconductor layer and the semiconductor layer doped with impurities are formed. The resistive contact layer pattern 52 and the semiconductor pattern 42 are formed on the gate electrode 26 by patterning by a photolithography process.

Next, as shown in FIGS. 8A, 8B, and 8C, a metal layer made of chromium or chromium alloy, molybdenum or molybdenum alloy, titanium or titanium alloy, tantalum or tantalum alloy on the gate insulating film 30 and the semiconductor pattern 42. After the deposition, the metal layer is patterned by a photolithography process to include the data lines 62, 64, 65, including the data line 62, the data pad 64, the source electrode 65, and the drain electrode 66. Data lines 62, 64, 65, 66, and 68 including the 66 and dummy data lines 68 are formed.

Subsequently, the island-like ohmic contact layer pattern 52 positioned at the bottom thereof using the source electrode 65 and the drain electrode 66 as a mask is etched to contact the source electrode 65 with the ohmic contact layer pattern 55. The resistive contact layer pattern 56 in contact with the drain electrode 66 is separated.

Next, as shown in Figs. 9A, 9B and 9C, a protective film 70 made of silicon nitride covering the data wiring and the thin film transistor is formed.

Next, the first contact hole 72 exposing the drain electrode 66 and the second contact hole 74 exposing the data pad 64 are exposed by photo etching the protective layer 70 and the gate insulating layer 30 by a photolithography process. The third contact hole 75 exposing the edge portion of the dummy data line 68 and the fourth contact hole 76 exposing the second data line D2 and positioned in parallel with the third contact hole 75. And a fifth contact hole 78 exposing the gate pad 24.

Next, again, as shown in Figs. 3, 4 and 5, after depositing a transparent conductive film made of IZO or ITO on the exposed front surface of the substrate including the protective film 70, the transparent conductive film is a photolithography process Pixel electrode 82 contacting the drain electrode 66 through the first contact hole 72 through the first contact hole 72, and the auxiliary data pad 84 connected to the data pad 64 through the second contact hole 74. And the dummy data line 68 and the auxiliary data through the auxiliary gate pad 86, the third contact hole 75, and the fourth contact hole 76, which are connected to the gate pad 24 through the fifth contact hole 78. The connection pattern 88 connecting the two data lines D2 is formed.

Subsequently, a subsequent process is performed to complete the manufacturing process of the thin film transistor substrate.

As described above, in the present invention, the dummy data line is formed on the other side of the pixel electrode having the data line only on one side, thereby making the size of the coupling capacitance affecting all the pixel electrodes of the substrate the same.

The present invention makes the amount of charges charged in all the pixel electrodes the same by adjusting the amount of fluctuation in the pixel electrodes occurring in all the pixel electrodes. As a result, all the pixel electrodes of the substrate show the image of the same brightness to ensure the brightness uniformity of the screen, thereby improving the image quality.

Claims (4)

A plurality of gate lines; A plurality of data lines crossing each of the gate lines; A plurality of thin film transistors electrically connected to the gate line and the data line; A plurality of pixel electrodes connected to each of the thin film transistors; A dummy data line having a data line formed on only one side of the plurality of pixel electrodes on the other side of a neighboring pixel electrode; A connection pattern electrically connecting one of the data lines among the other data lines except the data line adjacent to the neighboring pixel electrode among the plurality of data lines and the dummy data line. Thin film transistor substrate comprising a. In claim 1, A data pad formed at one end of the data line and a gate pad formed at one end of the gate line; The connection pattern is formed on the thin film transistor substrate to be positioned around the data pad. In claim 1, The connection pattern is a thin film transistor substrate formed of a material forming the pixel electrode. In claim 1, And the dummy data line is formed of a material forming the data line.