KR20060080038A - Thin film transistor panel for liquid crystal display and method for manufacturing the same - Google Patents

Abstract

The thin film transistor substrate for a liquid crystal display device includes an insulating substrate, a gate line formed on the insulating substrate, a gate insulating film formed on the insulating substrate on which the gate line is formed, a data line formed on the gate insulating film and intersecting the gate line, and formed on the gate insulating film. And a storage capacitive electrode formed of the same material as the data line, a protective layer formed on the insulating substrate on which the data line and the storage capacitive electrode are formed, and a pixel electrode formed on the protective layer and at least partially overlapping the storage capacitive electrode.

In addition, a method of manufacturing a thin film transistor substrate for a liquid crystal display device is provided.

Liquid Crystal Display, Thin Film Transistor Board, Response Speed, Capacitive Electrode, Bridge

Description

Thin film transistor panel for liquid crystal display device and manufacturing method therefor {Thin film transistor panel for liquid crystal display and method for manufacturing the same}

1 is a conceptual diagram of a liquid crystal display according to a first embodiment of the present invention.

2A is a plan view of a thin film transistor substrate for a liquid crystal display according to a first embodiment of the present invention.

FIG. 2B is a cross-sectional view taken along the line IIb-IIb ′ of FIG. 2A.

FIG. 3 is a signal waveform diagram for describing a data signal when switching from black to white.

4 is a graph illustrating a change in luminance over time when a switch is made from black to white.

5 is a graph showing a change in position of the cusp according to the ratio of the capacitance of the sustain capacitor and the capacitance of the liquid crystal capacitor.

6A, 7A, 8A, and 9A are plan views illustrating a method of manufacturing a thin film transistor for a liquid crystal display according to a first embodiment of the present invention.

FIG. 6B is a cross-sectional view taken along the line VIb-VIb ′ of FIG. 6A.

FIG. 7B is a cross-sectional view taken along the line VIIb-VIIb 'of FIG. 7A.                 

FIG. 8B is a cross-sectional view taken along the line 'b-'b' of FIG. 8A.

FIG. 9B is a cross-sectional view taken along line VIIb-VIIb 'of FIG. 9A.

10A is a plan view of a thin film transistor substrate for a liquid crystal display according to a second exemplary embodiment of the present invention.

FIG. 10B is a cross-sectional view taken along the line VIIb-VIIb 'of FIG. 10A.

11A is a plan view of a thin film transistor substrate for a liquid crystal display according to a third exemplary embodiment of the present invention.

FIG. 11B is a cross-sectional view taken along the line 'Ib-'Ib' of FIG. 10A.

12A is a plan view of a thin film transistor substrate for a liquid crystal display according to a fourth embodiment of the present invention.

12B is a cross-sectional view taken along line IIb-IIb 'of FIG. 12A.

13A is a plan view of a thin film transistor substrate for a liquid crystal display according to a fifth embodiment of the present invention.

FIG. 13B is a cross-sectional view taken along the line IIIIII-IIIIII ′ of FIG. 13A. (Explanation of symbols for the main parts of the drawing)

1: liquid crystal panel 2: gate driver

3: data driver 4: thin film transistor substrate

10: insulated substrate 22: gate line

24: gate pad 26: gate electrode

30 gate insulating film 40 semiconductor layer                 

55, 56: ohmic contact layer 62: data line

64: source electrode 66: drain electrode

68: data pad 70: sustained capacitive electrode

80: protective layer 90: pixel electrode

91: first bridge 92: second bridge

94: auxiliary gate pad 98: auxiliary data pad

The present invention relates to a thin film transistor substrate for a liquid crystal display device and a manufacturing method thereof.

A liquid crystal display (LCD) includes a liquid crystal layer having dielectric anisotropy in which the arrangement direction is changed by a voltage applied from the outside. The liquid crystal display device displays an image such as letters, numbers, arbitrary icons, etc. by applying a voltage to the liquid crystal layer, and adjusting the intensity of the voltage to adjust the transmittance of light passing through the liquid crystal layer.

Liquid crystal displays are representative of flat panel displays (FPDs), and have advantages such as small size, light weight, and low power consumption compared to cathode ray tubes. Therefore, the liquid crystal display device is widely applied to the general industry, for example, the computer industry, the electronic industry, the information and communication industry, etc. due to such unique advantages. In addition, the liquid crystal display device has been applied to various fields such as a display device of a portable computer, a monitor of a desktop computer, a monitor of a high-definition video device, and the like.

Based on the driving method, the liquid crystal display may be classified into an active matrix display device and a passive matrix display device according to whether a switching element is used. The active matrix display device is a method of applying a voltage to a liquid crystal by using an active element such as a thin film transistor as a switch and driving the passive matrix display device. A passive matrix display device arranges a plurality of electrode strings in a vertical matrix to form a liquid crystal. It is driven by applying voltage. Recently, active matrix display devices have been widely used.

When the screen is changed from black to white, the active matrix display responds by generating a cusp in which a luminance change occurs in two stages due to a voltage change applied to the liquid crystal. The phenomenon that time decreases may occur. In particular, in a liquid crystal display device using a liquid crystal having a small cell gap and having a large dielectric anisotropy, this phenomenon is more prominent.

An object of the present invention is to provide a thin film transistor substrate for a liquid crystal display device having improved characteristics.

Another object of the present invention is to provide a method of manufacturing a thin film transistor substrate for a liquid crystal display device having improved characteristics.

The technical problems of the present invention are not limited to the above-mentioned technical problems, and other technical problems not mentioned will be clearly understood by those skilled in the art from the following description.

The thin film transistor substrate for a liquid crystal display device according to the first embodiment of the present invention for achieving the technical problem is an insulating substrate, a gate line formed on the insulating substrate, a gate insulating film formed on the insulating substrate formed with the gate line, the gate insulating film A data line formed over the gate line, a storage layer formed on the gate insulating layer, and a protective layer formed on the insulating substrate on which the data line and the storage capacitive electrode are formed; And a pixel electrode at least partially overlapping the storage capacitive electrode.

According to another aspect of the present invention, there is provided a method of manufacturing a thin film transistor substrate for a liquid crystal display device, the method including: forming a gate line on an insulating substrate, forming a gate insulating film on the gate line, Forming a storage capacitive electrode on a gate insulating layer with a data line crossing the gate line and the same material as the data line, forming a protective layer on an insulating substrate on which the data line and the storage capacitive electrode are formed, and holding on the protective layer Forming a pixel electrode at least partially overlapping the capacitive electrode.

Specific details of other embodiments are included in the detailed description and the drawings.

Advantages and features of the present invention and methods for achieving them will be apparent with reference to the embodiments described below in detail with the accompanying drawings. However, the present invention is not limited to the embodiments disclosed below, but may be implemented in various forms. It is provided to fully convey the scope of the invention to those skilled in the art, and the present invention is defined only by the scope of the claims. Like reference numerals refer to like elements throughout.

1 is a conceptual diagram of a liquid crystal display according to a first embodiment of the present invention.

Referring to FIG. 1, the liquid crystal display according to the first exemplary embodiment of the present invention includes a liquid crystal panel 1, a gate driver 2, and a data driver 3.

The liquid crystal panel 1 includes a plurality of gate lines G ₁ to G _n and data lines D ₁ to D _m and a matrix-type pixel area formed by crossing them as an equivalent circuit. The gate lines G ₁ to G _n extend in the row direction to transfer the gate signals, and the data lines D ₁ to D _m extend in the column direction to transfer the data signals. The switching elements M, the liquid crystal capacitors C _lc , and the first and second sustain capacitors C _st1 are connected to the gate lines G ₁ to G _n and the data lines D ₁ to D _{m in the} plurality of pixel regions. , C _st2 ).

The switching element M is a three-terminal element, the control terminal is connected to the gate lines (G ₁ to G _n ), the input terminal is connected to the data lines (D ₁ to D _m ), the output terminal is a liquid crystal capacitor (C _lc ) and one terminal of the first and second sustain capacitors C _st1 and C _st2 . In addition, the switching element M is implemented as a thin film transistor including amorphous silicon and polysilicon as a channel layer.

The liquid crystal capacitor C _lc is connected to the output terminal of the switching element M and a common voltage Vcom or a reference voltage Vref.

The first and second sustain capacitors C _st1 and C _st2 are connected between the output terminal of the switching element M and the common voltage (independent wiring) or the gate line directly above the output terminal of the switching element M ( G ₁ to G _n ) may be connected (shear gate method). In FIG. 1, the first sustain capacitor C _st1 is connected by an independent wiring method, and the second sustain capacitor C _st2 is connected by a front gate method.

The gate driver 2 sequentially provides a gate signal for activating the switching element M to the plurality of gate lines G ₁ to G _n . The data driver 3 provides the grayscale voltage corresponding to the data signal to the plurality of data lines D ₁ to D _m in accordance with the timing at which the gate signal is applied.

2A is a plan view of a thin film transistor substrate for a liquid crystal display according to a first embodiment of the present invention. FIG. 2B is a cross-sectional view taken along the line IIb-IIb ′ of FIG. 2A.

2A and 2B, a thin film transistor substrate for a liquid crystal display according to a first exemplary embodiment of the present invention may include gate wirings 22, 24, and 26, a gate insulating layer 30, a semiconductor layer 40, and a resistance contact. Layers 55 and 56, data lines 62, 64, 66, 68, storage capacitive electrode 70, protective layer 80, pixel electrode 90, first and second bridges 91, 92 And an auxiliary gate pad 94 and an auxiliary data pad 98.

The gate wires 22, 24, and 26 are formed on the insulating substrate 10 and include a gate pad 24, a gate line 22, and a gate electrode 26. The gate pad 24 is connected to the end of the gate line 22 to receive a gate signal from the outside. The gate line 22 is elongated in the row direction to transmit the applied gate signal to the gate electrode 26, and the gate electrode 26 receives the gate signal to turn on the thin film transistor.

In addition, the gate lines 22, 24, and 26 may be formed in a single layer or a double layer or more. When formed as a single layer is formed of aluminum (Al) or aluminum alloy (Al alloy), and when forming more than a double layer as shown in Figure 2b, the lower layers (24a, 26a) is indium tin oxide (ITO) or indium zinc (IZO) The upper layers 24b and 26b may be formed of an opaque conductive film such as aluminum (Al), molybdenum (Mo), and molybdenum-tungsten alloy (MoW).

The gate insulating layer 30 is formed on the insulating substrate 10 on which the gate lines 22, 24, and 26 are formed, and may be mainly made of silicon nitride (SiN _x ) or the like.

The semiconductor layer 40 is formed on the gate insulating layer 30 of the gate electrode 26. The semiconductor layer 40 may be formed of amorphous silicon, polysilicon, or the like.

The ohmic contacts 55 and 56 are formed on the semiconductor layer 40 by being separated from both sides of the gate electrode 26. The ohmic contacts 55 and 56 may be made of n + hydrogenated amorphous silicon, polysilicon, or the like doped with a high concentration of n-type impurities such as silicide or phosphorus (P).

The data wires 62, 64, 66, and 68 are formed on the ohmic contact layers 55 and 56 and the gate insulating layer 30, and the data pads 68, the data lines 62, the source electrodes 64, and the drains are formed on the data lines 62 and 64. Electrode 66. The data pad 68 is connected to the end of the data line 62 to receive a gray voltage corresponding to the data signal from the outside. The data line 62 is formed to extend in the column direction to intersect the gate line 22 and define a pixel. In addition, the source electrode 64 is a branch of the data line 62 and extends to the upper portion of the ohmic contact layer 55. The drain electrode 66 is formed on the ohmic contact layer 56 positioned opposite the source electrode 64 with respect to the gate electrode 26, and is formed separately from the source electrode 64.

In addition, the data lines 62, 64, 66, and 68 may be formed in a single layer or a double layer or more. When formed as a single layer, it may be formed of aluminum (Al), aluminum alloy (Al alloy), molybdenum-tungsten (MoW) alloy, chromium (Cr), tantalum (Ta) and the like. 2B, the lower layers 62a, 64a, 66a are formed of a material having low resistance, and the upper layers 62b, 64b, 66b are made of a material having good contact properties with other materials. It is desirable to lose. For example, the pair of bottom layers 62a, 64a, 66a and top layers 62b, 64b, 66b may be chromium (Cr) / aluminum (Al) (or aluminum alloy), aluminum (Al) / molybdenum (Mo). , Chromium (Cr) or molybdenum-tungsten alloy (MoW) / aluminum (Al).

The storage capacitive electrode 70 constitutes a first storage capacitor 71 (see C _{st1 in} FIG. 1). The storage capacitive electrode 70 is positioned on the gate insulating layer 30. The storage capacitive electrode 70 may be formed of more than a single layer or a double layer 70a, 70b, and the constituent material is the same as that of the data lines 62, 64, 66, and 68. In this case, the storage capacitive electrode 70 may be formed at the same time as the data lines 62, 64, 66, and 68, or may be formed separately from the data lines 62, 64, 66, and 68.

In addition, the storage capacitive electrode 70 includes a first partial storage capacitive electrode 70c parallel to the gate line 22 and a second partial storage capacitive electrode 70d parallel to the data line 62. . In the thin film transistor substrate 4 for a liquid crystal display device according to the first embodiment of the present invention, an end of the first partial storage capacitive electrode 70c is connected to the middle of the second partial storage capacitive electrode 70d so as to be 'ㅓ'. 'It is made of a shape, but is not limited thereto.

The passivation layer 80 may be formed on the data lines 62, 64, 66, and 68 and the storage capacitive electrode 70, and may be formed of silicon nitride (SiN _x ) or an organic insulating layer. The protective layer 80 includes first to fourth contact holes 81, 82, 83, and 84 that expose the capacitive electrode 70, a fifth contact hole 85 that exposes the gate pad 24, and a drain. A sixth contact hole 86 exposing the electrode 66 and a seventh contact hole 88 exposing the data pad 68 are formed.

The pixel electrode 90 is electrically connected to the drain electrode 66 through the sixth contact hole 86, and at least a part of the pixel electrode 90 overlaps the first storage capacitor 71 (FIG. 1). C _st1 ), and a second sustain capacitor 72 (see C _st2 of FIG. 1) is formed from the front gate line 22.

The first and second bridges 91 and 92 electrically connect the storage capacitive electrodes 70 of adjacent pixels. That is, the first bridge 91 electrically connects the storage capacitor electrode 70 of the upper pixel and the lower pixel through the first contact hole 81 and the third contact hole 83. The second bridge 92 electrically connects the storage capacitor electrode 70 of the left pixel and the right pixel through the second contact hole 82 and the fourth contact hole 84.

The auxiliary gate pad 94 and the auxiliary data pad 98 are electrically connected to the gate pad 24 and the data pad 68 through the fifth contact hole 85 and the seventh contact hole 88, respectively. The auxiliary gate pad 94 and the auxiliary data pad 98 complement the contact with the external circuit device and protect the gate pad 24 and the data pad 68.

Hereinafter, as in the thin film transistor substrate for a liquid crystal display according to the first embodiment of the present invention, the reason for forming the storage capacitive electrode 70 on the gate insulating film 30 will be described.

In general, the response time of the twisted nematic (TN) mode may be represented by Equation 1. The response time means the time taken to change from 10% to 90% of the luminance difference between the two gray levels when the gray level changes. Here, τ _on represents a response time when switching from white to black, and τ _off represents a response time when switching from black to white. d is the cell gap, γ ₁ is the rotational viscosity of the liquid crystal, Δε is the dielectric anisotropy of the liquid crystal, V is the applied voltage, V _c is the threshold voltage of the thin film transistor, and K ₂ is the elastic modulus of the liquid crystal.

Equation 1 holds only when the intensity of the voltage applied to the liquid crystal panel can be kept constant. When the voltage is applied to the liquid crystal panel using the actual thin film transistor substrate, the response time is influenced by other factors because the voltage intensity is not kept constant.

FIG. 3 is a signal waveform diagram for describing a data signal when switching from black to white.

Referring to FIG. 3, whenever a gate signal is applied, a predetermined gray voltage is applied to the liquid crystal panel as a data signal. In the 1/60 second interval after the switch from black to white, the relationship shown in Equation 2 is established by the law of charge conservation.

Here, the voltage applied to the pixel when the gate signal is high is represented by V ₁ , and the voltage immediately before the gate signal becomes high next is represented by V ₂ . Further, C _st is the sum of the capacitances of the first and second sustain capacitors, C _lc (V ₁ ) is the capacitance of the liquid crystal capacitor at the voltage V ₁ , and C _lc (V ₂ ) is the capacitance of the liquid crystal capacitor at the voltage V _2. , ε (V ₁ ) means the dielectric constant of the liquid crystal at the voltage V ₁ , ε (V ₂ ) means the dielectric constant of the liquid crystal at the voltage V ₂ .

Referring to Equation 2, since ε (V ₁ ) is generally larger than ε (V ₂ ), the voltage V ₁ is increased to a significant level compared to the voltage of V ₂ . Therefore, a cusp occurs in the response waveform of the TN mode, and the response time is delayed.

4 is a graph illustrating a change in luminance over time when a switch is made from black to white. Referring to FIG. 4, it can be seen that a cusp occurs around 20 ms (a), thereby delaying a response time when switching from black to white.

The response time means the time taken to change from 10% to 90% of the luminance difference between the two gray levels when the gray level changes, so if the cusp is positioned above 90% of the final luminance, the response time decreases. It can be improved. Here, referring back to Equation 2, in order to reduce the rate of change of the voltage V ₂ , the capacitance of the sustain capacitor C _st must be greater than the capacitance of the liquid crystal capacitor C _lc . This is because if the capacitance of the sustain capacitor C _st is large enough, the influence of the change of the liquid crystal on the capacitance of the liquid crystal capacitance C _lc can be reduced.

5 is a graph illustrating a change in position of the cusp according to the ratio of the capacitance of the sustain capacitor C _st and the capacitance of the liquid crystal capacitor C _lc .

Referring to FIG. 5, it can be seen that the position of the cusp increases as the ratio of the capacitance of the sustain capacitor C _st to the capacitance of the liquid crystal capacitor C _lc increases. That is, it can be seen that the cusp is positioned at 90% or more when the ratio of the capacitance of the sustain capacitor C _st to the capacitance of the liquid crystal capacitor C _lc is about 0.55.

Table 1 is a table showing the change in the response time of the capacitance of the holding capacitor (C _st ) according to the ratio of the capacitance of the liquid crystal capacitor (C _lc ). As in FIG. 5, it can be seen that as the ratio of the capacitance of the sustain capacitor C _st to the capacitance of the liquid crystal capacitor C _lc increases, the position of the cusp rises and the response time decreases.

Device C _st / C _lc Cusp's location τ _on τ _off τ _total #One 0.37 82% 4.42 16.81 21.23 #2 0.44 87% 6.55 13.95 20.5 # 3 0.58 93% 4.32 9.95 14.27

Referring again to FIGS. 2A and 2B, since the storage capacitive electrode 70 is positioned above the gate insulating layer 30, the capacitance of the first storage capacitor 71 is applied to the thin film transistor substrate for a conventional liquid crystal display device. It becomes larger than that. That is, in the conventional thin film transistor substrate for liquid crystal display devices, since the storage capacitive electrode was formed at the same time as the gate wiring, a gate insulating film and a protective layer were used as the dielectric. However, since the thin film transistor substrate for the liquid crystal display according to the first embodiment of the present invention uses only the protective layer 80 as the dielectric, the capacitance of the first sustain capacitor 71 is increased.

Hereinafter, a method of manufacturing a thin film transistor substrate for a liquid crystal display according to a first embodiment of the present invention will be described with reference to FIGS. 6A to 9B, 2A, and 2B.

6A, 7A, 8A, and 9A are plan views illustrating a method of manufacturing a thin film transistor for a liquid crystal display according to a first embodiment of the present invention. FIG. 6B is a cross-sectional view taken along the line VIb-VIb ′ of FIG. 6A. FIG. 7B is a cross-sectional view taken along the line VIIb-VIIb 'of FIG. 7A. FIG. 8B is a cross-sectional view taken along the line 'b-'b' of FIG. 8A. FIG. 9B is a cross-sectional view taken along line VIIb-VIIb 'of FIG. 9A.

6A and 6B, first, gate wirings 22, 24, and 26 including a gate pad 24, a gate line 22, and a gate electrode 26 are formed on an insulating substrate 10. In the thin film transistor substrate for a liquid crystal display according to the first exemplary embodiment of the present invention, the double layer 24a, 24b, 26a, and 26b is formed, but is not limited thereto. A transparent conductive film such as indium tin oxide (ITO) or indium zinc oxide (IZO), an opaque conductive film such as aluminum (Al), molybdenum (Mo), and molybdenum-tungsten alloy (MoW) are sequentially deposited and then a photosensitive film is coated. . After the photoresist film is developed to form a photoresist pattern, the opaque conductive film and the transparent conductive film are sequentially etched by wet etching to form the gate wirings 22, 24, and 26 in the row direction. Thereafter, the photoresist pattern is removed by ashing.

Referring to FIGS. 7A and 7B, the silicon nitride (SiN _x ) is deposited to have a thickness of 1500 μm to 5000 A by using a chemical vapor deposition (CVD) method to form a gate insulating layer 30. Subsequently, the polysilicon layer and the polysilicon layer doped with n-type impurities are deposited to have a thickness of 500 mV to 1500 mV and 300 mV to 600 mV using the CVD method, respectively. The polysilicon layer and the polysilicon layer doped with n-type impurities are patterned by an etching process using a mask to form the semiconductor layer 40 and the ohmic contact layer 54.

8A and 8B, data lines 62, 64, 66, and 68 including a data pad 68, a data line 62, a source electrode 64, and a drain electrode 66 are formed. In the thin film transistor substrate for a liquid crystal display according to the first embodiment of the present invention, the storage capacitor electrode 70 is formed together with the data lines 62, 64, 66, and 68.

In the case of forming a double layer, chromium (Cr) / aluminum (Al) (or aluminum alloy) and aluminum (Al) in a pair of lower layers 62a, 64a, 66a and 70a and upper layers 62b, 64b, 66b and 70b, respectively. Molybdenum (Mo), chromium (Cr) or molybdenum-tungsten alloy (MoW) / aluminum (Al) are possible. Such metals are deposited to a thickness of 1500 kV to 3000 kV using a sputtering method. Thereafter, patterning is performed using an etching process using a mask to form the data lines 62, 64, 66, and 68 and the storage capacitive electrode 70. Here, the ohmic contact layer 54 (not shown) of the source electrode 64 and the drain electrode 66 is removed and separated into two parts 55 and 56.

9A and 9B, a protective layer 80 is formed by depositing silicon nitride (SiN _x ) or coating an organic insulating layer. Thereafter, the first to fourth contact holes 81, 82, 83, and 84 exposing the storage capacitive electrode 70 and the fifth contact hole 85 exposing the gate pad 24 are exposed using a dry etching process. ), A sixth contact hole 86 exposing the drain electrode 66 and a seventh contact hole 88 exposing the data pad 68 are formed.

Referring again to FIGS. 2A and 2B, a transparent conductive material such as an IZO film or an ITO film is deposited on the passivation layer 80 to a thickness of 400 kV to 500 kV using a sputtering method. Thereafter, the pixel electrode 90, the first and second bridges 91 and 92, the auxiliary gate pad 94, and the auxiliary data pad 98 are formed using an etching process using a mask.

Here, the pixel electrode 90 is electrically connected to the drain electrode 66 through the sixth contact hole 86, and the first bridge 91 has the first contact hole 81 and the third contact hole 83. The storage capacitive electrode 70 of the upper pixel and the lower pixel is electrically connected to each other through the insulating film. The second bridge 92 electrically connects the storage capacitor electrode 70 of the left pixel and the right pixel through the second contact hole 82 and the fourth contact hole 84. The auxiliary gate pad 94 and the auxiliary data pad 98 are electrically connected to the gate pad 24 and the data pad 68 through the fifth contact hole 85 and the seventh contact hole 88, respectively.

In the method of manufacturing a thin film transistor substrate for a liquid crystal display according to the first exemplary embodiment of the present invention, the storage capacitor electrode 70 is formed on the gate insulating layer 30 together with the data lines 62, 64, 66, and 68. Thus, the capacitance of the first sustain capacitor (see C _{st1 in} FIG. 1) can be increased. Therefore, it is possible to change the position of the cusp when the gradation changes, thereby preventing a decrease in response time.

10A is a plan view of a thin film transistor substrate for a liquid crystal display according to a second exemplary embodiment of the present invention. FIG. 10B is a cross-sectional view taken along the line VIIb-VIIb 'of FIG. 10A. 2A and 2B, the same reference numerals are used for the same elements, and detailed descriptions of the corresponding elements will be omitted.

10A and 10B, the storage capacitive electrode 70 has a first partial storage capacitive electrode 70c parallel to the gate line 22 and a second partial storage capacitive parallel to the data line 62. Electrode 70d. In the thin film transistor substrate 5 for a liquid crystal display device according to the second exemplary embodiment of the present invention, an end of the first partial capacitive electrode 70c is connected to an end of the second partial capacitive electrode 70d so as to be 'b'. 'It is made of a shape, but is not limited thereto.

In addition, the third bridge 93 electrically connects the storage capacitive electrode 70 of the upper pixel and the right pixel through the first contact hole 81, the fourth contact hole 84, and the eighth contact hole 87. Connect with

11A is a plan view of a thin film transistor substrate for a liquid crystal display according to a third exemplary embodiment of the present invention. FIG. 11B is a cross-sectional view taken along the line 'Ib-'Ib' of FIG. 10A. 2A and 2B, the same reference numerals are used for the same elements, and detailed descriptions of the corresponding elements will be omitted.

11A and 11B illustrate a case in which the source electrode 64 and the drain electrode 66 are formed as shown in order to prevent misalignment. In the thin film transistor substrate 6 for a liquid crystal display device according to the third exemplary embodiment of the present invention, an end of the first partial storage capacitive electrode 70c is connected to an end of the second partial storage capacitive electrode 70d, 'It is made of a shape, but is not limited thereto.

12A is a plan view of a thin film transistor substrate for a liquid crystal display according to a fourth embodiment of the present invention. FIG. 11B is a cross-sectional view taken along line IIb-IIb 'of FIG. 10A. 2A and 2B, the same reference numerals are used for the same elements, and detailed descriptions of the corresponding elements will be omitted.

12A and 12B illustrate a case in which the storage capacitive electrodes of pixels adjacent to the upper and lower parts are integrally formed without using a separate first bridge (see 91 of FIG. 2A). Since the storage capacitive electrode of the liquid crystal display thin film transistor substrate 7 according to the fourth embodiment of the present invention is not formed together with the gate wiring, it may be formed in this manner. Therefore, as in FIGS. 12A and 12B, the first contact hole (see 81 in FIG. 2A) may be omitted, and the pixel electrode 90 may be formed in a larger area.

13A is a plan view of a thin film transistor substrate for a liquid crystal display according to a fifth embodiment of the present invention. FIG. 13B is a cross-sectional view taken along the line IIIIII-IIIIII ′ of FIG. 13A. 10A and 10B, the same reference numerals are used for the same components, and detailed descriptions of the corresponding components will be omitted.

13A and 13B, the thin film transistor substrate 8 for a liquid crystal display according to the fifth embodiment of the present invention may be formed using four masks, unlike the first to fourth embodiments. Here, the semiconductor layers 40, 41, and 42 have the same side profile as the data wires 62, 64, 66, and 68, and the ohmic contact layers 55, 56, 57, and 58 except for the thin film transistor region. That is, although the source electrode 64 and the drain electrode 66 are disconnected in the thin film transistor region, the semiconductor layer 41 is connected to form a channel therein.

A thin film transistor substrate 8 for a liquid crystal display device according to a fifth embodiment of the present invention first uses a semiconductor layer, a metal layer, and the like on the gate insulating layer 30 in a continuous manner using, for example, a chemical vapor deposition (CVD) method. Deposit. Thereafter, the thickness of the photoresist pattern of the portion where the channel of the thin film transistor region is to be formed is made smaller than that of the other portion, and is etched collectively so that the semiconductor layers 40, 41, 42 and the ohmic contact layers 55, 56 57, 58, and data lines 62, 64, 66, 68 are formed.

Here, the method of varying the thickness of the photoresist film may form a slit or grid pattern or use a translucent film, but is not limited thereto. Here, the line width of the pattern located between the slits or the spacing between the patterns, that is, the width of the slits, is preferably smaller than the resolution of the exposure machine used during exposure, and in the case of using a translucent film, in order to control the transmittance when fabricating a mask. Thin films having different transmittances or thin films having different thicknesses may be used.

Although embodiments of the present invention have been described above with reference to the accompanying drawings, those skilled in the art to which the present invention pertains may implement the present invention in other specific forms without changing the technical spirit or essential features thereof. I can understand that. Therefore, it should be understood that the embodiments described above are exemplary in all respects and not restrictive.

According to the thin film transistor substrate for a liquid crystal display device and a method of manufacturing the same according to the present invention as described above has one or more of the following effects.

First, by forming the storage capacitive electrode on the gate insulating film, it is possible to increase the capacitance of the storage capacitor.

Second, it is possible to prevent a decrease in response time when the gray level changes.

Claims (15)

Insulating substrate; A gate line formed on the insulating substrate; A gate insulating film formed on the insulating substrate on which the gate line is formed; A data line formed on the gate insulating layer and crossing the gate line; A storage capacitive electrode formed on the gate insulating layer and formed of the same material as the data line; A protective layer formed on the insulating substrate on which the data line and the storage capacitive electrode are formed; And And a pixel electrode formed on the passivation layer, the pixel electrode overlapping at least a portion of the storage capacitive electrode. The method of claim 1, The storage capacitor electrode includes a first partial storage capacitive electrode parallel to the gate line and a second partial storage capacitive electrode parallel to the data line. The method of claim 2, The storage capacitive electrode of claim 1, wherein an end of the first partial storage capacitive electrode is connected to an end of the second partial storage capacitive electrode. The method of claim 2, The storage capacitive electrode of claim 1, wherein an end of the first partial storage capacitive electrode is connected to a middle of the second partial storage capacitive electrode. The method of claim 1, The storage capacitive electrode is a thin film transistor substrate for a liquid crystal display device formed on the same layer as the data line. The method of claim 1, And a plurality of bridges electrically connecting the storage capacitive electrodes of pixels adjacent to each other among the plurality of pixels formed in a matrix form on the insulating substrate. The method of claim 6, And the plurality of bridges include a first bridge electrically connecting the storage capacitive electrodes of pixels adjacent to left and right sides of a data line. The method according to claim 6 or 7, The plurality of bridges further includes a second bridge electrically connecting the storage capacitive electrodes of adjacent pixels to upper and lower gate lines. The method according to claim 7 or 8, And the first and second bridges are formed of the same material as the pixel electrode. Forming a gate line on the insulating substrate; Forming a gate insulating film on the gate line; Forming a storage capacitive electrode on the gate insulating layer, the data line crossing the gate line and the same material as the data line; Forming a protective layer on the insulating substrate on which the data line and the storage capacitive electrode are formed; Forming a pixel electrode at least partially overlapping the storage capacitive electrode on the passivation layer. The method of claim 10, wherein the forming of the data line and the storage capacitive electrode is performed. Forming a semiconductor layer on the gate insulating film; Forming a metal layer on the semiconductor layer; And collectively etching the semiconductor layer and the metal layer to form the data line and the storage capacitive electrode. The method of claim 10, And forming a plurality of bridges electrically connecting the storage capacitive electrodes of adjacent pixels among the plurality of pixels formed in a matrix form on the insulating substrate. The method of claim 12, Forming a first bridge electrically connecting the storage capacitive electrodes of pixels adjacent to left and right sides of the data lines forming the plurality of bridges. The method according to claim 12 or 13, The forming of the plurality of bridges further includes a second bridge electrically connecting the storage capacitive electrodes of adjacent pixels to upper and lower gate lines. The method according to claim 13 or 14, And the first and second bridges are formed simultaneously with the pixel electrode.

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