KR20050000681A - Liquid Crystal Display and method for fabricating of the same - Google Patents

Abstract

PURPOSE: An array substrate of an LCD(Liquid Crystal Display) and a method for manufacturing the array substrate are provided to reduce resistance of data lines by forming the data lines in a manner that an insulating layer is etched to form grooves and the data lines are formed in the grooves. CONSTITUTION: An array substrate of an LCD includes gate lines, an insulating layer(110) formed on the gate lines, data lines(122), thin film transistors, and transparent pixel electrodes(128). The gate lines are extended in one direction on a substrate(100). The insulating layer has etched grooves formed in portions that do not correspond to the gate lines and arranged in a direction perpendicular to the gate lines. The data lines are formed in the etched grooves of the insulating layer and intersect the gate lines. The thin film transistors are located at intersections of the gate lines and data lines. The pixel electrodes are respectively connected to the thin film transistors.

Description

Liquid Crystal Display and method for fabricating of the same}

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a liquid crystal display device, and relates to a configuration of a liquid crystal display device array substrate including low resistance wiring and a manufacturing method thereof.

In general, the liquid crystal display device is an apparatus for displaying an image by controlling the amount of light emitted downward to the outside through the liquid crystal by using the arrangement characteristics of the liquid crystal that changes when the intensity of the electric field distribution is changed.

To this end, a liquid crystal panel is usually divided into an array substrate and a color filter substrate, and the array substrate is vertically intersected so that data lines and gate lines are defined to define pixel regions, and at the intersection of the two lines, that is, on one side of a single pixel. The thin film transistor is positioned, and a transparent pixel electrode is formed for each pixel.

A transparent common electrode is formed on the front surface of the color filter substrate, and color filters corresponding to different colors are formed corresponding to each pixel.

In the above-described configuration, the thin film transistor receives a signal from the gate line and the data line, and the signal of the data line is transmitted to the pixel electrode through the thin film transistor according to the signal of the gate line.

Accordingly, the liquid crystals are arranged between the pixel electrode and the common electrode according to the generated electric field, and light is transmitted according to the arrangement of the liquid crystal to display an image.

Hereinafter, the configuration of the above-described array substrate will be described in more detail with reference to FIG. 1.

1 is an enlarged plan view showing a part of an array substrate for a liquid crystal display device.

(The arrangement of the array substrate may be modified in various ways. The configuration of FIG. 1 will be described by taking an example of the arrangement of an array substrate having a top gate type thin film transistor as a switching element.)

As shown in the drawing, a thin film transistor T, which is a switching element, is positioned in a matrix type on a transparent insulating substrate 10 (glass or plastic), and the gate wiring intersects the plurality of thin film transistors T. 18 and data wirings 26 are formed.

The plurality of regions defined as the plurality of gate lines 18 and the data lines 26 intersecting and spaced apart in parallel to each other is referred to as a pixel area P. FIG.

The pixel region P includes a transparent pixel electrode 30 connected to the thin film transistor T.

In the above-described configuration, the thin film transistor T is described by taking a coplanar structure having a top gate shape as an example.

The coplanar structure forms a semiconductor layer (generally formed of polysilicon) 12, and then forms a gate electrode 16 on the semiconductor layer 12, and on both sides of the gate electrode 16. The source electrode 22 and the drain electrode 24 in contact with the semiconductor layer 12 are disposed with an insulating film (not shown) therebetween.

Hereinafter, with reference to FIG. 2, the cross-sectional structure of the array substrate comprised as mentioned above is demonstrated.

FIG. 2 is a cross-sectional view taken along the line II-II ′ of FIG. 1.

As shown, the substrate 10 is defined by a thin film transistor region T and a pixel region P. As shown in FIG.

The active layer 12 is formed of polysilicon on the substrate 10 corresponding to the thin film transistor region T.

The active layer 12 may be divided into a first active region A1 and a second active region A2 on both sides of the first active region A1.

The gate electrode 16 is formed on the first active region A1 with the gate insulating layer 14 interposed therebetween. At this time, although not shown, a gate line 18 of FIG. 1 is formed at the same time as the gate electrode 16.

An interlayer insulating film 20 is formed on the gate electrode 16, and the interlayer insulating film 20 and the gate insulating film 14 below are etched to form second actives on both sides of the first active region A1. The first contact hole CH1 and the second contact hole CH2 exposing the region A2 are formed.

A source electrode 22 and a drain electrode 24 are formed on the interlayer insulating layer 20 to contact the lower second active region A2 through the first and second contact holes CH1 and CH2. .

At the same time, a data line 26 is formed in contact with the source electrode 22 and vertically intersects the gate line (18 in FIG. 1) and the interlayer insulating film 20 therebetween.

The passivation layer 28 exposing a part of the drain electrode 24 is formed on the substrate 20 including the source and drain electrodes 22 and 24 and the data line 26. In the upper portion, the pixel electrode 30 is in contact with the exposed drain electrode 24.

As described above, an array substrate for a liquid crystal display device is constructed.

In the above-described configuration, the gate wiring (18 in FIG. 1) and the data wiring 26 should take into account the respective resistance as the liquid crystal panel faces to the face.

In other words, the larger the resistance of the two wirings, the more the signal delay occurs, which causes uneven image quality on the front surface of the liquid crystal panel.

Therefore, in order to prevent such a signal delay, in the past, when the gate wiring (18 in FIG. 1) and the gate electrode 16 are formed, an aluminum-based metal having a very low resistance and low cost is used. The drain electrodes 22 and 24 and the data line 26 are limited in using aluminum (Al).

because. The semiconductor layer 12 is present under the source and drain electrodes 22 and 24. When the source and drain electrodes 22 and 24 are used as aluminum, the spy into which the aluminum penetrates into the semiconductor layer 12 is formed. There is a problem in that a spiking phenomenon is caused to cause the operation of the thin film transistor.

In order to solve this problem, low-resistance wiring materials such as copper (Cu), silver (Ag), and gold (Au) may be used as the source and drain electrodes 22 and 24 and the data wiring 26. (Cu) Likewise, the aluminum (Al) has many restrictions in terms of properties. The silver and gold are too expensive and practical in that they are free from chemical and physical constraints.

Therefore, as a method of easily lowering the resistance of the data line 26, a method of increasing the width of the data line 26 has been proposed, but this is not only the width of the data line 26 but also an alignment of + α. Since the margin (align margin) must be designed, there is a problem of significantly lowering the aperture ratio of the liquid crystal panel.

As a result, although the resistance can be lowered, there is a problem of causing a deterioration in image quality due to a decrease in aperture ratio.

The present invention has been made for the purpose of solving the above-described problems, when configuring the data wiring, without forming a separate process by etching the lower insulating film to form a groove, the inner surface of the groove A structure for forming a data line and a method of manufacturing the same are proposed.

As described above, since the area occupied by the data wirings is still intact as compared with the conventional art, the area of the data wirings can be expanded, so that the resistance of the wiring can be significantly reduced.

Therefore, there is an advantage that can produce a high-quality large area liquid crystal panel.

1 is an enlarged plan view showing a part of an array substrate for a liquid crystal display device;

FIG. 2 is a cross-sectional view taken along the line II-II ′ of FIG. 1;

3 is an enlarged plan view showing a part of an array substrate for a liquid crystal display device according to the present invention;

4A to 4F are cross-sectional views illustrating a process sequence of the present invention, taken along line IV-IV ′ of FIG. 3.

<Description of Symbols for Major Parts of Drawings>

100 substrate 102 buffer layer

104 semiconductor layer 106 gate insulating film

108 gate electrode 110 interlayer insulating film

118 source electrode 120 drain electrode

122: data wiring 124: protective film

126: pixel electrode

An array substrate for a liquid crystal display device for achieving the above object includes a gate wiring extending in one direction on the substrate; An insulating layer disposed on the gate wiring and having an etching groove formed in a direction perpendicular to the gate wiring in a portion other than the gate wiring; A data line extending vertically across the insulating film on the insulating film, the data wiring being formed on an inner surface of the etching groove of the insulating film; A thin film transistor positioned at an intersection point of the gate line and the data line; It includes a transparent pixel electrode connected to the thin film transistor.

The thin film transistor is configured in the form of an active layer, a gate electrode over the active layer, a source and a drain electrode in contact with the active layer, or a gate electrode, an active layer formed over the gate electrode, and positioned above the active layer. It is configured in the form of a source electrode and a drain electrode spaced apart therefrom.

According to an aspect of the present invention, there is provided a method of manufacturing an array substrate for a liquid crystal display device, the method including: forming a gate wiring extending in one direction on the substrate; Forming an insulating film on the substrate including the gate wiring, wherein the insulating groove is formed at a portion except the gate wiring in a direction perpendicular to the gate wiring; Forming a data line on an inner surface of the etch groove of the insulating layer and extending perpendicularly to the gate line on the insulating layer; Forming a thin film transistor at an intersection point of the gate line and the data line; Forming a transparent pixel electrode connected to the thin film transistor.

According to another aspect of the present invention, there is provided a method of manufacturing an array substrate for a liquid crystal display device, the method comprising: defining a plurality of pixel regions on a substrate and a switching region on one side of the pixel region; Forming an island-like semiconductor layer corresponding to the switching region; Forming a gate insulating film on an entire surface of the substrate on which the semiconductor layer is formed; Forming a gate electrode on the gate insulating layer over the semiconductor layer and a gate wiring connected to the gate electrode and extending to one side of the pixel region; Forming an ohmic contact layer by doping n + or p + impurities to the surface of the semiconductor layer except for the portion where the gate electrode is located; Forming an interlayer insulating film on an entire surface of the substrate on which the gate electrode and the gate wiring are formed; Etching the interlayer insulating film and the gate insulating film to form first and second contact holes exposing the ohmic contact layer to both sides of the gate electrode, and forming an etching groove in a direction perpendicular to the gate wiring; ; Source and drain electrodes spaced apart from each other while being in contact with the exposed ohmic contact layer, and contacting the source electrodes to extend in a direction perpendicular to the gate wiring and at the same time to form a data wiring contacting an inner surface of the etch groove. Steps; Forming a passivation layer on a front surface of the substrate on which the source and drain electrodes and the data line are formed to expose a portion of the drain electrode; And forming a transparent pixel electrode positioned in the pixel region while contacting the exposed drain electrode.

Hereinafter, exemplary embodiments of the present invention will be described with reference to the accompanying drawings.

Example

When the data line is formed, the data line is formed in the etching groove formed by etching the lower insulating film.

3 is an enlarged plan view schematically illustrating a configuration of an array substrate for a liquid crystal display device according to the present invention.

As shown in the drawing, the gate line 110 extending in one direction on the transparent insulating substrate 100 and the gate line 110 defining the pixel region P are perpendicularly intersected with each other.

A thin film transistor T including a gate electrode 108, an active layer 104, a source electrode 118, and a drain electrode 120 is formed at an intersection point of the gate line 110 and the data line 122. .

In this case, the gate electrode 108 is connected to the gate wiring 110, and the source electrode 118 is configured to be connected to the data wiring 122.

The pixel region P includes a transparent pixel electrode 128 in contact with the drain electrode 118.

In the above-described configuration, it is characteristic that the etching groove 116 is formed under the data wiring 122, and the data wiring 122 is formed on the inner surface of the etching groove 116.

Such a configuration results in widening the area of the data line 122 while taking the area occupied by the data line 122 in the same manner as before, and this structure can significantly lower the resistance of the data line 122. Make sure

4A to 4F, a manufacturing process of an array substrate for a liquid crystal display device according to the present invention having the planar configuration as described above will be described.

4A to 4F are cross-sectional views taken along the line IV-IV ′ of FIG. 3 and according to the process sequence of the present invention.

As shown in FIG. 4A, as shown, first, silicon nitride (SiN _x ) or silicon oxide (SiO ₂ ) is deposited on the substrate 100 to form a buffer layer 102.

The buffer layer 102 is useful when the substrate 100 is an alkali metal. In detail, when heat is applied to the substrate 100, the metal wiring formed on the substrate 100 is not affected by the alkali metal eluted to the surface of the substrate 100.

Subsequently, an island-like polysilicon pattern 104 is formed in the switching region T on the buffer layer 102.

The polysilicon pattern 104 is fabricated by applying heat after depositing an amorphous silicon layer. The most common method is a low temperature silicon crystallization method using a laser.

Optionally, the polysilicon pattern 104 is defined as a first active region A1 and a second active region A2 on both sides of the first active region A1.

As shown in FIG. 4B, one selected from the group of inorganic insulating materials including silicon nitride (SiN _X ) and silicon oxide (SiO ₂ ) is deposited on the entire surface of the substrate 100 on which the polysilicon pattern 104 is formed. The gate insulating film 106 is formed.

Next, the gate electrode 108 is formed on the gate insulating layer 106 corresponding to the first active region A1, and the gate wiring 110 connected to the gate electrode 108 in one direction is formed. Form an extension.

Although not represented, the gate electrode 108 and the gate wiring 110 generally include a double layer in which a low resistance aluminum-based metal and a buffer metal layer protecting the same are laminated to prevent signal delay.

This is because the aluminum-based metal is low in resistance but chemically poor in corrosion resistance and thus has a disadvantage of being easily corroded.

Next, a process of doping the second active region A2 of n + or p + is performed by using the gate electrode as an anti-doping film.

Finally, the second active region A2 can function as an ohmic contact layer.

As shown in FIG. 4C, an inorganic insulating layer including silicon nitride (SiN _x ) and silicon oxide (SiO ₂ ) is formed on the entire surface of the substrate 100 on which the gate electrode 108 and the gate wiring 110 (in FIG. 3) are formed. One selected from the group of materials is deposited to form the interlayer insulating layer 110.

Next, the interlayer insulating layer 110 may be patterned to expose the first active hole 112 and the second active region A2 of the polysilicon pattern 104 on both sides of the gate electrode 108. The contact hole 114 is formed.

At the same time, the etching groove 116 is formed in a direction perpendicular to the direction in which the gate wiring 110 is formed.

In this case, the etching groove 116 may or may not be formed on the gate wiring 110 (see FIG. 3).

As shown in FIG. 4D, chromium (Cr), molybdenum (Mo), tungsten (W), titanium (Ti), neodymium (Nd), and the like are formed on the entire surface of the substrate 100 on which the etching groove 116 is formed. Depositing and patterning a selected one of the conductive metal groups, and contacting the data line 122 perpendicularly intersecting the gate line 110 and the exposed second active region A2. The source electrode 118 and the drain electrode 120 are formed.

In this case, the data line 122 is patterned to form an inner surface of the etching groove 116.

In this case, the width of the etch groove 116 is the same as the width occupied by the conventional data line 122, but since the data line 122 is formed on the inner surface of the etch groove 116 is larger than the conventional area Results that can be constructed.

As shown in FIG. 4E, an inorganic insulating material including silicon nitride (SiN _X ) and silicon oxide (SiO ₂ ) is formed on the entire surface of the substrate 100 on which the data line 122 and the source and drain electrodes 118 and 120 are formed. A protective film 124 composed of a single layer or multiple layers of insulating films is formed by depositing / coating one selected from the group or a group of organic insulating materials including benzocyclobutene (BCB) and an acrylic resin resin. .

Next, the passivation layer 124 is patterned to form a drain contact hole 126 exposing a part of the drain electrode 120.

As shown in FIG. 4F, one of a transparent conductive metal group including indium tin oxide (ITO) and indium zinc oxide (IZO) on the entire surface of the substrate 100 on which the passivation layer 124 is formed. Deposited and patterned to form a pixel electrode 128 in contact with the exposed drain electrode 120.

Through the process as described above it can be produced an array substrate for a liquid crystal display device according to the present invention.

The above-described process is a method of increasing the area of the data wiring without additional processes in the method of manufacturing an array substrate including a thin film transistor having a general top gate type structure.

However, since the structure of the data wiring is applicable to the configuration of a general array substrate, all of the array substrate configurations having such a structure should be considered as an application object.

When manufacturing an array substrate for a liquid crystal display device according to the present invention,

First, when forming the data wiring, an etch groove is formed under the data wiring, and the data wiring is formed on the inner side of the etching groove, so that the area of the data wiring is equal while the area occupied by the data wiring is the same as in the prior art. Since it can be made large, the resistance of a data wiring can be remarkably reduced without lowering an aperture ratio.

Second, since the resistance of the data wiring can be significantly reduced, there is an effect that can produce a high-quality liquid crystal panel.

Third, since the resistance of the data line can be significantly reduced, there is an effect that a large area liquid crystal panel can be manufactured.

Fourth, since there is no need to use a separate expensive metal to reduce the resistance of the data wiring and no process is added, there is an effect of improving the process yield.

Claims (12)

A gate wiring extending in one direction on the substrate; An insulating layer disposed on the gate wiring and having an etching groove formed in a direction perpendicular to the gate wiring in a portion other than the gate wiring; A data line extending vertically across the insulating film on the insulating film, the data wiring being formed on an inner surface of the etching groove of the insulating film; A thin film transistor positioned at an intersection point of the gate line and the data line; Transparent pixel electrode connected to the thin film transistor Array substrate for a liquid crystal display device comprising a. The method of claim 1, And the thin film transistor includes an active layer, a gate electrode over the active layer, and source and drain electrodes in contact with the active layer. The method of claim 1, The thin film transistor includes a gate electrode, an active layer and an ohmic contact layer stacked on the gate electrode, a source electrode positioned on the ohmic contact layer, and a drain electrode spaced apart from the predetermined distance. Forming a gate wiring extending in one direction on the substrate; Forming an insulating film on the substrate including the gate wiring, wherein the insulating groove is formed at a portion except the gate wiring in a direction perpendicular to the gate wiring; Forming a data line on an inner surface of the etch groove of the insulating layer and extending perpendicularly to the gate line on the insulating layer; Forming a thin film transistor at an intersection point of the gate line and the data line; Forming a transparent pixel electrode connected to the thin film transistor Array substrate manufacturing method for a liquid crystal display device comprising a. The method of claim 4, wherein And the thin film transistor comprises an active layer, a gate electrode over the active layer, and source and drain electrodes in contact with the active layer. The method of claim 4, wherein The thin film transistor may include a gate electrode, an active layer and an ohmic contact layer stacked on the gate electrode, a source electrode located on the ohmic contact layer, and a drain electrode spaced apart from the predetermined gap. . The method of claim 4, wherein And the insulating film is formed of one selected from the group of inorganic insulating materials including silicon nitride (SiN _X ) and silicon oxide (SiO ₂ ). The method of claim 4, wherein And the transparent pixel electrode is formed of one selected from a group of transparent conductive metals including indium tin oxide (ITO) and indium zinc oxide (IZO). Defining a plurality of pixel regions on the substrate and a switching region on one side of the pixel region; Forming an island-like semiconductor layer corresponding to the switching region; Forming a gate insulating film on an entire surface of the substrate on which the semiconductor layer is formed; Forming a gate electrode on the gate insulating layer over the semiconductor layer and a gate wiring connected to the gate electrode and extending to one side of the pixel region; Forming an ohmic contact layer by doping n + or p + impurities to the surface of the semiconductor layer except for the portion where the gate electrode is located; Forming an interlayer insulating film on an entire surface of the substrate on which the gate electrode and the gate wiring are formed; Etching the interlayer insulating film and the gate insulating film to form first and second contact holes exposing the ohmic contact layer to both sides of the gate electrode, and forming an etching groove in a direction perpendicular to the gate wiring; ; Source and drain electrodes spaced apart from each other while being in contact with the exposed ohmic contact layer, and contacting the source electrodes to extend in a direction perpendicular to the gate wiring and at the same time to form a data wiring contacting an inner surface of the etch groove. Steps; Forming a passivation layer on a front surface of the substrate on which the source and drain electrodes and the data line are formed to expose a portion of the drain electrode; Forming a transparent pixel electrode positioned in the pixel region while contacting the exposed drain electrode Array substrate manufacturing method for a liquid crystal display device comprising a. The method of claim 9, And the polysilicon pattern is crystallized by heat-treating amorphous silicon. The method of claim 9, And the gate insulating film and the interlayer insulating film are formed of one selected from the group of inorganic insulating materials including silicon nitride (SiN _X ) and silicon oxide (SiO ₂ ). The method of claim 9, And the transparent pixel electrode is formed of one selected from a group of transparent conductive metals including indium tin oxide (ITO) and indium zinc oxide (IZO).